Integrated circuit device

Abstract

The utility model provides an integrated circuit device which comprises a first transistor placed on the front side of a semiconductor substrate. The first transistor includes a first gate, a first epitaxial region, and a second epitaxial region, a first channel extending between the first epitaxial region and the second epitaxial region and passing through the first gate, and a first metal-like device directly overlying the first epitaxial region and the second epitaxial region, respectively, mD) fragments and second type metal defining fragments. A first power rail is located on a backside of the semiconductor substrate, a first via structure extends from the first epitaxial region to the first power rail, and a second via structure extends from the first metal-defining segment to the first power rail.

Description

TECHNICAL FIELD

[0001] The utility model relates to an integrated circuit device. BACKGROUND

[0002] The continuing trend of miniaturization of integrated circuits has resulted in devices that consume less power as they grow smaller, but provide more functionality at higher speeds than earlier generations of technology. This miniaturization is achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify designs of semiconductor devices while ensuring that the IC structural design and manufacturing specifications are met. SUMMARY

[0003] The utility model provides a kind of integrated circuit device, including the first transistor on the front side of semiconductor substrate, the first transistor includes first gate, first epitaxial region and second epitaxial region, first channel extends between the first epitaxial region and the second epitaxial region and passes through the first gate, and first metal definition segment of the first type and second metal definition segment of the first type are directly overlaid the first epitaxial region and the second epitaxial region respectively, first power rail on the back side of the semiconductor substrate, first via structure extending from the first epitaxial region to the first power rail, and second via structure extending from the first metal definition segment of the first type to the first power rail.

[0004] The utility model provides a kind of integrated circuit device, including the first multiple gate structures extending along a first direction on the front side of semiconductor wafer, multiple first epitaxial regions are aligned with each other between corresponding gate structure in the first multiple gate structures and in the second direction perpendicular to the first direction, multiple first metal definition segments of the first type extend along the first direction and directly overlay corresponding first epitaxial region in the multiple first epitaxial regions, first power rail extends along the second direction on the back side of the semiconductor wafer, multiple first via structures extend from the first power rail to corresponding first epitaxial region in the multiple first epitaxial regions, and multiple second via structures extend from the first power rail to corresponding first metal definition segment in the multiple first metal definition segments of the first type.

[0005] To let the above-mentioned features and advantages of the utility model more obvious and easy to understand, below text example is held, and cooperation figure is as follows detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the application, or the present application, can best be understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the clarity of discussion.

[0007] Figure 1A and Figure 1B are plan and cross-sectional views of an IC layout and corresponding IC device, respectively, according to some embodiments.

[0008] Figures 2A to 2C are plan and cross-sectional views of an IC layout and corresponding IC device, respectively, according to some embodiments.

[0009] Figure 3 is a plan view of an IC layout and corresponding IC device, according to some embodiments.

[0010] Figure 4 is a plan view of an IC layout and corresponding IC device, according to some embodiments.

[0011] Figure 5A and Figure 5B are plan views of an IC layout and corresponding IC device, respectively, according to some embodiments.

[0012] Figure 6 is a plan view of an IC layout and corresponding IC device, according to some embodiments.

[0013] Figure 7 is a flowchart of a method of manufacturing an IC device, according to some embodiments.

[0014] Figure 8 is a flowchart of a method of generating an IC layout, according to some embodiments.

[0015] Figure 9 is a block diagram of an IC layout generation system, according to some embodiments.

[0016] Figure 10 is a block diagram of an IC manufacturing system and IC manufacturing flow associated therewith, according to some embodiments.

[0017] BRIEF DESCRIPTION OF DRAWINGS

[0018] 100, 200A, 200B, 300, 400: IC layout / device

[0019] 100C, 200AC, 200BC, 200C, 400C: cell

[0020] 400PX, 400PY: pitch cell

[0021] 700, 800: method

[0022] 702, 704, 706, 708, 710, 712, 802, 804, 806, 808: operation

[0023] 900: IC layout generation system

[0024] 902: processor

[0025] 904: computer readable storage medium

[0026] 906: computer program code / instructions

[0027] 907: cell library

[0028] 908: bus

[0029] 909: layout

[0030] 910: I / O interface

[0031] 912: network interface

[0032] 914: network

[0033] 942: user interface

[0034] 1000: IC manufacturing system

[0035] 1020: design company

[0036] 1022: IC design layout

[0037] 1030: photomask company

[0038] 1032: data preparation

[0039] 1044: photomask manufacturing

[0040] 1045: photomask

[0041] 1050: IC foundry

[0042] 1052: manufacturing tool

[0043] 1053: semiconductor wafer

[0044] 1060: IC device

[0045] M0A, M0B: front side metal region / segment

[0046] BM0A, BM0B: back side metal region / segment

[0047] MD: metal-like defined region / segment

[0048] CMD: Metal Definition Cut Zone

[0049] GS: Gate Zone / Structure

[0050] CP: Cut Zone for Gate

[0051] CL: Channel

[0052] FTV: Feed Through Via / Hole Zone / Structure

[0053] VB, VG, VD, VDR: Via Hole Zone / Structure

[0054] AA1, AA2: Active Zone / Area

[0055] N: n-Active Zone / Area

[0056] P: p-Active Zone / Area

[0057] DOD: Dummy Active Zone / Area

[0058] TX: Transistor

[0059] VDD: Supply Voltage

[0060] VSS: Reference Voltage

[0061] AAS, FAS: Spacing

[0062] PG: Power Grid Track

[0063] SUB: Semiconductor Substrate / Wafer

[0064] CH: Cell Height

[0065] P0: Pitch

[0066] D1, D2, D4, D5, D6a, D6b, D7a, D7b: Width

[0067] D3, D3a, D3b: Distance

[0068] X: X-Dimension

[0069] Y: Y-Dimension

[0070] Z: Z-Dimension

[0071] A-A’: A-A’ Section Line

[0072] B-B’: B-B’ Section Line DETAILED DESCRIPTION

[0073] The present utility model content provides for implementing the different features of the different embodiments or examples of the present utility model. The following specific examples of components and arrangements are set forth to simplify the present utility model. Of course, these are only examples and are not intended to be limiting. For example, the formation of a first feature on or over a second feature in the following description can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature so that the first feature and the second feature can not be in direct contact. In addition, the present utility model can repeatedly use reference numbers and / or letters in various examples. Such repeated use is for the purpose of brevity and clarity and is not intended to convey a relationship between the various embodiments and / or configurations discussed.

[0074] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for describing the relationship between one component or feature to another component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. The device can have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0075] In various embodiments, an IC device and method of fabrication based on an IC layout includes a structure (e.g., a transistor) on a front side of a semiconductor substrate, the structure including a gate, first and second epitaxial regions, a channel extending between the first and second epitaxial regions and through the gate, and first and second metal- like defined (MD) segments directly overlying the first and second epitaxial regions. A power rail is on a back side of the semiconductor substrate, a first via structure (e.g., a backside via) extends from the first epitaxial region to the power rail, and a second via structure (e.g., a feed-through via (FTV)) extends from the first metal- like defined segment to the power rail.

[0076] Thus, as compared to a plurality of parallel arrangements of a plurality of via structures not included in a plurality of electrical paths from a plurality of power rails to a plurality of front side structures, an electrical path from a power rail to a first metal- like defined segment includes a parallel arrangement of two via structures, and thus a two-via path resistance is reduced. As compared to such other approaches, the reduced path resistance acts to reduce a parasitic voltage drop (i.e., an IR voltage drop) due to current flow.

[0077] As discussed below, in some embodiments, Figure 1A 、 Figure 2A 、 Figure 2B and Figures 3 to 6 are shown as plan views and Figure 1B and 2C are shown as cross-sectional views. Figures 1A to 6 Each of the figures in Figure 7 is a device / layout figure, where reference numerals represent both IC device features and IC layout features used to at least partially define corresponding IC device features in a fabrication flow (e.g., the method 700 discussed below with reference to Figure 10 and / or the IC fabrication flow related to the IC fabrication system 1000 discussed below with reference to Figures 1A to 6 In some embodiments, Figure 8 one or more of the figures in Figures 1A to 6 Each of the figures in

[0078] For illustration, each of the figures herein (e.g., Figures 1A to 6 ) is simplified. The figures are views of IC structures and devices that include and exclude various features to facilitate the discussion below. In various embodiments, the IC structures, devices, and / or layout figures include one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain structures or other transistor elements, isolation structures, and so on, in addition to the features illustrated in Figures 1A to 6 .

[0079] Figures 1A to 6 The positioning and relative sizing of the various features illustrated in Figures 1A to 6 include features positioned and / or sized otherwise within the corresponding IC layout / device.

[0080] Figure 1A and Figure 1B are plan and cross-sectional views (along the A-A’ crossline of Figure 1A ) of an IC layout 100 and a corresponding IC device 100, respectively, according to some embodiments. Figure 2A is a plan view of an IC layout 200A and a corresponding IC device 200A, according to some embodiments, and Figure 2B and Figure 2C are plan and cross-sectional views (along the A-A’ crossline of Figure 2Bof B-B’). In some embodiments, the IC layout and corresponding device 200A and 200B are collectively referred to as IC layout 200 and IC device 200.

[0081] Each of the views of IC layout / device 100 or 200 includes an X and Y direction, and Figure 1A , Figure 2A and Figure 2B Each of the views of IC layout / device 100 or 200 includes an X and Y direction, and Figure 1B and Figure 2C includes a Y direction and a Z direction.

[0082] Each of IC layout / device 100 and 200 includes a portion of a semiconductor substrate SUB, also referred to in some embodiments as a substrate SUB, a semiconductor wafer SUB, or a wafer SUB. The substrate SUB includes a Frontside and a Backside, each corresponding to a subset of features contained in IC layout / device 100 or 200, as shown in and discussed below with respect to Figures 1A to 3 .

[0083] IC layout / device 100 corresponds to an embodiment of cell 100C including two instances of active area / region AA1 and one instance of active area / region AA2, and IC layout / device 200 corresponds to an embodiment of cell 200AC or 200BC including two instances of active area / region AA2. In some embodiments, cell 100C is referred to as a PNNP, PNP, NPPN, or NPN cell, and / or cell 200AC or 200BC (collectively referred to in some embodiments as cell 200C) is referred to as a PPNN or NNPP cell.

[0084] Each of cells 100C and 200C also includes a metalloid-defined region / segment MD, a metalloid-defined cut region CMD, a gate region / structure GS, a gate cut region CP, a feedthrough via region / structure FTV, a backside via region / structure VB, and a via region / structure VDR, and in some embodiments a via region / structure VD and / or VG, configured as described below.

[0085] Each of the IC layouts / devices 100 and 200 also includes instances of front-side metal regions / segments M0A and M0B, also referred to in some embodiments as front-side metal zero regions / segments M0A and M0B or metal zero regions / segments M0A and M0B, and instances of back-side metal regions / segments BM0A and BM0B, also referred to in some embodiments as back-side metal zero regions / segments BM0A and BM0B, back-side power rails BM0A and BM0B, or power rails BM0A and BM0B. In some embodiments, one or more of the front-side metal regions / segments M0A and / or M0B, and / or the back-side metal regions / segments BM0A and / or BM0B are included in the corresponding one or more cells 100C or 200C.

[0086] In some embodiments, the front-side metal regions / segments M0A and M0B correspond to separate front-side photomask modules, e.g., configured to enable metal region / segment pitches smaller than based on metal region / segment pitches of a single photomask module.

[0087] In some embodiments, the back-side metal regions / segments BM0A and BM0B correspond to separate back-side photomask modules, e.g., separate distribution paths for power and reference voltages.

[0088] In Figures 1A to 6 In some cases, not all instances of a given feature are labeled, e.g., a single instance, for clarity.

[0089] An active region / area (e.g., active region / area AA1 or AA2) is an area in an IC layout that is taken into a fabrication process as a part of defining an active area, also referred to as oxide diffusion or definition (OD), either directly in a substrate SUB or in an n-well or p-well (not shown), in which one or more IC device features, e.g., source / drain (S / D) structures (not shown), are formed. In some embodiments, an active area is an n-type or p-type active area of a planar transistor, a fin field-effect transistor (FinFET), or a gate-all-around (GAA) transistor. In various embodiments, an active area (structure) includes one or more semiconductor materials (e.g., silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), etc.), acceptor dopants (e.g., boron (B) or aluminum (Al)), or donor dopants (e.g., phosphorus (P) or arsenic (As)), or another suitable material.

[0090] In some embodiments, an active region / area is an area in the IC layout that is incorporated into the fabrication process as part of defining a nano-sheet structure, e.g., a contiguous volume of one or more layers of a semiconductor material having n-type or p-type doping. In various embodiments, each nano-sheet layer comprises a single monolayer or multiple monolayers of a given semiconductor material.

[0091] In some embodiments, a portion of an active region / area (e.g., an epitaxial region) corresponds to a source / drain structure (also referred to in some embodiments as a source / drain terminal) of a transistor. In some embodiments, an active region / area includes one or more channel regions (e.g., channel CL), a portion of an active region / area (e.g., an epitaxial region), extends through a gate structure and between multiple source / drain terminals in a transistor (e.g., a GAA transistor), thereby configured as a conduction path between the multiple source / drain terminals that is controllable by the gate structure.

[0092] A gate region / structure (e.g., gate region / structure GS) is an area in the IC layout that is incorporated into the fabrication process as part of defining a gate structure. A gate structure is a volume comprising one or more electrically conductive segments (e.g., gates) comprising one or more conductive materials, e.g., polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, the one or more electrically conductive segments thereby configured to control a voltage provided at an adjacent gate dielectric layer.

[0093] A dielectric layer (e.g., a gate dielectric layer) is a volume comprising one or more insulating materials (e.g., silicon dioxide, silicon nitride (Si3N4)), and / or one or more other suitable materials (e.g., a low dielectric material having a k-value less than 3.8, or a high dielectric material having a k-value greater than 3.8). For example, aluminum oxide (AI2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable to provide a high resistance between IC structure elements, i.e., a resistance level above a predetermined threshold, corresponding to one or more error levels based on the effect of resistance on circuit performance.

[0094] In various embodiments, a gate dielectric layer has a substantially planar shape (e.g., as part of a planar transistor), a shape corresponding to a transistor topology (e.g., as part of a FinFET), or a substantially cylindrical shape (e.g., as part of a GAA transistor), whereby a distance by which a gate is separated from a corresponding channel region is large enough to limit current to a specified level, and small enough to enable an electric field in the channel having a specified electric field strength.

[0095] A cut-gate region (e.g., cut-gate region CP) is also referred to as a cut-poly region in some embodiments, is a region in the IC layout that is incorporated into the manufacturing process as part of defining a break in the gate of a given gate structure, e.g., a portion that is etched away after the gate is deposited, thereby electrically isolating the corresponding adjacent portions of the gate from each other.

[0096] A metal definition region / segment (e.g., metal definition region / segment MD) is a conductive region in the IC layout that is incorporated into the manufacturing process as part of defining a metal definition segment, also referred to as a conductive segment or metal definition conductive line or trace, in and / or on the semiconductor substrate and capable of being electrically connected to underlying source / drain structures and / or underlying and / or overlying via structures. In some embodiments, the metal definition segment includes a portion of at least one metal layer (e.g., a contact layer) that overlies and contacts the substrate and has a thickness that is sufficiently small to enable an insulating layer to be formed between the metal definition segment and the overlying metal layer. For example, a first or lowermost metal layer. In various embodiments, the metal definition segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal, or a material suitable for providing a low resistance electrical connection between IC structure elements, i.e., a resistance level that is below a predetermined threshold that corresponds to one or more error levels based on the effect of resistance on circuit performance.

[0097] In various embodiments, the metal definition segment includes a portion of the substrate SUB and / or epitaxial layer that has a doping level, e.g., based on an implantation process, sufficient to cause the segment to have a low resistance level. In various embodiments, the doped metal definition segment includes one or more dopant materials having a doping concentration of about 1*1016per cubic centimeter (cm-3) or greater.

[0098] In some embodiments, the manufacturing process includes multiple metal definition layers, and a metal definition region / segment refers to any one or more of the multiple metal definition layers in the manufacturing process.

[0099] A metal definition cut region (e.g., metal definition cut region CMD) is a region in the IC layout that is incorporated into the manufacturing process as part of defining a break in a given metal definition structure, e.g., a portion that is etched away after the metal definition structure is formed, thereby causing adjacent and aligned metal definition segments to be electrically isolated from each other.

[0100] A metal region / segment (e.g., a frontside metal region / segment M0A or M0B or a backside metal region / segment BM0A or BM0B) is an area in an IC layout diagram that is incorporated into the manufacturing process as part of defining a structure containing a metal segment, which, in a given metal layer of the manufacturing process, includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials.

[0101] In some embodiments, each of the front metal regions / segments MOA and MOB corresponds to the bottommost or first front metal layer, also referred to in some embodiments as a metal zero layer or front metal zero layer. In some embodiments, each of the metal regions / segments BM0A and BM0B corresponds to the bottommost or first back metal layer, also referred to in some embodiments as a back metal zero layer. Front metal regions / segments MOA and MOB and / or back metal regions / segments BM0A and BM0B corresponding to other metal layers are within the scope of the present invention.

[0102] A via region / structure (e.g., via region / structure FTV, VB, VDR, VD, or VG) is an area in an IC layout that is incorporated into the manufacturing process as part of defining a via structure that includes one or more conductive materials configured to provide an electrical connection between a first conductive structure (e.g., a power rail or other metal segment) and a second conductive structure. In some embodiments, the first or second conductive structure is referred to as an upper conductive structure or a lower conductive structure. In some embodiments, the second structure corresponds to a metal-like defining structure in the case of via region / structure FTV or VDR, to a source / drain structure or other epitaxial region in the case of via region / structure VB or VD, and / or to a gate in the case of via region / structure VG.

[0103] like Figures 1A to 2C As shown, IC layouts / devices 100 and 200 include respective cells 100C and 200C having a cell height CH corresponding to 13 locations (e.g., rails) along the Y direction, at which up to seven instances of metal regions / segments MOA can be positioned alternately with up to six instances of metal regions / segments MOB. Other relationships between the cell height CH and the instances of metal regions / segments MOA and MOB are within the scope of the present invention.

[0104] like Figure 1A 、 Figure 1B 、 Figure 2B and Figure 2CAs shown, the top and bottom (relative to the Y direction) boundaries of the cells 100C and 200BC are aligned with the centers (relative to the Y direction) of the metal regions / segments M0A and BM0A in the X direction, and the centers of instances of the metal regions / segments M0A are aligned with the centers of the metal regions / segments BM0B in the X direction at the centers of the corresponding cells 100C or 200BC.

[0105] As shown, the top and bottom boundaries of the cell 200AC are aligned with the centers of the metal regions / segments M0A in the X direction, and instances of the metal regions / segments M0A are aligned with the top edges of the metal regions / segments BM0A and BM0B. Figure 2A

[0106] As shown, each active region / area AA1 of the IC layout / device 100 overlaps / overlies two via regions / structures VB, each via region / structure VB overlapping / overlying a corresponding metal region / segment BM0A, and each active region / area AA2 overlaps / overlies two via regions / structures VB, each via region / structure VB overlapping / overlying a metal region / segment BM0B. Figure 1A Figure 1B At each location where an active region / area AA1 overlaps / overlies a via region / structure VB, a metal-like defining region / segment MD overlaps / overlies the active region / area AA1 and extends away from the active region / area AA1 in a corresponding positive or negative Y direction. For each active region / area AA1, two corresponding metal-like defining regions / segments MD overlap / overlie the via regions / structures FTV, which overlap / overlie the metal regions / segments BM0A overlaid by the active region / area AA1.

[0107] Each such front-side metal-like defining region / segment MD is thereby electrically connected to the corresponding underlying back-side metal region / segment BM0A and the corresponding via region / structure VB by a parallel configuration of the corresponding via region / structure FTV and the corresponding portion of the active region / area AA1. In some embodiments, the parallel configuration is referred to as a dual-via configuration or a dual-via front-side / back-side connection.

[0108] In embodiments shown in

[0109] In embodiments shown in Figure 1A Figure 1B In some embodiments, one or more of the via regions / structures VB included in the dual-via configuration overlaps / overlies the metal region / segment BM0A at a location other than an edge.

[0110] In embodiments shown in Figure 1A 1B ​​​​In the embodiment depicted in FIG, the via region / structure FTV included in the dual via configuration overlaps / underlies the edge of the corresponding metal-like demarcation region / segment MD. In some embodiments, one or more via regions / structures FTV included in the dual via configuration overlap / underlies the corresponding metal-like demarcation region / segment MD at locations other than the edge.

[0111] exist Figure 1A and Figure 1B In the illustrated embodiment, IC layout / device 100 includes two metal regions / segments MOA, which overlap / overlie corresponding via regions / structures VDR, which overlap / overlie corresponding metal-like demarcation regions / segments MD, and are electrically connected to the overlapping / underlying metal region / segment BM0A via a dual via configuration. In some embodiments, IC layout / device 100 does not include one or both of the metal regions / segments MOA electrically connected to the metal region / segment BM0A via a dual via configuration.

[0112] exist Figure 1A and Figure 1B In the illustrated embodiment, IC layout / device 100 includes a metal region / segment MOA that overlaps / overlies a corresponding via region / structure VDR, which overlaps / overlies a corresponding region / segment in the metal-like definition region / segment MD, wherein the metal region / segment overlaps / overlies a corresponding portion of the active area / region AA2, which overlaps / overlies a corresponding via region / structure VB, which overlaps / overlies a metal region / structure BM0B, with the metal region / segment MOA being electrically connected to the overlapping / underlying metal region / segment BM0A via a single via configuration. In some embodiments, IC layout / device 100 does not include some or all of the electrical connections from the metal region / segment MOA to the metal region / segment BM0B.

[0113] like Figures 2A to 2C As shown, each active area / region AA2 of the IC layouts / devices 200A and 200B overlaps / overlies two via areas / structures VB, and each via area / structure VB overlaps / overlies a corresponding metal area / segment BM0A or BM0B.

[0114] At each location where active area / region AA2 overlaps / overlies via area / structure VB, metalloid defining region / segment MD overlaps / overlies active area / region AA2 and extends away from active area / region AA2 in the corresponding positive or negative Y direction. For each active area / region AA2, two corresponding metalloid defining region / segments MD overlap / overlie via area / structure FTV, which overlap / overlie metal area / segment BM0A or BM0B, which in turn overlaps / overlie active area / region AA2.

[0115] Each such front-side metal-like definition region / segment MD is thereby electrically connected to the corresponding underlying back-side metal region / segment BM0A or BM0B in parallel with the corresponding via region / structure VB through a parallel configuration of the corresponding via region / structure FTV and the corresponding portion of the active area / region AA2. In some embodiments, the parallel configuration is referred to as a dual via configuration or a dual via front-side / back-side connection.

[0116] exist Figure 2B and 2C In the embodiment of the IC layout / device 200B depicted in FIG, the via region / structure VB included in the dual via configuration overlaps / overlaps edges of the metal regions / segments BM0A and BM0B. In some embodiments, one or more via regions / structures VB included in the dual via configuration of the IC layout / device 200B overlap / overlaps metal regions / segments BM0A or BM0B at locations other than the edges.

[0117] exist Figure 2B and Figure 2C In the illustrated embodiment, IC layout / device 200B includes three metal regions / segments MOA overlapping / overlying corresponding via regions / structures VDR, which are electrically connected to corresponding metal-like demarcation regions / segments MD of the overlapping / underlying metal regions / segments BM0A and BM0B via a dual via configuration. In some embodiments, IC layout / device 100 does not include one or both of the metal regions / segments MOA electrically connected to the metal regions / segments BM0A and BM0B via a dual via configuration.

[0118] In some embodiments of IC layout / device 100 and / or 200, metal region / segment BM0A and corresponding instances of metal region / segment M0A (if present) are configured to have one of a supply or reference voltage, and metal region / segment BM0B and corresponding instances of metal region / segment M0A (if present) are configured to have another supply or reference voltage.

[0119] like Figure 1A and Figure 2AAs shown, in the Y direction, the active regions / areas AA1 have a width Dl, the active regions / areas AA2 have a width D2, the distance between adjacent instances of the active regions / areas AA1 and AA2 has a distance D3, the spacing from the top boundary of the cell 100C or 200AC to the active regions / areas AA1 or AA2 has a distance D3a, the spacing from the bottom boundary of the cell 100C or 200AC to the active regions / areas AA1 or AA2 has a distance D3b, the gate cut region CP has a width D4, the via region / structure FTV has a width D5, the via regions / structures VB corresponding to the active regions / areas AA1 and AA2 have respective widths D6a and D6b, and the metal regions / segments BM0A and BM0B have respective widths D7a and D7b.

[0120] As shown, the cell height CH of the cell 100C is given by the following: Figure 1A As shown, the cell height CH of the cell 200C is given by the following:

[0121] Figure 2A As shown, the cell height CH of the cell 200C is given by the following:

[0122] In some embodiments, the width D2 is substantially equal to twice the width Dl.

[0123] In some embodiments, the widths D7a and D7b are substantially equal, or the width D7a is greater than the width D7b.

[0124] In some embodiments, two values (e.g., widths and / or distances) are considered approximately related based on being corresponding to nominal values of an IC layout and / or based on being within one or more error ranges corresponding to a manufacturing process related to the IC device.

[0125] Because signal paths are routed through the metal regions / segments M0A and M0B to a given cell, the Y direction width and distance relationships of the metal regions / segments can affect signal path routing efficiency. In some embodiments, the wiring efficiency improves as the ratio of the Y direction width or distance to the pitch P0 decreases.

[0126] In some embodiments, the ratio of one or more cell heights CH to the pitch P0 ranges from 10 to 15, the ratio of the width Dl or D2 to the pitch P0 ranges from 1 to 5, the ratio of the distance D3, D3a, or D3b to the pitch P0 ranges from 2 to 5, the ratio of the width D4 to the pitch P0 ranges from 1 to 4, the ratio of the width D5 to the pitch P0 ranges from 1 to 2, the ratio of the width D6a or D6b to the pitch P0 ranges from 1 to 5, or the ratio of the width D7a or D7b to the pitch P0 ranges from 1 to 10.

[0127] ​In some embodiments of IC layout / device 100 or 200, one or more of cells 100C, 200AC or 200BC include an instance of active area / region AA1 or AA2, metal-like defined region / segment MD, metal-like defined cut region CMD, gate region / structure GS, gate cut region CP, via VD or VG, or metal region / segment M0A or M0B configured as one or more transistors TX (labeled as a single instance in each of Figure 1A and Figure 2A for clarity), located at a location where the gate region / structure GS overlaps / overlies the active area / region AA1 or AA2.

[0128] At such locations, one or more channels CL extend between adjacent epitaxial regions of the active area / region and through a gate of the gate region / structure GS.

[0129] In some embodiments, the leftmost and / or rightmost (with respect to the X direction) gate region / structure GS of cells 100C, 200AC or 200BC is a dummy gate region / structure, e.g., a gate region / structure that overlaps / overlies an edge of active area / region AA1 and / or AA2.

[0130] In embodiments as shown in Figures 1A to 2C Cells 100C and 200C of IC layout / device 100 and 200 include two or four gate regions / structures GS extending along the Y direction. Cells 100C and 200C of IC layout / device 100 and 200 including other numbers of gate regions / structures GS extending along the Y direction are within the scope of the present disclosure.

[0131] By including instances of via regions / structures VB and FTV configured as described above, each IC layout / device 100, 200A and 200B includes an electrical path from power rail BM0A and / or BM0B to a corresponding metal-like defined segment that includes a parallel arrangement of two via structures, whereby the dual via path resistance is reduced as compared to methods in which an electrical path from a power rail to a frontside structure does not include a parallel arrangement of via structures.

[0132] The reduced path resistance is used to reduce parasitic voltage drops, i.e., IR voltage drops, due to current flow as compared to such other methods. In some embodiments, the IR drop is reduced by approximately 5 millivolts (mV) as compared to other methods.

[0133] Figure 3 An IC layout / device 300 according to some embodiments is illustrated. IC layout / device 300 includes cells 300C, 300AC and 300BC, which are configured as described above with reference to Figures 1A to 2CTwo instances of each of the units 100C and 200BC are discussed, which are aligned in the Y direction and the grid track PG extends in the X direction. For the sake of clarity, individual features of the units 100C and 200BC are not labeled.

[0134] The number of units 100C and 200BC is provided as a non-limiting example for illustrative purposes. Other numbers of units 100C or 200BC, such as zero, one, or more than two, are also within the scope of the present invention.

[0135] Alternative examples of the grid rail PG correspond to the supply voltage VDD and the reference voltage VSS.

[0136] exist Figure 3 In the illustrated embodiment, the power rail corresponding to the supply voltage VDD is aligned with the shared boundary of cells 100C and 200BC, and the power rail corresponding to the reference voltage VSS is aligned with the centers of cells 100C and 200BC. In such embodiments, the active areas / regions AA1 and AA2 of cell 100C are p-type and n-type active areas / regions, respectively, and cell 100C is referred to as a PNP or PNNP cell 100C in some embodiments. In such embodiments, the top and bottom instances of the active area / region AA2 of cell 200BC are p-type and n-type active areas / regions, respectively, and cell 200BC is referred to as a PPNN cell 200BC in some embodiments.

[0137] In some embodiments, the power rail corresponding to reference voltage VSS is aligned with the shared boundary of cells 100C and 200BC, and the power rail corresponding to supply voltage VDD is aligned with the centers of cells 100C and 200BC. In such embodiments, active areas / regions AA1 and AA2 of cell 100C are n-type and p-type active areas / regions, respectively, and cell 100C is referred to as an NPN or NPPN cell 100C in some embodiments. In such embodiments, the top and bottom instances of active area / region AA2 of cell 200BC are n-type and p-type active areas / regions, respectively, and cell 200BC is referred to as an NNPP cell 200BC in some embodiments.

[0138] like Figure 3 As shown, the adjacent active area / region AA1 at the shared boundary of cell 100C and the adjacent active area / region AA2 at the shared boundary of cell 200BC are separated by a spacing AAS. In some embodiments, the spacing AAS corresponds to one or more minimum spacing rules associated with the positioning of the through-hole region / structure FTV between adjacent active areas / regions AA1 or AA2. In some embodiments, the minimum value of the spacing AAS is equal to the above-mentioned minimum spacing rule. Figure 1A and Figure 2AThe sum of the widths D5 of the via regions / structures FTV in question, plus twice the minimum spacing between the via regions / structures FTV and a given instance, active region AA1 or AA2. In some embodiments, the spacing AAS has a value equal to the sum of the distances D3a and D3b, as discussed above with respect to Figure 1A and 2A in question.

[0139] In some embodiments, the value of the spacing AAS is greater than the spacing between adjacent active regions / areas, which does not include the cells (not shown) of the via regions / structures FTV. In some embodiments, the cells 100C or 200C are modified versions of previously existing cells in which the values of the distances D3a and D3b and, by extension, the spacing AAS have been increased to accommodate the configuration of the via regions / structures FTV at the shared cell boundaries.

[0140] As the value of the spacing AAS increases, the flexibility to accommodate the widths D5 of the via regions / structures FTV increases, while the elasticity to accommodate the widths D1 and D2 of the active regions AA1 and AA2 and the distances D3 between the instance active regions / areas AA1 and AA2 decreases. In some embodiments, the spacing AAS has a value ranging from 80 nanometers to 150 nanometers. In some embodiments, the spacing AAS has a value ranging from 100 nanometers to 120 nanometers.

[0141] By including one or more of the cells 100C or 200BC configured as described above to include corresponding dual via paths, the IC layout / device 300 is able to realize the benefits discussed above with respect to the IC layouts / devices 100 and 200.

[0142] Figure 4 An IC layout / device 400 according to some embodiments is illustrated. The IC layout / device 400 includes four rows and four columns of tiles, each of the cells 100C and 200C aligned with the power grid tracks PG, each cell being discussed above with respect to Figures 1A to 3 The IC layout / device 400 includes four rows and four columns of tiles, each of the cells 100C and 200C aligned with the power grid tracks PG, each cell being discussed above with respect to

[0143] The number of rows and columns of the cells 100C and 200C is a non-limiting example provided for illustrative purposes. Other numbers of rows and / or columns of one or both of the cells 100C or 200C, for example, zero, one to three, or more than four, are also within the scope of the present application.

[0144] Each cell block 100C or 200C is separated from the cell 400C in the X direction by a padding cell 400PX and in the Y direction by a padding cell 400PY. For clarity, individual features of the cells 100C, 200C, 400PX, and 400PY are not shown.

[0145] The cell 400C is an IC layout that does not include a parallel arrangement of via structures between the frontside and backside metal regions / segments. In some embodiments, the cell 400C is an IC layout that includes a parallel arrangement of via structures between the frontside and backside metal regions / segments. Figure 4 In the illustrated embodiment, the cell 400C includes a single instance of n-type and p-type active regions / areas N and P and has a cell height equal to the power grid track PG pitch. In some embodiments, the cell 400C includes a single instance of n-type and p-type active regions / areas N and P and has a cell height equal to twice the power grid track PG pitch. Figure 4 One or more arrangements other than the illustrated arrangement, e.g., a cell height equal to twice the power grid track PG pitch.

[0146] Each of the padding cells 400PX and 400PY is one or more cells configured to physically separate and thereby electrically isolate the corresponding cell block 100C or 200C from the cell 400C along the corresponding positive or negative X or Y direction.

[0147] In various embodiments, a single instance of the cell 400PX corresponds to one or more rows of the cell 100C or 200C and / or a single instance of the cell 400PY corresponds to one or more columns of the cell 100C or 200C.

[0148] In some embodiments, the cell 400PX and / or 400PY includes features containing one or more insulating materials. In some embodiments, the cell 400PX and / or 400PY has dimensions and / or includes positioned features thereby maintaining pattern uniformity (e.g., gate pitch) between the cell block 100C or 200C and the adjacent cell 400C.

[0149] In some embodiments, the cell 400PX and / or 400PY includes features containing one or more dummy active regions (also referred to as dummy oxide diffusion or bounding regions in certain embodiments). A dummy active region is a region in an IC layout that is included in a fabrication process as part of a bounding region in which a modification of a standard operation corresponding to formation of an active region is performed. In some embodiments, the modification includes a subset of operations and / or one or more operations in addition to the standard operation, e.g., a deposition operation, whereby the region includes one or more insulating materials instead of an active region.

[0150] In some embodiments, the cell 400PX corresponds to the following with respect to the cell 100C or 200C. Figure 5A and 5BIn some embodiments, unit 400PY corresponds to the following non-limiting examples of Figure 6 Non-limiting examples discussed.

[0151] By incorporating one or more cells 100C or 200C configured as described above to include corresponding dual via paths, the IC layout / device 400 is able to achieve the benefits discussed above with respect to the IC layouts / devices 100 and 200 .

[0152] Figure 5A and 5B Shown above is Figure 4 The units 400PX and 400C are discussed as non-limiting examples. Figure 5A In the embodiment shown, unit 400PX is located between unit 400C and unit 100C, as described above with respect to Figure 1A and Figure 1B Discussed. Figure 5B In the embodiment shown, unit 400PX is located between unit 400C and unit 200C, as described above with reference to FIG. Figures 2A to 2C For the sake of clarity, individual features of units 100C, 200C, and 400C are not labeled.

[0153] like Figure 5A and Figure 5B As shown in each, cell 400PX has a width in the X direction equal to the gate pitch (not labeled) and includes instances of dummy active regions / areas DOD, metalloid defining regions / segments MD and metalloid defining cut regions CMD and gate cut regions CP.

[0154] The dummy active area / region DOD is aligned in the X direction with the active area / region (e.g., active area / region AA1 and / or AA2) of cell 100C or 200C and extends through cell 400PX. The dummy active area / region DOD is thus configured to electrically isolate the active areas / regions of cells 100C and 200C from the active area / region of cell 400C. In some embodiments, the dummy active area / region DOD, which is aligned in the X direction with the active area / region of cell 100C or 200C, is used to maintain loading uniformity of one or more pieces of fabrication equipment used to form active areas in IC device 400.

[0155] The metalloid defining region / segment MD extends in the Y direction and is centered in the cell 400PX along the X direction. The metalloid defining region / segment MD is thus configured to match the metalloid defining spacing pattern of the cell 100C or 200C with the metalloid defining spacing pattern of the cell 400C, thereby maintaining manufacturing load uniformity.

[0156] The metalloid definition cut region CMD and the gate cut region CP are configured to electrically isolate instances of the via region / structure FTV from features of the cell 400C.

[0157] An IC layout / device 400 including one or both of the non-limiting examples of cell 400C and cell 400PX between a corresponding one of cells 100C or 200C can thereby achieve the benefits described above.

[0158] Figure 6 Shown above is Figure 4 The non-limiting example of the unit 400PY discussed above is the unit 400PY located above with respect to Figure 1A and Figure 1B For clarity, individual features of units 100C and 400C are not labeled. In some embodiments (not shown), a non-limiting example of unit 400PY is located between unit 400C and unit 200C, as discussed above. Figures 2A to 2C discussed.

[0159] like Figure 6 As shown, the cell 400PY includes instances of dummy active regions / areas DOD, metalloid defining regions / segments MD, metalloid defining cut regions CMD, and gate structures GS, each of which is referred to above. Figures 1A to 3 discussed.

[0160] Figure 6 The number of examples of active regions / areas DOD, metal-like defining regions / segments MD, metal-like defining cut regions CMD, and gate structures GS shown in FIG. 1 is a non-limiting example provided for illustrative purposes. Figure 6 Instances of active regions / areas DOD, metalloid definition regions / segments MD, metalloid definition cut regions CMD, and gate structures GS other than those depicted are within the scope of the present invention.

[0161] Instances of the metal-like defined region / segment MD and gate region / structure GS extend in the Y direction and are configured to align with corresponding instances of the metal-like defined region / segment MD and gate region / structure GS in cells 400C and 100C or 200C, thereby maintaining manufacturing load uniformity.

[0162] The metalloid defined cut region CMD and the gate cut region CP are configured to electrically isolate instances of the metalloid defined region / segment MD and gate region / structure GS in cell 400PX from features in cells 400C and 100C or 200C (e.g., the through-hole region / structure FTV in cell 100C).

[0163] The instances of the dummy active region / area DOD are configured to electrically isolate the instances of the metal-like demarcation region / segment MD and the gate region / structure GS in cell 400PX from the features in cells 400C and 100C or 200C (e.g., the via region / structure FTV in cell 100C). In some embodiments, the instances of the dummy active region / area DOD are configured to match the active region / area spacing pattern of cells 400C and 100C or 200C, thereby maintaining manufacturing loading uniformity.

[0164] like Figure 6 As shown, a via region / structure FTV (e.g., in cell 100C) and an adjacent dummy active region / area DOD are separated by a spacing FAS. In some embodiments, because the dummy active region / area DOD is configured to electrically isolate the via region / structure FTV from other features, the spacing FAS is less than the minimum spacing rule for the spacing between an instance of the via region / structure FTV and an active region / area.

[0165] Thus, the non-limiting example IC layout / device 400 including cell 400PY between cell 400C and one of cells 100C or 200C can achieve the benefits discussed above.

[0166] Figure 7 is a flow chart of a method 700 for manufacturing an IC device according to some embodiments. The method 700 is operable to form the above referenced Figure 1A and Figure 1B The IC device 100 discussed above with reference to Figures 2A to 2C The IC device 200 discussed above with reference to Figure 3 The IC device 300 discussed above, and / or referenced above Figures 4 to 6 The IC device 400 is discussed.

[0167] In some embodiments, performing some or all of the operations of method 700 is performed to construct a portion of multiple IC devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing multiple manufacturing operations, such as one or more of developing, diffusion, deposition, etching, planarization, or other operations suitable for constructing multiple IC devices in a semiconductor wafer.

[0168] In some embodiments, the operations of method 700 are as follows: Figure 7 In some embodiments, the operations of method 700 are performed in the order shown in FIG. Figure 7 In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 700. In some embodiments, performing some or all of the operations of method 700 includes performing the following steps with respect to IC manufacturing system 1000 and Figure 10 one or more operations discussed.

[0169] In operation 702, in some embodiments, first and second epitaxial regions are formed on a front side of a semiconductor wafer. In some embodiments, forming the first and second epitaxial regions includes forming one of the active areas AA1 or AA2 of the IC device 100 or 200, as discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0170] In some embodiments, forming the first and second epitaxial regions includes forming two or more additional epitaxial regions, e.g., including one or both of the active areas AA1 or AA2 of the same IC device 100 or 200, and / or one or both of the active areas AA1 or AA2 of one or more additional IC devices 100 or 200, as discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0171] In some embodiments, forming the two or more additional epitaxial regions includes forming two or more additional epitaxial regions having the same or opposite doping as the first epitaxial region and the second epitaxial region, e.g., as discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0172] In some embodiments, forming the two or more additional epitaxial regions includes forming two or more additional epitaxial regions having the same or different widths as the first epitaxial region and the second epitaxial region, e.g., as discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0173] In some embodiments, forming the first and second epitaxial regions includes performing one or more deposition and / or implantation processes in regions of the semiconductor wafer corresponding to the first and second epitaxial regions, thereby achieving a predetermined doping concentration and type for one or more given dopants, e.g., as discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0174] In some embodiments, forming the first and second epitaxial regions includes forming source / drain structures including the first and second epitaxial regions, e.g., by performing one or more implantation processes and / or one or more deposition processes.

[0175] In operation 704, in some embodiments, a first gate and a first channel are constructed, the first channel extending between the first and second epitaxial regions and through the first gate. In some embodiments, constructing the first gate and the first channel includes constructing one or more instances of the gate structure GS and the channel CL discussed above with reference to Figures 1A to 6 one or more operations discussed.

[0176] In some embodiments, constructing the first gate and the first channel includes constructing one or more additional gates and / or channels based on forming two or more additional epitaxial regions in operation 702 .

[0177] In some embodiments, constructing the first gate and the first channel includes performing a plurality of fabrication operations, such as developing, diffusion, deposition, etching, planarization, or other suitable fabrication operations as described above with respect to Figures 1A to 6 One or more of the operations of the first gate and the first channel discussed.

[0178] In operation 706, in some embodiments, first and second metal type delimiting segments are formed directly overlying the first and second epitaxial regions, respectively. In some embodiments, forming the first metal type delimiting segment and the second metal type delimiting segment includes forming the above-described Figures 1A to 6 Examples of metalloid-defined fragment MDs are discussed.

[0179] In some embodiments, forming the first and second metal-like demarcation segments includes forming two or more additional metal-like demarcation segments in accordance with forming the two or more additional epitaxial regions in operation 702 .

[0180] In some embodiments, forming the metal-like defining segment comprises performing multiple fabrication operations including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form a continuous low resistance structure.

[0181] In some embodiments, forming the first and second metal delimiting segments is a process for forming one or more transistors (e.g., as described above with respect to Figures 1A to 6 Part of the transistor TX) discussed.

[0182] In some embodiments, forming the first and second types of metal-bounded segments is forming one or more via structures and / or one or more metal segments (e.g., as described above with respect to Figures 1A to 6 The discussed via structure VDR, VD or VG, or part of the metal segment MOA or MOB).

[0183] In some embodiments, forming the via structure or metal segment includes performing multiple fabrication operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form a continuous low-resistance structure.

[0184] In operation 708, in some embodiments, a first via structure is formed extending from the first epitaxial region to the back side of the semiconductor substrate. In some embodiments, forming the first via structure includes forming the via structure described above. Figures 1A to 6 Discuss the through-hole structure VB.

[0185] In some embodiments, forming the first via structure includes forming one or more additional via structures in accordance with forming two or more additional epitaxial regions in operation 702.

[0186] In operation 710, in some embodiments, a second via structure extending from the first metal-like defining segment to the semiconductor substrate backside is formed. In some embodiments, forming the second via structure includes forming a via structure as discussed above with reference to Figures 1A to 6 the via structure FTV.

[0187] In some embodiments, forming the second via structure includes forming one or more additional via structures in accordance with forming two or more additional epitaxial regions in operation 702.

[0188] In operation 712, in some embodiments, a first power rail overlying each of the first and second via structures is constructed at the semiconductor substrate backside. In some embodiments, forming the first power rail includes forming a metal segment as discussed above with reference to Figures 1A to 6 the metal segment BM0A or BM0B.

[0189] In some embodiments, constructing the first power rail includes constructing one or more additional power rails in accordance with forming two or more additional epitaxial regions in operation 702.

[0190] In some embodiments, forming the power rail includes performing a plurality of fabrication operations including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form a continuous low-resistance structure at the substrate backside.

[0191] By performing some or all of the operations of method 700, an IC device is fabricated in which each of one or more electrical paths from one or more power rails to one or more metal-like defining segments includes a parallel arrangement of two via structures, thereby achieving the benefits discussed above with respect to IC device 100 through IC device 400.

[0192] Figure 8 is a flowchart of a method 800 of generating an IC layout, in accordance with some embodiments, for example, the IC layout 100 discussed above with respect to Figure 1A and 1B the IC layout 200 discussed above with respect to Figures 2A to 2C the IC layout 300 discussed above with respect to Figure 3 the IC layout 400 discussed above with respect to Figures 4 to 6 .

[0193] In some embodiments, generating the IC layout includes generating an IC layout corresponding to an IC device fabricated based on the generated IC layout, such as the IC device 100 to the IC device 400 discussed above with respect to FIGS. 1 to Figure 6

[0194] In some embodiments, some or all of the method 800 is performed by a processor of a computer, such as the processor 902 of the IC layout generation system 900 discussed below with respect to FIG. 9. Figure 9

[0195] Some or all of the operations of the method 800 can be performed as part of a design process performed in a design company, such as the design company 1020 discussed below with respect to FIG. 10. Figure 10

[0196] In some embodiments, the operations of the method 800 are performed in the order illustrated. In some embodiments, the operations of the method 800 are performed simultaneously and / or in a different order than illustrated. In some embodiments, one or more operations of the method 800 are performed before, between, during, and / or after one or more other operations of the method 800. Figure 8 Figure 8 In operation 802, in some embodiments, a cell is retrieved from a storage device, the cell including a dual via configuration. The dual via configuration includes first and second via regions configured as an electrical path including a parallel via structure arrangement between a backside power rail and at least one frontside feature, such as a metal defining region configured to define a metal defining segment. In some embodiments, the at least one frontside feature includes a via and metal region overlapping the metal defining region and corresponding to an overlying via structure and metal segment, such as the via region / structure VDR and the metal region / segment M0A or M0B discussed above with respect to FIGS. 1 to

[0197] In some embodiments, retrieving the cell from the storage device includes retrieving one or more of the cells 100C and / or 200C discussed above with respect to FIGS. 1 to Figures 1A to 3

[0198] In some embodiments, retrieving the cell from the storage device includes retrieving a previously stored cell including the dual via configuration. Figures 1A to 6

[0199] In some embodiments, retrieving the cell from the storage device includes retrieving a previously stored cell including the dual via configuration.

[0200] In some embodiments, modifying the previously stored cell to obtain the dual via configuration includes adding one or more features, such as the one or more via regions discussed above with respect to FIGS. 1 to

[0201] Figures 1A to 6 ​​​​​​​The via region FTV and / or VB are discussed.

[0202] In some embodiments, modifying the one or more features includes moving the active region to accommodate the one or more via regions, e.g., as discussed above with reference to Figures 1A to 6 The active regions AA1 and / or AA2 are discussed.

[0203] In some embodiments, retrieving the cell from the storage device includes retrieving the IC layout of the cell from the cell library 907 of the IC layout generation system 900, as discussed below with reference to Figure 9 The IC layout 400 is discussed.

[0204] In some embodiments, retrieving the cell from the storage device includes storing the modified IC layout of the cell in the same or a different storage device, e.g., the cell library 907 of the IC layout generation system 900.

[0205] In operation 804, the dual-via cell is positioned in the IC layout. In some embodiments, positioning the cell in the IC layout includes positioning one or more of the cells 100C or 200C in the IC layout 100 to the IC layout 400, as discussed above with reference to Figures 1A to 6 The IC layout 400 is discussed.

[0206] In some embodiments, positioning the cell in the IC layout includes aligning the cell according to a power grid (e.g., the power grid tracks PG discussed above with reference to Figure 3 and Figure 4 The power grid tracks PG.

[0207] In some embodiments, positioning the cell in the IC layout includes arranging one or more cell blocks including the cell in the IC layout, e.g., the cell blocks 100C or 200C in the IC layout 400 discussed above with reference to Figures 4 to 6 The IC layout 400 is discussed.

[0208] In some embodiments, arranging the one or more cell blocks includes positioning one or more spacer cells between the one or more blocks and other cells, e.g., the spacer cells 400PX and / or 400PY between the one or more blocks and the cells 400C discussed above with reference to Figures 4 to 6 The IC layout 400 is discussed.

[0209] In operation 806, in some embodiments, the IC layout includes the dual-via configured cell stored in a storage device. In some embodiments, storing the IC layout in the storage device includes storing the IC layout 100 to the IC layout 400 (as discussed above with reference to Figures 1A to 6 The IC layout 400 is discussed.

[0210] In various embodiments, storing the IC layout in a storage device includes storing the IC layout in a non-volatile computer-readable memory or a library of cells (e.g., a database and / or including storing the IC layout over a network). In some embodiments, storing the IC layout in a storage device includes storing the IC layout in a layout 909 of the IC layout generation system 900 or over a network 914, as described below with reference to Figure 9 as discussed above.

[0211] In operation 808, in some embodiments, one or more manufacturing operations are performed based on the IC layout. In some embodiments, performing one or more manufacturing operations includes performing one or more developing exposures based on the IC layout. As described above, in some embodiments, performing one or more manufacturing operations includes performing one or more etching operations based on the IC layout. Figure 7 later Figure 10 As discussed above, one or more manufacturing operations are performed based on the IC layout, such as one or more developing exposures.

[0212] By performing some or all of the operations of the method 800, an IC layout is generated that corresponds to an IC device in which each of the one or more electrical paths from the one or more power rails to the one or more metal-like defined segments includes a parallel arrangement of two via structures, thereby achieving the benefits discussed above with respect to the IC device 100 through the IC device 400.

[0213] Figure 9 is a block diagram of an IC layout generation system 900 according to some embodiments. For example, the IC layout generation system 900 can be used to implement the methods described herein for designing an IC layout according to one or more embodiments, according to some embodiments.

[0214] In some embodiments, the IC layout generation system 900 is a general purpose computing device that includes a hardware processor 902 and a non-transitory computer- readable storage medium 904. Among other things, the storage medium 904 is encoded with (i.e., stores) computer program code 906, i.e., a set of executable instructions. The hardware processor 902, upon execution of the instructions 906, represents, at least in part, an electronic design automation tool that implements part or all of a method, such as the method 500 of generating an IC layout described above with respect to FIG. 5 and / or the method 700 of generating an IC layout described above with respect to FIG. 7. Figure 7 the methods described above for generating an IC layout.

[0215] The processor 902 is electrically coupled via the bus 908 to the computer- readable storage medium 904. The processor 902 is also electrically coupled via the bus 908 to the I / O interface 910. The network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to the network 914, enabling the processor 902 and the computer-readable storage medium 904 to connect to external elements via the network 914. The processor 902 is configured to execute the computer program code 906 encoded in the computer-readable storage medium 904, so as to enable the IC layout generation system 900 to perform part or all of the mentioned programs and / or methods. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0216] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). By way of example, the computer-readable storage medium 904 includes a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 904 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W) and / or a digital video disc (DVD).

[0217] In one or more embodiments, the computer-readable storage medium 904 stores computer program code 906 configured to enable the IC layout generation system 900 (where such execution represents at least in part an electronic design automation tool) to perform part or all of the mentioned programs and / or methods. In one or more embodiments, the computer-readable storage medium 904 also stores information that is advantageous for performing part or all of the mentioned programs and / or methods.

[0218] In one or more embodiments, the computer-readable storage medium 904 stores a cell library 907 of cells, including cells described herein, such as the cells 100C, 200C, 400PX, and 400PY discussed above with respect to FIGS. 1-4. Figure 6 In one or more embodiments, the computer-readable storage medium 904 stores a cell library 907 of cells, including cells described herein, such as the cells 100C, 200C, 400PX, and 400PY discussed above with respect to FIGS. 1-4.

[0219] In one or more embodiments, the computer-readable storage medium 904 stores a layout map 909, which includes the IC layout maps described herein, such as the IC layout maps 100-400 of some embodiments discussed above with respect to FIGS. 1-4. Figure 6

[0220] The IC layout generation system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuits. In one or more embodiments, the I / O interface 910 includes a keyboard, a number keypad, a mouse, a trackball, a joy pad, a touch screen, and / or a cursor arrow key for transmitting information and instructions to the processor 902.

[0221] The IC layout generation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface such as BLUETOOTH, WIFI, Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), Wideband Code Division Multiple Access (WCDMA), etc.; or a wired network interface such as ETHERNET, Universal Serial Bus (USB), or IEEE-1364. In one or more embodiments, part or all of the programs and / or methods mentioned are implemented in two or more IC layout generation systems 900.

[0222] The IC layout generation system 900 is configured to receive information through the I / O interface 910, including instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 902, which is transmitted to the processor 902 via the bus 908; the IC layout generation system 900 is configured to receive information related to a user interface (UI) through the I / O interface 910, which is stored in the computer-readable medium 904 as a user interface 942.

[0223] ​In some embodiments, a portion or all of the mentioned programs and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the mentioned programs and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, a portion or all of the mentioned programs and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned programs and / or methods is implemented as a software application that is part of an electronic design automation tool. In some embodiments, a portion or all of the mentioned programs and / or methods are implemented as a software application used by IC layout generation system 900. In some embodiments, a layout including standard cells is generated using a tool such as or other appropriate layout generation tool.

[0224] In some embodiments, the programs are implemented as functions of programs stored in a non-transitory computer readable recording medium. Examples of the non-transitory computer readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage or memory units such as one or more optical discs (e.g., DVD), magnetic discs (e.g., hard disc), semiconductor memories (e.g., ROM, RAM, memory card, etc.).

[0225] Figure 10 is a block diagram of an IC manufacturing system 1000 and an IC manufacturing flow related thereto according to some embodiments. In some embodiments, at least one of (A) one or more semiconductor photomasks, or (B) at least one component in a semiconductor integrated circuit layer is manufactured using manufacturing system 1000 based on an IC layout.

[0226] In Figure 10In the embodiment of the present invention, IC manufacturing system 1000 includes entities that interact with each other during the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 1060, such as design company 1020, photomask company 1030, and IC manufacturer / foundry 1050. The entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 1020, photomask company 1030, and IC foundry 1050 are owned by a single large company. In some embodiments, two or more of design company 1020, photomask company 1030, and IC foundry 1050 coexist in a common facility and utilize common resources.

[0227] The design company (or design team) 1020 generates an IC design layout 1022. The IC design layout 1022 includes various geometric patterns, such as cells 100C, 200C, 400PX and / or 400PY and / or as described above with reference to FIG. Figure 6 The IC layout drawings 100 to 400 discussed. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers that constitute the various components of the IC device 1060 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout drawing 1022 includes various IC features (e.g., active areas, gates, sources and drains, through-holes for metal wires or interlayer interconnects, and openings for bonding pads) formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design company 1020 implements an appropriate design process to form the IC design layout drawing 1022. The design process includes one or more of logical design, physical design, or layout and routing. The IC design layout drawing 1022 is presented in one or more data files having geometric pattern information. For example, the IC design layout drawing 1022 can be expressed in a GDSII file format or a DFII file format.

[0228] Photomask company 1030 includes data preparation 1032 and photomask fabrication 1044. Photomask company 1030 uses IC design layout 1022 to fabricate one or more photomasks 1045 for fabricating layers of IC device 1060 according to IC design layout 1022. Photomask company 1030 performs photomask data preparation 1032 in which IC design layout 1022 is converted into a representative data file (RDF). Photomask data preparation 1032 provides the RDF to photomask fabrication 1044. Photomask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. Design layout 1022 is manipulated via photomask data preparation 1032 to conform to specific characteristics of the mask writer and / or requirements of IC foundry 1050. In Figure 10 In some embodiments, photomask data preparation 1032 and photomask fabrication 1044 can be collectively referred to as photomask data preparation.

[0229] In some embodiments, photomask data preparation 1032 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for imaging errors, such as those that can be caused by diffraction, interference, other process effects, etc. Optical proximity correction adjusts IC design layout 1022. In some embodiments, photomask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats optical proximity correction as an inverse imaging problem.

[0230] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks the IC design layout 1022, which has been processed in optical proximity correction, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the mask rule checker modifies the IC design layout 1022 to compensate for the constraints during mask fabrication 1044, which can undo the modifications performed by optical proximity correction in order to satisfy the mask creation rules.

[0231] In some embodiments, the photomask data preparation 1032 includes a lithography process check (LPC), which simulates the process to be performed by the IC foundry 1050 to manufacture the IC device 1060. The lithography process check simulates the process based on the IC design layout 1022 to create a simulated manufactured device, such as the IC device 1060. The process parameters in the lithography process check simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The lithography process check considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after creating the simulated manufactured device through the lithography process check, if the simulated device is not close enough in shape to meet the design rules, the optical proximity correction and / or the photomask specification checker are repeated to further refine the IC design layout 1022.

[0232] It should be understood that the above description of photomask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs), to modify IC design layout 1022 according to manufacturing specifications. Additionally, the processes applied to IC design layout 1022 during data preparation 1032 can be performed in a variety of different orders.

[0233] After the photomask data preparation 1032 and during the photomask fabrication 1044, a photomask 1045 or a set of photomasks 1045 is fabricated based on the modified IC design layout 1022. In some embodiments, the photomask fabrication 1044 includes performing one or more e-beam exposures based on the modified IC design layout 1022. In some embodiments, an e-beam or multiple e-beam machines are used to form a pattern on a mask (photomask or reticle) 1045 based on the modified IC design layout 1022. The photomask 1045 can be formed in various technologies. In some embodiments, the photomask 1045 is formed using binary technology. In some embodiments, the photomask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., ultraviolet or extreme ultraviolet light) used to expose a photo-sensitive material layer (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and penetrates the transparent regions. In one example, a binary mask version of the photomask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the photomask 1045 is formed using phase shift technology. In a phase shift mask version of the photomask 1045, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The photomask resulting from the photomask fabrication 1044 is used in a variety of processes. For example, such a photomask is used in an ion implantation process to form various doped regions in a semiconductor wafer 1053, in an etching process to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0234] The IC foundry 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC foundry 1050 is a semiconductor foundry. For example, there can be one manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line, BEOL) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry.

[0235] The IC foundry 1050 includes wafer fabrication tools 1052 configured to perform various fabrication operations on semiconductor wafers 1053 such that IC devices 1060 are fabricated according to photomasks (e.g., photomask 1045). In various embodiments, the fabrication tools 1052 include a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition chamber or a low-pressure chemical vapor deposition furnace), a chemical mechanical polishing system, a plasma etching system, a wafer cleaning system, or one or more other manufacturing devices capable of performing one or more suitable fabrication processes as discussed herein.

[0236] The IC foundry 1050 uses the photomask 1045 fabricated by the photomask company 1030 to fabricate the IC devices 1060. Thus, the IC foundry 1050 uses the IC design layout 1022, at least indirectly, to fabricate the IC devices 1060. In some embodiments, the IC foundry 1050 uses the photomask 1045 to fabricate a semiconductor wafer 1053 to form the IC devices 1060. In some embodiments, IC fabrication includes performing one or more exposures to light based at least indirectly on the IC design layout 1022. The semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which material layers are formed. The semiconductor wafer 1053 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0237] In some embodiments, an integrated circuit device includes a first transistor on a front side of a semiconductor substrate, the first transistor including a first gate, a first epitaxial region and a second epitaxial region, a first channel extending between the first epitaxial region and the second epitaxial region and passing through the first gate, and a first type of metal definition segment and a second type of metal definition segment directly overlying the first epitaxial region and the second epitaxial region, respectively, a first power rail on a back side of the semiconductor substrate, a first via structure extending from the first epitaxial region to the first power rail, and a second via structure extending from the first type of metal definition segment to the first power rail. In some embodiments, the first via structure is aligned with an edge of the first power rail. In some embodiments, the second via structure is aligned with an edge of the first type of metal definition segment. In some embodiments, the integrated circuit device includes a second transistor on the front side of the semiconductor substrate, the second transistor including a second gate, the second epitaxial region and a third epitaxial region, a second channel extending between the second epitaxial region and the third epitaxial region and passing through the second gate, and the second type of metal definition segment and a third type of metal definition segment directly overlying the third epitaxial region, and a third via structure extending from the third epitaxial region to the first power rail, the second via structure extending from the third type of metal definition segment to the first power rail. In some embodiments, the integrated circuit device includes a second transistor on the front side of the semiconductor substrate, the second transistor including a second gate aligned with the first gate in a first direction, a third epitaxial region and a fourth epitaxial region, a second channel extending between the third epitaxial region and the fourth epitaxial region and passing through the second gate, and a third type of metal definition segment and a fourth type of metal definition segment directly overlying the third epitaxial region and the fourth epitaxial region, respectively, and aligned with the first type of metal definition segment and the second type of metal definition segment, respectively, in the first direction, a second power rail on the back side of the semiconductor substrate, a third via structure extending from the third epitaxial region to the second power rail, and a fourth via structure extending from the third type of metal definition segment to the second power rail. In some embodiments, the first transistor and the second transistor are different types of N-type transistors or P-type transistors. In some embodiments, the first epitaxial region, the second epitaxial region, the third epitaxial region, and the fourth epitaxial region have the same width in the first direction. In some embodiments, each of the first transistor and the second transistor is a first type of N-type transistor or P-type transistor, and the integrated circuit device further includes a third transistor between the first transistor and the second transistor, wherein the third transistor is a second type of the N-type transistor or the P-type transistor.In some embodiments, the third transistor includes a fifth epitaxial region and a sixth epitaxial region having a width in the first direction that is substantially twice a width in the first direction of the first epitaxial region, the second epitaxial region, the third epitaxial region, and the fourth epitaxial region.

[0238] In some embodiments, an integrated circuit device includes a first plurality of gate structures extending along a first direction on a front side of a semiconductor wafer, a plurality of first epitaxial regions between corresponding ones of the first plurality of gate structures and aligned with one another in a second direction perpendicular to the first direction, a plurality of first metal-like definition segments extending along the first direction and directly overlying corresponding ones of the plurality of first epitaxial regions, a first power rail extending along the second direction on a back side of the semiconductor wafer, a plurality of first via structures extending from the first power rail to corresponding ones of the plurality of first epitaxial regions, and a plurality of second via structures extending from the first power rail to corresponding ones of the plurality of first metal-like definition segments. In some embodiments, the integrated circuit device includes a plurality of second epitaxial regions in corresponding ones of the first plurality of gate structures and aligned with one another in the second direction, a plurality of second metal-like definition segments extending along the first direction and directly overlying corresponding ones of the plurality of second epitaxial regions, a second power rail extending along the second direction on the back side of the semiconductor wafer, a plurality of third via structures extending from the second power rail to corresponding ones of the plurality of second epitaxial regions, and a plurality of fourth via structures extending from the second power rail to corresponding ones of the plurality of second metal-like definition segments. In some embodiments, the integrated circuit device includes a plurality of third epitaxial regions between corresponding ones of the first plurality of gate structures, between the plurality of first epitaxial regions and the plurality of second epitaxial regions in the first direction, and aligned with one another in the second direction, wherein the first epitaxial regions and the second epitaxial regions of the plurality of first epitaxial regions and the plurality of second epitaxial regions have a first doping type and a first width in the first direction, and the third epitaxial regions of the plurality of third epitaxial regions have a second doping type different from the first doping type and a second width in the first direction greater than the first width. In some embodiments, the integrated circuit device includes a second plurality of gate structures extending along the first direction on the front side of the semiconductor wafer, and a plurality of fourth epitaxial regions and a plurality of fifth epitaxial regions in corresponding ones of the second plurality of gate structures and aligned with one another in the second direction, wherein the fourth epitaxial regions and the fifth epitaxial regions of the plurality of fourth epitaxial regions and the plurality of fifth epitaxial regions have the first width in the first direction, and the plurality of fourth epitaxial regions and the plurality of fifth epitaxial regions are offset from the plurality of first epitaxial regions, the plurality of second epitaxial regions, and the plurality of third epitaxial regions in one of the first direction or the second direction.In some embodiments, the first epitaxial regions of the first plurality of epitaxial regions have a first doping type, and the second epitaxial regions of the second plurality of epitaxial regions have a second doping type different from the first doping type. In some embodiments, the integrated circuit device includes a second plurality of gate structures extending along the first direction on the front side of the semiconductor wafer, and a plurality of third epitaxial regions and a plurality of fourth epitaxial regions between corresponding gate structures of the second plurality of gate structures and aligned with each other in the second direction, wherein the first epitaxial regions of the first plurality of epitaxial regions and the second epitaxial regions of the second plurality of epitaxial regions have a first width in the first direction, the third epitaxial regions of the plurality of third epitaxial regions and the fourth epitaxial regions of the plurality of fourth epitaxial regions have a second width in the first direction that is less than the first width, and the plurality of third epitaxial regions and the plurality of fourth epitaxial regions are offset from the first plurality of epitaxial regions and the second plurality of epitaxial regions in one of the first direction or the second direction.

[0239] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit device, characterized in that: include: A first transistor is located on the front side of the semiconductor substrate, the first transistor comprising: a first gate; a first epitaxial region and a second epitaxial region; a first channel extending between the first epitaxial region and the second epitaxial region and passing through the first gate; and A first type metal-defined segment and a second type metal-defined segment directly overlying the first epitaxial region and the second epitaxial region, respectively; a first power rail located on the back side of the semiconductor substrate; a first via structure extending from the first epitaxial region to the first power rail; and A second via structure extends from the first metal-bounding segment to the first power rail.

2. The integrated circuit device according to claim 1, wherein: The first through-hole structure is aligned with an edge of the first power rail.

3. The integrated circuit device according to claim 1, wherein: The second through-hole structure is aligned with the edge of the first metal-boundary segment.

4. The integrated circuit device according to claim 1, wherein: Also includes: a second transistor located on the front side of the semiconductor substrate, the second transistor comprising: a second gate; the second epitaxial region and the third epitaxial region; a second channel extending between the second epitaxial region and the third epitaxial region and passing through the second gate; and The second type metal-defined segment and the third type metal-defined segment directly overlie the third epitaxial region; and a third via structure extending from the third epitaxial region to the first power rail, The second via structure extends from the third type metal-bound segment to the first power rail.

5. The integrated circuit device according to claim 1, wherein: Also includes: a second transistor located on the front side of the semiconductor substrate, the second transistor comprising: a second gate aligned with the first gate in a first direction; a third epitaxial region and a fourth epitaxial region; a second channel extending between the third epitaxial region and the fourth epitaxial region and passing through the second gate; and A third type of metal delimiting segment and a fourth type of metal delimiting segment, which directly overlie the third epitaxial region and the fourth epitaxial region, respectively, and are aligned with the first type of metal delimiting segment and the second type of metal delimiting segment, respectively, in the first direction; a second power rail located on the back side of the semiconductor substrate; a third via structure extending from the third epitaxial region to the second power rail; and A fourth via structure extends from the third type metal-defining segment to the second power rail.

6. An integrated circuit device, characterized in that: include: a first plurality of gate structures extending along a first direction on the front side of the semiconductor wafer; a plurality of first epitaxial regions located between corresponding gate structures of the first plurality of gate structures and aligned with each other in a second direction perpendicular to the first direction; A plurality of first type metal-defining segments extend along the first direction and directly overlie corresponding first epitaxial regions of the plurality of first epitaxial regions. a first power rail extending along the second direction on the back side of the semiconductor wafer; a plurality of first via structures extending from the first power rail to corresponding first epitaxial regions of the plurality of first epitaxial regions; as well as A plurality of second via structures extend from the first power rail to corresponding first type metal-delimited segments of the plurality of first type metal-delimited segments.

7. The integrated circuit device according to claim 6, wherein: Also includes: a plurality of second epitaxial regions located at corresponding gate structures among the first plurality of gate structures and aligned with each other in the second direction; a plurality of second type metal-defined segments extending along the first direction and directly overlying corresponding second epitaxial regions of the plurality of second epitaxial regions, a second power rail extending along the second direction on the back side of the semiconductor wafer; a plurality of third via structures extending from the second power rail to corresponding second epitaxial regions of the plurality of second epitaxial regions; as well as A plurality of fourth via structures extend from the second power rail to corresponding second type metal-delimited segments of the plurality of second type metal-delimited segments.

8. The integrated circuit device according to claim 7, wherein: Also includes: a plurality of third epitaxial regions located between corresponding gate structures in the first plurality of gate structures, located between the plurality of first epitaxial regions and the plurality of second epitaxial regions in the first direction, and aligned with each other in the second direction, wherein The first epitaxial region and the second epitaxial region of the plurality of first epitaxial regions and the plurality of second epitaxial regions have a first doping type and a first width in the first direction, and The third epitaxial region of the plurality of third epitaxial regions has a second doping type different from the first doping type and a second width in the first direction that is greater than the first width.

9. The integrated circuit device according to claim 8, wherein: Also includes: a second plurality of gate structures extending along the first direction on the front side of the semiconductor wafer; and a plurality of fourth epitaxial regions and a plurality of fifth epitaxial regions, which are located in corresponding gate structures in the second plurality of gate structures and are aligned with each other in the second direction, wherein The fourth epitaxial regions and the fifth epitaxial regions of the plurality of fourth epitaxial regions and the plurality of fifth epitaxial regions have the first width in the first direction, and The plurality of fourth epitaxial regions and the plurality of fifth epitaxial regions are offset from the plurality of first epitaxial regions, the plurality of second epitaxial regions, and the plurality of third epitaxial regions in one of the first direction or the second direction.

10. The integrated circuit device according to claim 7, wherein: in The first epitaxial region of the plurality of first epitaxial regions has a first doping type, and The second epitaxial region of the plurality of second epitaxial regions has a second doping type different from the first doping type.

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