Device structure including a composite package

Abstract

A device structure including a composite package includes a first semiconductor die including a semiconductor substrate, a dielectric material layer, an edge ring sealing structure, at least one passivation dielectric layer, and a cap metal ring; the dielectric material layer covers the semiconductor substrate; the edge ring sealing structure laterally surrounds the dielectric material layer without any lateral opening therethrough; the at least one passivation dielectric layer covers the dielectric material layer; a cap metal ring contacts a top surface portion of the edge ring seal structure and laterally surrounds a lower portion of the at least one passivation dielectric layer. Each corner region of the at least one passivation dielectric layer has no metal material except for a corresponding single inclined rod portion of the cap metal ring. Alternatively or additionally, a spacer metal ring having a different height than the cap metal ring may be formed within the at least one passivation dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to a semiconductor device structure, particularly to a device structure including a composite package. BACKGROUND

[0002] Generally, if a semiconductor die is formed within a mold compound die frame of a composite package (e.g., a system in package), an edge seal structure can be used for the semiconductor die. However, a mismatch between various coefficients of thermal expansion of the edge seal structure and the mold compound die frame can create a large mechanical stress during use of the composite package. This mechanical stress can induce stress cracks and functional failures in the composite package. SUMMARY

[0003] The present utility model aims to provide a device structure including a composite package to solve at least one of the above problems.

[0004] Some embodiments of the present utility model provide a device structure including a composite package, the composite package comprising a first semiconductor die, the first semiconductor die comprising: a semiconductor substrate; a dielectric material layer covering the semiconductor substrate; an edge ring seal structure laterally surrounding the dielectric material layer; at least one passivation dielectric layer covering the dielectric material layer; and a cap metal ring contacting a top surface portion of the edge ring seal structure and laterally surrounding a lower portion of the at least one passivation dielectric layer, wherein: the edge ring seal structure comprises two longitudinal portions parallel to a first sidewall of the first semiconductor die; two lateral portions parallel to a second sidewall of the first semiconductor die; and four inclined corner portions connecting a corresponding one of the two longitudinal portions and a corresponding one of the two lateral portions; and each corner region of the at least one passivation dielectric layer between a vertical plane and a vertical line does not have any metal material other than a corresponding single inclined rod portion of the cap metal ring, the vertical plane comprising an inner sidewall of the four inclined corner portions of the edge ring seal structure, and the vertical line comprising a nearest corner edge of the first semiconductor die.

[0005] According to one of the embodiments of the present utility model, further comprising a first mold compound die frame laterally surrounding the first semiconductor die.

[0006] According to one of the embodiments of the present utility model, further comprising: a second semiconductor die located above or below the first semiconductor die and bonded to the first semiconductor die; and a second mold compound die frame laterally surrounding the first semiconductor die and contacting a horizontal surface of the first mold compound die frame, wherein sidewalls of the second mold compound die frame are vertically coincident with sidewalls of the first mold compound die frame.

[0007] According to one of the embodiments of the present application, the cover metal ring includes two first bar portions parallel to a plurality of the first sidewalls of the first semiconductor die; two second bar portions parallel to a plurality of the second sidewalls of the first semiconductor die; and four inclined bar portions connecting a corresponding one of the two first bar portions and a corresponding one of the two second bar portions and located at a corresponding corner region of the at least one passivation dielectric layer.

[0008] According to one of the embodiments of the present application, a width of each of the four inclined bar portions is in a range of 3.2 micrometers to 7.2 micrometers.

[0009] According to one of the embodiments of the present application, each region of the four inclined bar portions adjacent to a corresponding one of the two first bar portions and the two second bar portions is laterally spaced apart from sidewalls selected from both of the plurality of the first sidewalls and the plurality of the second sidewalls of the first semiconductor die by an offset distance in a range of 27 micrometers to 90 micrometers.

[0010] According to one of the embodiments of the present application, a ratio of a length of one of the two first bar portions to a length of one of the plurality of the first sidewalls of the first semiconductor die is in a range of 0.8500 to 0.9948; and a ratio of a length of one of the two second bar portions to a length of one of the plurality of the second sidewalls of the first semiconductor die is in a range of 0.8500 to 0.9948.

[0011] According to one of the embodiments of the present application, the plurality of dielectric material layers cover the semiconductor substrate and have a plurality of metal interconnect structures formed therein; and the edge cover sealing structure extends vertically from the semiconductor substrate to a bottom surface of the at least one passivation dielectric layer.

[0012] According to one of the embodiments of the present application, the at least one passivation dielectric layer includes: a first passivation dielectric layer contacting a topmost surface of the plurality of dielectric material layers; at least one second passivation dielectric layer contacting a topmost surface of the cover metal ring; and a third passivation dielectric layer covering and vertically spaced apart from the cover metal ring.

[0013] The utility model discloses another some embodiments provide a kind of device structure comprising composite package, composite package includes first semiconductor die, and first semiconductor die includes: semiconductor substrate;Dielectric material layer, covers semiconductor substrate;Edge ring sealing structure, laterally surrounds dielectric material layer, without any lateral opening through it;At least one passivation dielectric layer, covers dielectric material layer;Cover metal ring, contact top surface portion of edge ring sealing structure, and laterally surround lower part of at least one passivation dielectric layer;Spacing metal ring, form in at least one passivation dielectric layer, and be located in cover metal ring, and have topmost surface, be located above the horizontal plane comprising the topmost surface of cover metal ring. BRIEF DESCRIPTION OF DRAWINGS

[0014] Various aspects of the disclosure will now be described with reference to the drawing figures. It should be noted that the various features are not necessarily drawn to scale and that, to the extent possible, the same reference numerals will be used throughout the drawing figures and text to refer to same or like parts. In fact, the dimensions of the elements can be arbitrarily enlarged or reduced for the sake of clarity in illustrating the features of the present disclosure.

[0015] According to embodiments of the present disclosure, FIG. 1A is a vertical cross-sectional view of a semiconductor die.

[0016] According to embodiments of the present disclosure, FIG. 1B is FIG. 1A is a partial perspective top view of an embodiment semiconductor die, wherein the embodiment semiconductor die is in a first configuration. Vertical plane A-A’ is FIG. 1A is a cross-section of the vertical cross-sectional view of

[0017] FIG. 1C is an enlarged view of region C of FIG. 1B

[0018] FIG. 1D is a first region of an embodiment semiconductor die of FIGS. 1A-1C along vertical plane D-D’ of FIG. 1C is a vertical cross-sectional view.

[0019] FIG. 1E is a second region of an embodiment semiconductor die of FIGS. 1A-1C along vertical plane E-E’ of FIG. 1C is a vertical cross-sectional view.

[0020] According to embodiments of the present disclosure, FIG. 2A is a partial perspective top view of an embodiment semiconductor die of FIG. 1, wherein the embodiment semiconductor die is in a second configuration.

[0021] FIG. 2B is an enlarged view of region B of FIG. 2A

[0022] According to embodiments of the present disclosure, FIG. 3A ​​is a partial perspective top view of the embodiment semiconductor die of FIG. 1, with the embodiment semiconductor die in a third configuration.

[0023] FIG. 3B is a zoomed-in view of region B of FIG. 3A

[0024] FIG. 4A is a vertical cross-sectional view of a first region of the embodiment semiconductor die, with the embodiment semiconductor die in a fourth configuration. FIG. 4A the vertical cross-section corresponds to vertical cross-section D-D’ of FIG. 1C

[0025] FIG. 4B is a vertical cross-sectional view of a second region of the embodiment semiconductor die, with the embodiment semiconductor die in a fourth configuration. FIG. 4B the vertical cross-section corresponds to vertical cross-section E-E’ of FIG. 1C

[0026] FIG. 4C is a vertical cross-sectional view of a region of the embodiment semiconductor die, with the embodiment semiconductor die in a fifth configuration. FIG. 4C the vertical cross-section corresponds to vertical cross-section E-E’ of FIG. 1C

[0027] FIG. 5A is a vertical cross-sectional view of a first region of the embodiment semiconductor die, with the embodiment semiconductor die in a sixth configuration. FIG. 5A the vertical cross-section corresponds to vertical cross-section D-D’ of FIG. 1C

[0028] FIG. 5B is a vertical cross-sectional view of a second region of the embodiment semiconductor die, with the embodiment semiconductor die in a sixth configuration. FIG. 5B the vertical cross-section corresponds to vertical cross-section E-E’ of FIG. 1C

[0029] FIG. 5A is a vertical cross-sectional view of a region of the embodiment semiconductor die, with the embodiment semiconductor die in a seventh configuration. FIG. 5B the vertical cross-section corresponds to vertical cross-section E-E’ of FIG. 4A

[0030] According to embodiments of the present disclosure, FIG. 4B is a vertical cross-sectional view of an embodiment structure including a carrier wafer and a plurality of first semiconductor dies attached to the carrier wafer.

[0031] FIG. 5C is a top view of the embodiment structure of FIG. 5C FIG. 1C ​​​​​​​​a cross-section of a vertical cross-sectional view of the embodiment structure after forming a first mold compound matrix.

[0032] According to embodiments of the disclosure, FIG. 5C is a vertical cross-sectional view of the embodiment structure after forming a second mold compound matrix.

[0033] According to embodiments of the disclosure, FIG. 4C is a vertical cross-sectional view of the structure after attaching a set of second semiconductor die and third semiconductor die to each first semiconductor die.

[0034] According to embodiments of the disclosure, FIG. 6A is a vertical cross-sectional view of the embodiment structure after forming a second mold compound matrix.

[0035] According to embodiments of the disclosure, FIG. 6B is a vertical cross-sectional view of the structure after forming a support wafer.

[0036] According to embodiments of the disclosure, FIG. 6A is a vertical cross-sectional view of the structure after separating the carrier wafer and formatting the array of solder material portions.

[0037] According to embodiments of the disclosure, FIG. 6A is a vertical cross-sectional view of a composite package.

[0038] According to embodiments of the disclosure, FIG. 7 is a structure including a composite package and a package substrate.

[0039] According to embodiments of the disclosure, FIG. 8 is a structure including a composite package, a package substrate, and a printed circuit board.

[0040] According to embodiments of the disclosure, FIG. 9 is a first alternative structure.

[0041] According to embodiments of the disclosure, FIG. 10 is a second alternative structure.

[0042] According to embodiments of the disclosure, FIG. 11 is a third alternative structure.

[0043] According to embodiments of the disclosure, FIG. 12 is a fourth alternative structure.

[0044] According to embodiments of the disclosure, FIG. 13 is a flowchart showing steps for forming a device structure.

[0045] Reference designators are as follows:

[0046] 8: substrate

[0047] 16: insulating layer

[0048] 22: liner

[0049] 24: via structure / TSV structure

[0050] 28: bonding structure

[0051] 30: semiconductor device

[0052] 61: encapsulation structure

[0053] 62: metal stack structure

[0054] 63: metal stack structure

[0055] 64: stack ring

[0056] 65: stack ring

[0057] 66: metal structure / metal stack structure

[0058] 67: metal stack structure

[0059] 70: dielectric material layer

[0060] 72: via structure

[0061] 74: line structure

[0062] 76: interconnect structure

[0063] 80: passivation dielectric layer

[0064] 81: passivation dielectric layer

[0065] 82: passivation dielectric layer

[0066] 83: passivation dielectric layer

[0067] 91: cap metal ring

[0068] 92: spacer metal ring

[0069] 95: metal bar structure

[0070] 98: bonding structure

[0071] 100: device area / printed circuit board / PCB

[0072] 110: substrate

[0073] 188: bonding pad

[0074] 190: solder joint

[0075] 192: fill material portion

[0076] 200: substrate

[0077] 214: via structure

[0078] 240: circuitry

[0079] 242: insulating layer

[0080] 244: interconnect

[0081] 248: bond pad

[0082] 260: circuitry

[0083] 262: insulating layer

[0084] 264: interconnect

[0085] 268: bond pad

[0086] 290: solder material portion

[0087] 292: filler material portion

[0088] 300: peripheral region

[0089] 310: wafer

[0090] 311: light-to-heat conversion layer / LTHC layer

[0091] 510: transistor

[0092] 532: source region

[0093] 535: channel

[0094] 538: drain region

[0095] 542: alloy portion

[0096] 548: alloy portion

[0097] 550: dielectric

[0098] 552: electrode

[0099] 560: capacitor

[0100] 562: electrode

[0101] 564: dielectric

[0102] 566: electrode

[0103] 621: via structure

[0104] 622: via structure

[0105] 623: via structure

[0106] 624: via structure

[0107] 625: via structure

[0108] 641: metal plate

[0109] 642: metal plate

[0110] 643: metal plate

[0111] 644: metal ring

[0112] 645: metal ring

[0113] 700: die

[0114] 701: die

[0115] 702: die

[0116] 703: die

[0117] 710: die

[0118] 721: frame

[0119] 722: frame

[0120] 740: support plate

[0121] 790: solder material portion

[0122] 792: filler material portion

[0123] 800: package

[0124] 1910: step

[0125] 1920: step

[0126] 1930: step

[0127] 1940: step

[0128] 70P: dielectric material portion

[0129] 721M: matrix

[0130] 722M: matrix

[0131] 740S: wafer

[0132] 82A: lower second passivation dielectric layer

[0133] 82B: upper second passivation dielectric layer

[0134] 92A: lower portion

[0135] 92B: upper portion

[0136] A-A’: plane

[0137] C: Area

[0138] CE:Edge

[0139] COD1:Distance

[0140] COD2:Distance

[0141] CR: Corner region

[0142] D-D': Plan / Section

[0143] E-E': Plan / Section

[0144] hd1: direction

[0145] hd2:direction

[0146] L1: Length

[0147] L2: Length

[0148] SCS: Slanted Corner Section

[0149] SW1: Side wall

[0150] SW2: Sidewall

[0151] UA:Unit Area

[0152] VP: plane

[0153] w: width DETAILED DESCRIPTION

[0154] The following provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, when the following description refers to forming a first component above or on a second component, it may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0155] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless otherwise noted, elements having the same or similar reference labels can have the same material formation and the same thickness, within a tolerance.

[0156] Various embodiments of the present disclosure provide a device structure including at least one semiconductor die configured to provide reduced stress within a molding compound die frame. Generally, an annular cap metal ring located at a periphery of the semiconductor die at a level of a passivation dielectric layer creates mechanical stress due to a mismatch in a coefficient of thermal expansion of the annular cap metal ring and a coefficient of thermal expansion of the molding compound die frame. Embodiments of the present disclosure provide an annular cap metal ring configured to reduce stress in a corner region of the semiconductor die. An edge ring seal structure can be provided in the semiconductor die such that the edge ring seal structure laterally surrounds a metal interconnect structure formed within a dielectric material layer. The edge ring seal structure can include four angled corner portions connecting corresponding longitudinal portions and corresponding lateral portions of the edge ring seal structure. Each corner region of the at least one passivation dielectric layer has no metal material other than a corresponding single angled bar portion of the cap metal ring. Alternatively or additionally, a spacer metal ring can be formed within the at least one passivation dielectric layer and can be located within the cap metal ring such that the spacer metal ring has a topmost surface located above a level including a topmost surface of the cap metal ring. The geometry of the cap metal ring and the layer composition of the at least one passivation dielectric layer can be selected to reduce stress in the semiconductor die when it is placed within the molding compound die frame. Various aspects of the present disclosure are now described with reference to the drawings.

[0157] According to embodiments of the present disclosure, FIG. 14 is a vertical cross-sectional view of a semiconductor die. According to embodiments of the present disclosure, FIG. 15 is a perspective view of an embodiment semiconductor die of FIG. 16 is a cross-section of the vertical cross-sectional view of FIG. 17 is a perspective view of an embodiment semiconductor die of FIG. 18 is a magnified view of region C of FIG. 19 is a perspective view of an embodiment semiconductor die of FIG. 1A is a cross-section of the vertical cross-sectional view of FIG. 1B is a vertical cross-sectional view of a first region of an embodiment semiconductor die of FIG. 1A is a vertical cross-sectional view of a vertical plane D-D' ofFIG. 1A is FIG. 1C embodiments of the semiconductor die along a vertical plane E-E' of FIG. 1B is a vertical cross-sectional view along the vertical plane E-E' of

[0158] According to embodiments of the disclosure, reference is made to FIG. 1D various views of a semiconductor die 700. Embodiments of the semiconductor die 700 are referred to as semiconductor die 700 hereinafter, and can be used subsequently as any semiconductor die, such as a first semiconductor die and / or a second semiconductor die formed in a corresponding mold compound die frame described below (e.g., placed and surrounded by a mold compound die frame). Each semiconductor die 700 can include a device region 100 and a peripheral region 300. The device region 100 includes semiconductor devices 30 and / or metal interconnect structures including metal interconnect structures 76, and the peripheral region 300 includes peripheral metal structures 66. Generally, the peripheral region 300 can have a frame shape (in a top view) having an outer rectangular perimeter and an inner octagonal perimeter having four major straight sides and four angled corner sides having a smaller lateral extent than any of the four major straight sides.

[0159] Generally, a semiconductor wafer including semiconductor substrates 8 can be provided. The semiconductor wafer can be a commercially available semiconductor wafer. For example, the semiconductor wafer can include a single crystal silicon wafer. Semiconductor devices 30 can be formed on, in, and / or over a top surface of the semiconductor substrates 8.

[0160] A through-substrate via (TSV) structure 24 can be formed in an upper portion of the semiconductor substrate within the device region 100. The TSV structure 24 can be electrically isolated from the semiconductor substrate 8 by an insulating liner 22. After forming the semiconductor devices 30, the dielectric material layer 70, the at least one passivation dielectric layer 80, and the front bond structure 98, the semiconductor wafer can be thinned from a backside to expose a backside surface of the TSV structure 24. After thinning the semiconductor substrate 8, a backside insulating layer 16 can be deposited on the recessed backside surface of the semiconductor substrate 8. A backside bond structure 28 can be formed on the backside surface of the TSV structure 24. The combination of the semiconductor wafer (thinned), the dielectric material layer 70, the at least one passivation dielectric layer 80 can be cut along a dicing channel to provide a plurality of semiconductor dies 700, one of which is shown in FIGS. 1A-1C

[0161] ​In one embodiment, the semiconductor device 30 can include at least one field effect transistor 510 (e.g., semiconductor device 30) located on or above the semiconductor substrate 8. Each field effect transistor 510 can include a source region 532, a drain region 538, a gate dielectric 550, a gate electrode 552, and a semiconductor channel 535. In some embodiments, one or more field effect transistors 510 can include a source metal-semiconductor alloy portion 542 and a drain metal-semiconductor alloy portion 548. At least one field effect transistor 510 can include at least one planar field effect transistor, at least one fin field effect transistor, at least one fully wrapped gate transistor, at least one two-dimensional channel field effect transistor, at least one vertical field effect transistor, and / or at least one thin film transistor.

[0162] Alternatively or additionally, the semiconductor device 30 can include at least one passive semiconductor device, such as at least one capacitor 560, such as at least one trench capacitor and / or at least one thin film capacitor. Each capacitor 560 can include a first electrode 562, a node dielectric 564, and a second electrode 566.

[0163] A dielectric material layer 70, a metal interconnect structure 76, and various peripheral metal stack structures 66 can be formed above the semiconductor substrate 8. The dielectric material layer 70 includes an interlayer dielectric (ILD) material, such as an undoped silicate glass, a doped silicate glass, a porous silicate glass, or a non-porous organic silicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide. In one embodiment, the dielectric material layer can include and / or can consist essentially of a non-polymeric dielectric material, i.e., a dielectric material that is not a polymeric material.

[0164] The metal interconnect structure 76 includes metal via structures 72 and metal line structures 74 formed within the dielectric material layer 70. The metal via structures 72 and the metal line structures 74 can provide electrical connections to and from the semiconductor device 30, and can provide an electrically conductive path between the front bond structure 98 and the TSV structure 24, and thus between the front bond structure 98 and the backside bond structure 28.

[0165] The peripheral metal structures 66 include an edge ring seal structure 61 (see, e.g., FIG. 1) and a backside seal structure 62 (see, e.g., FIG. 1). The edge ring seal structure 61 can include a metal ring 64 and a dielectric material 63. The backside seal structure 62 can include a metal ring 64 and a dielectric material 63. FIG. 1C and FIG. 1E), the edge ring seal structure 61 laterally surrounds each metal interconnect structure 76 as a continuous structure without any lateral openings therethrough, and includes ring portions that laterally surround corresponding enclosed regions at four corner regions of the semiconductor die 700. The edge ring seal structure 61 includes metal plates 641 and nested metal via structures 621. Each metal plate 641 laterally surrounds the entire region of the device region 100. Each nested via structure 621 laterally surrounds the entire region of the device region 100. Each nested metal via structure 621 located at a same via layer can be nested within or among the remaining nested metal via structures 621 located at the same via layer. As such, the metal plates 641 and the metal via structures 621 within the edge seal structure 61 can have respective openings therethrough that laterally surround the entire metal interconnect structure 76 in plan view (i.e., in a top view showing all element regions).

[0166] The peripheral metal structure 66 can optionally include inner metal stack structures 62 that are laterally surrounded by the edge ring seal structure 61 and laterally surround each metal interconnect structure. The inner metal stack structures 62 can be laterally spaced apart from one another. Each inner metal stack structure 62 can include a vertical alternating sequence of metal plates 642 and metal via structures 622.

[0167] The peripheral metal structure 66 can optionally include intermediate metal stack structures 63 that are laterally surrounded by corresponding rings within the edge ring seal structure 61, e.g. FIGS. 1A-1C As shown in the example. FIG. 1C In the example shown, the peripheral region 300 of the semiconductor die 700 includes four corner regions, each corner region including two enclosed regions laterally surrounded by the edge ring seal structure 61. The intermediate metal stack structures 63 can be located among the enclosed regions laterally surrounded by the ring portions of the edge ring seal structure 61. Each intermediate metal stack structure 63 can include a vertical alternating sequence of metal plates 643 and metal via structures 623.

[0168] The peripheral metal structure 66 can include an inner peripheral metal stack ring 64. The inner peripheral metal stack ring 64 laterally surrounds the edge ring seal structure 61 and includes a vertically alternating sequence of metal rings 644 and metal via structures 624. Each metal ring 644 can be topologically homeomorphic to a torus, i.e., can be continuously deformed into a torus shape without creating new holes and without removing any existing holes. Adjacent pairs of metal rings 644 can be vertically separated from one another by a plurality of metal via structures 624 that are laterally spaced apart from one another. Accordingly, lateral openings exist within the inner peripheral metal stack ring 64 between adjacent pairs of metal via structures 624. The presence of lateral perforations in the inner peripheral metal stack ring 64 helps to reduce mechanical stress that is generated by the inner peripheral metal stack ring 64 during thermal expansion of the semiconductor die 700.

[0169] The peripheral metal structure 66 can include an outer peripheral metal stack ring 65. The outer peripheral metal stack ring 65 laterally surrounds the inner peripheral metal stack ring 64 and the edge ring seal structure 61 and includes a vertically alternating sequence of metal rings 645 and metal via structures 625. Each metal ring 645 can be topologically homeomorphic to a torus. Adjacent pairs of metal rings 645 can be vertically separated from one another by a plurality of metal via structures 625 that are laterally spaced apart from one another. Accordingly, lateral openings exist within the outer peripheral metal stack ring 65 between adjacent pairs of metal via structures 625. The presence of lateral perforations in the outer peripheral metal stack ring 65 helps to reduce mechanical stress that is generated by the outer peripheral metal stack ring 65 during thermal expansion of the semiconductor die 700.

[0170] The peripheral metal structure 66 can optionally include outer metal stack structures 67 that are located outside of the outer peripheral metal stack ring 65 and the edge ring seal structure 61. The outer metal stack structures 67 can be located within the four corner regions of the semiconductor die 700. Each outer metal stack structure 67 can include a vertically alternating sequence of metal plates (not explicitly labeled) and metal via structures (not explicitly shown).

[0171] Generally, all of the metal via structures 72 of the metal interconnect structure 76 and all of the metal via structures (621, 622, 623, 624, 625) of the peripheral metal structure 66 located at the same via level can be formed simultaneously. Similarly, all of the metal line structures 74 of the metal interconnect structure 76 and all of the metal plates (641, 642, 643) and all of the metal rings (644, 645) of the peripheral metal structure 66 located at the same metal line level can be formed simultaneously. The metal via structures 72 of the metal interconnect structure 76, the metal via structures (621, 622, 623, 624, 625) of the peripheral metal structure 66, the metal line structures 74 of the metal interconnect structure 76, and the metal plates (641, 642, 643) and the metal rings (644, 645) of the peripheral metal structure 66 can each include a corresponding metal liner and a corresponding metal fill material portion. Each metal liner can include a metal barrier material, such as TiN, TaN, WN, MoN, or a combination thereof. Each metal fill material portion can include and / or consist essentially of a metal (such as W, Cu, Al, Co, Ru, and / or Mo) or an intermetallic alloy of at least two metals.

[0172] The edge ring seal structure 61 laterally surrounds the metal interconnect structure 76 without any lateral opening therethrough. Accordingly, a contiguous peripheral annular portion of the dielectric material layer 70 can be separated from a contiguous central portion of the dielectric material layer 70 by the edge ring seal structure 61. The contiguous peripheral annular portion of the dielectric material layer 70 is referred to in this disclosure as a peripheral dielectric material portion 70P.

[0173] According to one aspect of the present disclosure, the octagonal area defined by the inner sidewalls of the edge ring seal structure 61 (such as the innermost sidewalls of the metal plate 641 of the edge ring seal structure 61) defines four corner regions CR, each having a triangular area in a plan view. Each inner sidewall of the slanted corner portion SCS can define a corresponding vertical plane VP that contacts the inner sidewall of the slanted corner portion SCS and has the same lateral extent as the inner sidewall of the slanted corner portion SCS. In other words, the edge of the vertical plane VP can coincide with the vertically extended edge of the inner sidewall of the slanted corner portion SCS.

[0174] Reference is made to FIGS. 1A-1EA triangular region of the corner region CR can be defined by connecting two edges of the vertical plane VP and a location of the nearest corner edge CE of the semiconductor die 700 (i.e., the nearest one of the four corner edges CE of the semiconductor die 700). Thus, in plan view, each corner region CR can be defined as a region within the triangular region such that the vertices of the triangle in plan view include the points of the two vertically-extended edges of the slanted corner portion SCS and the nearest corner edge CE of the semiconductor die 700. Thus, each corner region of the at least one passivation dielectric layer 80 in the semiconductor die 700 is between the vertical plane VP that includes the inner sidewalls of the four slanted corner portions SCS of the edge ring seal structure 61 and the vertical line that includes the nearest corner edge CE of the semiconductor die 700.

[0175] The at least one passivation dielectric layer 80 is formed over the dielectric material layer 70. Each of the at least one passivation dielectric layer 80 can include a corresponding passivation dielectric material that retards or prevents diffusion of impurity elements, hydrogen, and / or moisture. Each of the at least one passivation dielectric layer 80 can include silicon nitride, silicon carbon nitride, undoped silicate glass, doped silicate glass, or a polymeric material (e.g., polyimide or resin).

[0176] In an embodiment, the at least one passivation dielectric layer 80 can include a plurality of passivation dielectric layers (81, 82, 83). For example, the at least one passivation dielectric layer 80 can include a first passivation dielectric layer 81 that contacts a topmost surface of the dielectric material layer 70, at least one second passivation dielectric layer 82 formed over the first passivation dielectric layer 81, and a third passivation dielectric layer 83 formed over the at least one second passivation dielectric layer 82. In one embodiment, the at least one second passivation dielectric layer 82 can include a lower second passivation dielectric layer 82A and an upper second passivation dielectric layer 82B.

[0177] A cap metal ring 91 can be formed on the top surface portion of the edge ring seal structure 61. In one embodiment, the cap metal ring 91 can be formed as a single annular structure that laterally surrounds the entire device region 100 in plan view. The cap metal ring 91 is formed as a unitary structure and can be topologically homeomorphic to a torus. In one embodiment, the cap metal ring 91 laterally surrounds the entire metal interconnect structure 76 in plan view, e.g., in a top-down view. In one embodiment, the cap metal ring 91 can be formed entirely within the region of the edge ring seal structure 61.

[0178] In one embodiment, a first passivation dielectric layer 81 can be deposited on a topmost surface of the dielectric material layer 70, and an annular line trench can be formed through the first passivation dielectric layer 81. At least one first metal material can be deposited in the annular line trench and above the first passivation dielectric layer 81, and can be patterned to form a cap metal ring 91. In this embodiment, the cap metal ring 91 can include a metal via portion extending vertically through the first passivation dielectric layer 81, and an annular metal plate portion covering a horizontal plane including a top surface of the first passivation dielectric layer 81. In one embodiment, the cap metal ring 91 can include a different metal material than the metal interconnect structure 76 and the edge ring seal structure 61. In one embodiment, the cap metal ring 91 can include a material selected from copper, aluminum-copper alloy, and aluminum-copper-silicon alloy. In one embodiment, the cap metal ring 91 can include an aluminum-based material including greater than 90 atomic percent aluminum.

[0179] In one embodiment, a width w of the cap metal ring 91, measured between the inner sidewall and the outer sidewall of the annular metal plate portion, can be in a range of 3.2 microns to 7.2 microns. A width of the metal via portion, measured at a level of the annular metal plate portion, can be less than the width w of the cap metal ring 91. According to an aspect of the disclosure, the width w of the cap metal ring 91 is selected to ensure that the cap metal ring 91 provides sufficient protection against diffusion of impurities and hydrogen atoms. Thus, the width w greater than 3.2 microns is preferred. Further, the width w of the cap metal ring 91 is selected to minimize negative stress effects due to thermal expansion of the cap metal ring 91. Thus, the width w less than 7.2 microns is preferred.

[0180] According to an aspect of the disclosure, the edge ring seal structure 61 laterally surrounds an irregular octagonal area of the semiconductor die 700 in a plan view. In one embodiment, the edge ring seal structure 61 includes two longitudinal portions parallel to the first sidewall SW1 of the semiconductor die 700, two lateral portions parallel to the second sidewall SW2 of the semiconductor die 700, and four slanted corner portions SCS connecting a respective one of the two longitudinal portions and a respective one of the two lateral portions. An angle between a longitudinal direction and each slanted corner portion SCS can be in a range of 30 degrees to 60 degrees, and can be 45 degrees.

[0181] Reference FIGS. 1A-1EIn the illustrated example, the two first sidewalls SW1 of the semiconductor die 700 can be parallel to the first horizontal direction hd1 and can have a first length LI that can be in a range of 1 millimeter (mm) to 40 mm, although smaller and larger lengths can also be used. The two second sidewalls SW2 of the semiconductor die 700 can be parallel to the second horizontal direction hd2 and can have a second length L2 that can be in a range of 1 mm to 40 mm, although smaller and larger lengths can also be used.

[0182] In one embodiment, the cap metal ring 91 can have a shape of an octagonal frame in a plan view. In one embodiment, the cap metal ring 91 includes two first bar portions parallel to the first sidewalls SW1 of the semiconductor die 700, two second bar portions parallel to the second sidewalls SW2 of the semiconductor die 700, and four inclined bar portions connecting a respective one of the two first bar portions and a respective one of the two second bar portions and located in a respective corner region CR of the at least one passivation dielectric layer 80. In one embodiment, the four inclined bar portions each have a width of 3.2 micrometers to 7.2 micrometers.

[0183] In one embodiment, each region where a respective one of the four inclined bar portions of the cap metal ring 91 adjoins the two first bar portions and the two second bar portions is laterally spaced from both the first sidewalls SW1 and the second sidewalls SW2 of the first semiconductor die by an offset distance, which is referred to in this disclosure as a corner offset distance. For example, each region where an inclined bar portion of the cap metal ring 91 adjoins a first bar portion of the cap metal ring 91 that extends laterally along the first horizontal direction hd1 can be laterally spaced from a proximal second sidewall SW2 of the semiconductor die 700 by a first corner offset distance COD1, and each region where an inclined bar portion of the cap metal ring 91 adjoins a second bar portion of the cap metal ring 91 that extends laterally along the second horizontal direction hd2 can be laterally spaced from a proximal first sidewall SW1 of the semiconductor die 700 by a second corner offset distance COD2.

[0184] According to an aspect of the disclosure, the first corner offset distance COD1 and the second corner offset distance COD2 can each be in a range of 27 microns to 90 microns. Generally, a large corner offset distance (COD1, COD2) increases the total area of the corner region CR and reduces the size of the device region 100 of the semiconductor die 700. Thus, the first corner offset distance COD1 and the second corner offset distance COD2 are preferably each less than 90 microns. However, a small corner offset distance (COD1, COD2) reduces the lateral distance between the lid metal ring 91 and the corner edge CE of the semiconductor die 700 and increases the mechanical stress generated by the thermal mismatch between the lid metal ring 91 and the subsequently formed molded compound die frame. Thus, the first corner offset distance COD1 and the second corner offset distance COD2 are preferably each greater than 27 microns.

[0185] The first length LI of the semiconductor die 700 and the first corner offset distance COD1 of the lid metal ring 91 determine the length of each first bar portion of the lid metal ring 91 extending laterally along the first horizontal direction hd1. Specifically, the length of each first bar portion of the lid metal ring 91 is equal to the first length L2 minus twice the first corner offset distance COD1. Similarly, the second length L2 of the semiconductor die 700 and the second corner offset distance COD2 of the lid metal ring 91 determine the length of each second bar portion of the lid metal ring 91 extending laterally along the second horizontal direction hd2. Specifically, the length of each second bar portion of the lid metal ring 91 is equal to the second length L2 minus twice the second corner offset distance COD2.

[0186] In one embodiment, the ratio of the length of one of the two first bar portions of the lid metal ring 91 to the length of one of the first sidewalls SW1 of the semiconductor die 700 (i.e., the first length LI) can be 0.8500 to 0.9948. In one embodiment, the ratio of the length of one of the two second bar portions of the lid metal ring 91 to the length of one of the second sidewalls SW2 of the semiconductor die 700 (i.e., the second length L2) can be 0.8500 to 0.9948.

[0187] Generally, a larger value of the ratio of the length of each first bar portion of the cap metal ring 91 to the first length LI and / or a larger value of the ratio of the length of each second bar portion of the cap metal ring 91 to the second length L2 increases the total area of the corner regions CR and reduces the size of the device region 100 of the semiconductor die 700. Thus, the ratio of the length of each first bar portion of the cap metal ring 91 to the first length LI and / or the ratio of the length of each second bar portion of the cap metal ring 91 to the second length L2 is preferably less than 0.9948. However, a smaller value of the ratio of the length of each first bar portion of the cap metal ring 91 to the first length LI and / or a smaller value of the ratio of the length of each second bar portion of the cap metal ring 91 to the second length L2 reduces the lateral distance between the cap metal ring 91 and the corner edges CE of the semiconductor die 700 and increases the mechanical stress generated by the thermal mismatch between the cap metal ring 91 and the subsequently formed mold compound die frame. Thus, the ratio of the length of each first bar portion of the cap metal ring 91 to the first length LI and / or the ratio of the length of each second bar portion of the cap metal ring 91 to the second length L2 is preferably greater than 0.8500.

[0188] In one embodiment, the at least one metal bar structure 95 can be optionally formed simultaneously with the cap metal ring 91 formed directly above the topmost surface of the peripheral metal stack ring 65. In this embodiment, at least one discrete line trench can be formed through the first passivation dielectric layer 81 along a direction parallel to the sidewalls of the semiconductor die 700, and at least one first metal material can be deposited in the at least one discrete line trench. The patterned portions of the at least one first metal material comprise the at least one metal bar structure 95. Each metal bar structure 95 can have a metal via portion extending vertically through the first passivation dielectric layer 81 and a metal line portion covering a horizontal plane including the top surface of the first passivation dielectric layer 81.

[0189] Each metal bar structure 95 can have the same material composition as the cap metal ring 91 and extends laterally parallel to the corresponding sidewall of the first and second sidewalls SW1 and SW2 of the semiconductor die 700. The at least one metal bar structure 95 is located in the peripheral region 300 between the outer sidewall of the cap metal ring and the sidewalls (SW1, SW2) of the semiconductor die 700. According to an aspect of the present disclosure, the four corner regions of the at least one metal bar structure 95 do not extend into the area of the corner regions CR in a plan view. Further, each corner region CR can not have any metal material other than the corresponding single sloped bar portion of the cap metal ring 91.

[0190] In one embodiment, a width of each metal rod structure 95 can be in a range from 3.2 microns to 7.2 microns, measured between the inner sidewall and the outer sidewall of the wire portion. The width of the metal via portion can be less than the width of the wire portion of the corresponding metal rod structure 95. According to an aspect of the disclosure, the width of each metal rod structure 95 is selected to ensure that each metal rod structure 95 provides sufficient protection against diffusion of impurities and hydrogen atoms. Thus, the width of each metal rod structure 95 is preferably greater than 3.2 microns. Further, the width of each metal rod structure 95 is selected to minimize negative stress effects due to thermal expansion of the corresponding metal rod structure 95. Thus, the width of each metal rod structure 95 is preferably less than 7.2 microns.

[0191] Optionally, a spacer metal ring 92 can be formed within a region of the cap metal ring 91 above a horizontal plane including the top surface of the first passivation dielectric layer 81. In this embodiment, the at least one first metal material can be patterned such that an annular remaining portion of the at least one first metal material covers a region of the inner metal stack structures 62. The annular remaining portion of the at least one first metal material constitutes a lower portion 92A of the spacer metal ring 92. As described above, the inner metal stack structures 62 can be laterally spaced apart from one another with an opening between each pair of laterally adjacent inner metal stack structures 62. The lower portion 92A of the spacer metal ring 92 is formed as a unitary structure that laterally surrounds the entire device region 100 of the semiconductor die 700.

[0192] A second passivation dielectric layer 82 can be formed over the first passivation dielectric layer 81, the cap metal ring 91, and the at least one metal rod structure 95. In one embodiment, the second passivation dielectric layer 82 can include a lower second passivation dielectric layer 82A that covers the top surface of the cap metal ring 91 and the at least one metal rod structure 95. An annular line trench can be formed over the lower portion 92A of the spacer metal ring 92. A second metal material can be deposited into the annular line trench and over the lower second passivation dielectric layer 82A, and can be patterned to form an upper portion 92B of the spacer metal ring 92. The upper portion 92B of the spacer metal ring 92 can include a metal via portion that extends vertically through the upper portion of the lower second passivation dielectric layer 82A, and an annular metal plate portion that covers a horizontal plane including the top surface of the lower second passivation dielectric layer 82A.

[0193] The second metal material can be the same as or different from the first metal material. In one embodiment, the upper portion of the spacer metal ring 92 can include a material selected from copper, aluminum-copper alloy, and aluminum-copper-silicon alloy. In one embodiment, the upper portion of the spacer metal ring 92 can include an aluminum-based material that includes greater than 90 atomic percent aluminum. In one embodiment, the second metal material can have a different material composition than the first metal material.

[0194] The combination of the lower portion 92A of the spacer metal ring 92 and the upper portion 92B of the spacer metal ring 92 make up the spacer metal ring 92. The vertical extent of the spacer metal ring 92 is vertically offset relative to the vertical extent of the cap metal ring 91. For example, the bottommost surface of the spacer metal ring 92 can be located above a horizontal plane that includes the bottommost surface of the cap metal ring 91, and can be located below a horizontal plane that includes the topmost surface of the cap metal ring 91. The topmost surface of the spacer metal ring 92 can be located above a horizontal plane that includes the topmost surface of the cap metal ring 91. In one embodiment, the lower portion 92A of the spacer metal ring 92 has the same material composition as the cap metal ring 91, and includes a horizontal surface that is within the horizontal plane that includes the topmost surface of the cap metal ring 91; the upper portion 92B of the spacer metal ring 92 has a different material composition than the cap metal ring 91.

[0195] An upper second passivation dielectric layer 82B can be formed over the lower second passivation dielectric layer 82A and the spacer metal ring 92. The combination of the lower second passivation dielectric layer 82A and the upper second passivation dielectric layer 82B make up the second passivation dielectric layer 82. Subsequently, a third passivation dielectric layer 83 can be formed over the second passivation dielectric layer 82. In one embodiment, the third passivation dielectric layer 83 can include and / or can consist essentially of silicon nitride. In one embodiment, the first passivation dielectric layer 81, the lower second passivation dielectric layer 82A, the upper second passivation dielectric layer 82B, and the third passivation dielectric layer 83 can include silicon nitride, silicon carbon nitride, a polymeric material (e.g., polyimide or a resin), undoped silicate glass, or doped silicate glass. In one embodiment, one, more, and / or each of the first passivation dielectric layer 81, the lower second passivation dielectric layer 82A, the upper second passivation dielectric layer 82B, and the third passivation dielectric layer 83 can include and / or can consist essentially of silicon nitride, silicon carbon nitride, or a polymeric material (e.g., polyimide or a resin). In one embodiment, the thickness of each of the first passivation dielectric layer 81, the lower second passivation dielectric layer 82A, the upper second passivation dielectric layer 82B, and the third passivation dielectric layer 83 can be in the range of 0.5 microns to 5 microns, such as from 1 micron to 3 microns, although lesser and greater thicknesses can also be used.

[0196] In one embodiment, the at least one passivation dielectric layer 80 includes a first passivation dielectric layer 81 that contacts a topmost surface of the dielectric material layer 70, at least one second passivation dielectric layer 82 that contacts a topmost surface of the cap metal ring 91, and a third passivation dielectric layer 83 that covers and is vertically spaced apart from the cap metal ring 91.

[0197] In one embodiment, at least one metal bar structure 95 is formed in a peripheral region of the at least one passivation dielectric layer 80 between the outer sidewall of the cap metal ring 91 and the sidewall of the first semiconductor die 700, the at least one metal bar structure 95 has the same material composition as the cap metal ring 91 and extends laterally parallel to a corresponding sidewall of the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 700. In one embodiment, the entirety of the region of the at least one passivation dielectric layer 80 between the outer sidewall of the cap metal ring 91 and the combination of the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 700 does not have metal material formed therein. Thus, any metal bar structure 95 is outside the region of each region of the at least one passivation dielectric layer 80 between the outer sidewall of the cap metal ring 91 and the combination of the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 700.

[0198] In one embodiment, the dielectric material layer 70 covers the semiconductor substrate 8 and has the metal interconnect structure 76 formed therein, and the edge ring seal structure 61 extends vertically from the semiconductor substrate 8 to a bottom surface of the at least one passivation dielectric layer 80.

[0199] The front bond structure 98 can be formed in a region of the device region 100 through the passivation dielectric layer 80. Subsequently, the backside of the semiconductor substrate 8 can be thinned from the backside, and a backside insulating layer 16 can be deposited on the recessed backside surface of the semiconductor substrate 8. The backside bond structure 28 can be formed on the backside surface of the TSV structure 24. Subsequently, the semiconductor wafer, the dielectric material layer 70, and the passivation dielectric layer 80 can be diced to form a plurality of semiconductor dies 700.

[0200] In general, the semiconductor die 700 can include the semiconductor substrate 8; the dielectric material layer 70 covering the semiconductor substrate 8; the edge ring seal structure 61 laterally surrounding the dielectric material layer 70 without any lateral opening therethrough; the at least one passivation dielectric layer 80 covering the dielectric material layer 70; and the cap metal ring 91 contacting a top surface portion of the edge ring seal structure 61 and laterally surrounding a lower portion 92A of the at least one passivation dielectric layer 80. The edge ring seal structure 61 includes two longitudinal portions parallel to the first sidewall SW1 of the first semiconductor die 700; two lateral portions parallel to the second sidewall SW2 of the first semiconductor die 700; and four slanted corner portions SCS connecting a corresponding one of the two longitudinal portions and a corresponding one of the two lateral portions. Each corner region of the at least one passivation dielectric layer 80 between a vertical plane VP and a vertical line does not have any metal material other than a corresponding single slanted bar portion of the cap metal ring 91, the vertical plane VP including an inner sidewall of the four slanted corner portions SCS of the edge ring seal structure 61, and the vertical line including a nearest corner edge CE of the first semiconductor die 700.

[0201] In one embodiment, the edge ring seal structure 61 can include four additional beveled corner sections outside of the four beveled corner sections SCS that have corresponding area overlaps with the cap metal ring 91. In this embodiment, the four beveled corner sections SCS that have portions with area overlaps with the cap metal ring 91 are referred to in this disclosure as inner beveled corner sections, and the four additional beveled corner sections outside of the inner beveled corner sections are referred to in this disclosure as outer beveled corner sections of the edge ring seal structure 61. The intermediate metal stack structure 63 can be located between a corresponding pair of an inner beveled corner section and an outer beveled corner section.

[0202] In one embodiment, the semiconductor die 700 can include a semiconductor substrate 8; a dielectric material layer 70 overlying the semiconductor substrate 8; an edge ring seal structure 61 laterally surrounding the dielectric material layer 70 without any lateral openings therethrough; at least one passivation dielectric layer 80 overlying the dielectric material layer 70; a cap metal ring 91 contacting a top surface portion of the edge ring seal structure 61 and laterally surrounding a lower portion 92A of the at least one passivation dielectric layer 80; a spacer metal ring 92 formed in the at least one passivation dielectric layer 80 and located within the cap metal ring 91 and having a topmost surface located above a horizontal plane containing a topmost surface of the cap metal ring 91.

[0203] According to embodiments of the present disclosure, FIG. 1D is a partial perspective top-down view of the embodiment semiconductor die of FIG. 1, with the embodiment semiconductor die in a second configuration. FIG. 1E is FIG. 1D is a magnified view of region B of

[0204] Referring to FIGS. 1A-1E and FIG. 1C the second configuration of the semiconductor die 700 can be derived from FIG. 1B the first configuration of the semiconductor die 700 shown in FIG. 1, or any of the alternative configurations described below that omit the formation of the at least one metal bar structure 95.

[0205] According to embodiments of the present disclosure, FIG. 2A is a partial perspective top-down view of the embodiment semiconductor die of FIG. 1, with the embodiment semiconductor die in a third configuration. FIG. 2B is FIG. 2A is a magnified view of region B of

[0206] Referring to FIG. 2A and FIG. 2B the third configuration of the semiconductor die 700 can be derived from FIGS. 1A-1E the first configuration of the semiconductor die 700 shown in FIG. 1, FIG. 3A and FIG. 3BThe second configuration of the semiconductor die 700 shown, or any of the additional alternative configurations to be described below, has the cap metal ring 91 formed so that the cap metal ring 91 covers the outer slanted corner portions SCS of the edge ring seal structure 61 and does not cover the inner slanted corner portions of the edge ring seal structure 61.

[0207] In a third configuration of the semiconductor die 700, the edge ring seal structure 61 includes two longitudinal portions parallel to the first sidewall SW1 of the first semiconductor die 700, two lateral portions parallel to the second sidewall SW2 of the first semiconductor die 700, and four slanted corner portions SCS (which are four outer slanted corner portions) connecting a respective one of the two longitudinal portions and a respective one of the two lateral portions. Each corner region of the at least one passivation dielectric layer 80 located between a vertical plane VP including an inner sidewall of the four slanted corner portions SCS of the edge ring seal structure 61 and a vertical line including the nearest corner edge CE of the first semiconductor die 700 does not have any metal material other than a respective single slanted bar portion of the cap metal ring 91. The cap metal ring 91 does not cover any inner slanted corner portions of the edge ring seal structure 61.

[0208] FIG. 3A is a vertical cross-sectional view of a first region of an example semiconductor die, where the example semiconductor die is in a fourth configuration. FIG. 3A corresponds to a vertical cross-section of FIG. 3B of FIG. 4D. FIGS. 1A-1E is a vertical cross-sectional view of a second region of an example semiconductor die, where the example semiconductor die is in a fourth configuration. FIG. 2A corresponds to a vertical cross-section of FIG. 2B of FIG. 4D.

[0209] Referring to FIG. 4A and FIG. 4A the fourth configuration of the semiconductor die 700 can originate from any of the previously described configurations or from any of the alternative configurations to be described below, which omit forming the spacer metal ring 92.

[0210] FIG. 1C is a vertical cross-sectional view of a region of an example semiconductor die, where the example semiconductor die is in a fifth configuration. FIG. 4B corresponds to a vertical cross-section of FIG. 4B of FIG. 4D.

[0211] Referring to FIG. 1C the fifth configuration of the semiconductor die 700 can originate from any of the previously described configurations or from any of the alternative configurations to be described below, which omit forming the spacer metal ring 92 and which omit forming the at least one metal bar structure 95.

[0212] FIG. 4A is a vertical cross-sectional view of a first region of an embodiment semiconductor die, where the embodiment semiconductor die is in a sixth configuration. FIG. 4B corresponds to the vertical cross-section D-D' of FIG. 4C FIG. 4C is a vertical cross-sectional view of a second region of an embodiment semiconductor die, where the embodiment semiconductor die is in a sixth configuration. FIG. 1C corresponds to the vertical cross-section E-E' of FIG. 4C

[0213] Referring to FIG. 5A and FIG. 5A , the sixth configuration of semiconductor die 700 can be derived from the fourth configuration of semiconductor die 700 shown in FIG. 1C and FIG. 5B by using a single homogenous passivation dielectric layer having a uniform material composition as the second passivation dielectric layer 82.

[0214] FIG. 5B is a vertical cross-sectional view of a region of an embodiment semiconductor die, where the embodiment semiconductor die is in a seventh configuration. FIG. 1C corresponds to the vertical cross-section E-E' of FIG. 5A

[0215] Referring to FIG. 5B , the seventh configuration of semiconductor die 700 can be derived from the fifth configuration of semiconductor die 700 shown in FIG. 4A by using a single homogenous passivation dielectric layer having a uniform material composition as the second passivation dielectric layer 82.

[0216] According to embodiments of the present disclosure, FIG. 4B is a vertical cross-sectional view of an intermediate structure comprising a carrier wafer and a plurality of first semiconductor dies 701 attached to the carrier wafer. FIG. 5C is a top view of the intermediate structure of FIG. 5C The vertical plane A-A' is the cross-section of the vertical cross-sectional view of FIG. 1C

[0217] Referring to FIG. 5C and FIG. 4C , a carrier wafer 310 is provided. The carrier wafer 310 can comprise a semiconductor wafer, an insulator layer, a conductive wafer, or a composite wafer that provides sufficient mechanical strength to the structure subsequently formed thereon. In an embodiment, the carrier wafer 310 can comprise a transparent wafer, such as a glass wafer or a sapphire wafer. The thickness of the carrier wafer 310 can be in the range of 500 micrometers to 2 millimeters, although smaller and larger thicknesses can also be used.

[0218] ​​​​A light-to-heat conversion (LTHC) layer 311 can be formed on a top surface of the carrier wafer 310. The LTHC layer 311 includes a material that absorbs light and converts it to heat. Commercially available materials are suitable for the LTHC layer 311. In general, the LTHC layer 311 can be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition, and can have a thickness of 10 nanometers (nm) to 1000 nm, although smaller and larger thicknesses can also be used.

[0219] The regions of the carrier wafer 310 can include a two-dimensional array of unit regions UA in which a two-dimensional array of fan-out packages will subsequently be formed. The two-dimensional array of unit regions UA can be configured as a two-dimensional periodic array, such as a two-dimensional rectangular array, or can be configured as a two-dimensional irregular array in which the unit regions UA repeat in a non-periodic manner. While the drawings of the present disclosure illustrate a two-dimensional periodic array of unit regions UA, the present disclosure expressly contemplates embodiments in which the unit regions UA are configured as a non-periodic two-dimensional array.

[0220] A pick-and-place tool including at least one camera and a pattern recognition program can be used to dispose the first semiconductor die 701 on the top surface of the LTHC layer 311. Each first semiconductor die 701 can be a reference FIG. 6A Any semiconductor die 700 described. In general, each first semiconductor die 701 can be placed so that the front bond structure 98 faces up or the backside bond structure 28 faces up. While the present disclosure is described using embodiments in which a single first semiconductor die 701 is placed within each unit region UA, the present disclosure expressly contemplates embodiments in which multiple first semiconductor dies 701 are placed within each unit region UA.

[0221] Referring FIG. 6B In the intermediate structure, a molding compound (MC) can be applied to the interstitial gaps of the first semiconductor die 701. The MC includes an epoxy-containing compound that can harden (i.e., cure) to provide a dielectric material portion having sufficient rigidity and mechanical strength. The MC can include an epoxy resin, a hardener, silica (as a filler material), and other additives. Depending on the viscosity and flowability, the MC can be provided in a liquid form or in a solid form. Liquid MCs can generally provide better handleability, good flowability, fewer voids, better filling, and fewer flow marks. Solid MCs can generally provide less cure shrinkage, better stand-off, and less die shift. A high filler content (e.g., 85% by weight) within the MC can shorten the time in molding, reduce molding shrinkage, and reduce molding warpage. A uniform filler size distribution in the MC can reduce flow marks and can enhance flowability.

[0222] The MC can be cured at a curing temperature to form a first molding compound matrix 721M, also referred to as a first MC matrix 721M. The first MC matrix 721M laterally surrounds each first semiconductor die 701. The first MC matrix 721M can be a continuous layer of material extending across the entire area of ​​the reconstituted wafer covering the carrier wafer 310. Excess portions of the first MC matrix 721M can be removed from above a horizontal plane containing the top surfaces of the first semiconductor die 701 by a planarization process, which can use chemical mechanical planarization (CMP). After the planarization process is performed, the top surfaces of the first semiconductor die 701 can be physically exposed. The top surfaces of the first semiconductor die 701 can be located within a horizontal plane containing the top surfaces of the first MC matrix 721M.

[0223] The first MC matrix 721M includes a plurality of first molding compound (MC) die frames located within the corresponding unit area UA. Each first MC die frame corresponds to a portion of the first MC matrix 721M located within the unit area UA (i.e., the area where a single interposer will be formed later). In other words, each portion of the first MC matrix 721M located within the corresponding unit area UA constitutes a first MC die frame. The first MC die frames are laterally adjacent to each other to provide a monolithic structure, which is the first MC matrix 721M. The first sidewall SW1 and the second sidewall SW2 of each first semiconductor die 701 contact the first molding compound matrix 721M.

[0224] refer to FIG. 6A In the intermediate structure, a group of at least one semiconductor die can be attached to each first semiconductor die 701. For example, a group of second semiconductor die 702 and third semiconductor die 703 can be attached to each first semiconductor die 701. In general, at least one second semiconductor die 702 can be bonded to each first semiconductor die 701. Each second semiconductor die 702 can have a reference FIG. 6A Any configuration of the semiconductor die 700 described above. Each second semiconductor die 702 can include an array of corresponding bonding structures, and the array of solder material portions 790 can be used to bond the second semiconductor die 702 to the front bonding structures 98 or the backside bonding structures 28 of the first semiconductor die 701. Similarly, at least one third semiconductor die 703 can optionally be bonded to each first semiconductor die 701. Each third semiconductor die 703 can have a reference FIG. 6AAny of the configurations of the semiconductor die 700 described. Each third semiconductor die 703 can include an array of corresponding bonding structures, and an array of solder material portions 790 can be used to bond the third semiconductor die 703 to additional front bonding structures 98 or additional backside bonding structures 28 of the first semiconductor die 701.

[0225] While the present disclosure is described with embodiments using second semiconductor dies 702 and third semiconductor dies 703 attached to each first semiconductor die 701, the present disclosure expressly contemplates embodiments where a single semiconductor die or three or more semiconductor dies are attached to the first semiconductor die 701 (or multiple first semiconductor dies) in each unit area UA.

[0226] Referring to FIG. 6B A bottom fill material can be applied to each gap between each first semiconductor die 701 and the corresponding overlying set of second semiconductor dies 702 and optional third semiconductor dies 703. A bottom fill material portion 792 can be formed within each unit area UA between the first semiconductor die 701 (or multiple first semiconductor dies) and the set of at least one overlying semiconductor die (e.g., second semiconductor dies 702 and third semiconductor dies 703).

[0227] An additional molding compound (MC) can be applied to the gaps of the second semiconductor dies 702 and optional third semiconductor dies 703. The additional molding compound can be cured at a curing temperature to form a second molding compound matrix 722M, which can also be referred to as a second MC matrix 722M. The second MC matrix 722M laterally surrounds each of the second semiconductor dies 702 and third semiconductor dies 703. The second MC matrix 722M can be a continuous layer of material that extends across the entire area of the reconstituted wafer that overlies the carrier wafer 310. Excess portions of the second MC matrix 722M can be removed from above the level of the top surfaces of the second semiconductor dies 702 and third semiconductor dies 703 by a planarization process that can use chemical mechanical planarization (CMP). After the planarization process is performed, the top surfaces of the second semiconductor dies 702 and third semiconductor dies 703 can be physically exposed. The top surfaces of the second semiconductor dies 702 and third semiconductor dies 703 can be within the level of the top surface of the second MC matrix 722M.

[0228] The second MC matrix 722M includes a plurality of second mold compound (MC) die frame portions located within a corresponding unit area UA. Each second MC die frame portion corresponds to a portion of the second MC matrix 722M located within a unit area UA (i.e., an area of a single interposer to be subsequently formed). In other words, each portion of the second MC matrix 722M located within a corresponding unit area UA constitutes a second MC die frame portion. The second MC die frame portions laterally abut one another to provide an overall structure, which is the second MC matrix 722M. The second sidewall SW2 of each second semiconductor die 702 contacts the second mold compound matrix 722M. The second MC matrix 722M laterally surrounds each underfill material portion 792.

[0229] Referring to FIGS. 1A-5C The support wafer 740S can be optionally attached to the reconstituted wafer including the first semiconductor die 701, the second semiconductor die 702, the third semiconductor die 703, the first MC matrix 721M, and the second MC matrix 722M. The support wafer 740S can include a semiconductor substrate, an insulating substrate, and a conductive substrate. The support wafer 740S has a thickness that provides sufficient mechanical support for the underlying assembly of the first semiconductor die 701, the second semiconductor die 702, the third semiconductor die 703, the first MC matrix 721M, and the second MC matrix 722M when the carrier wafer 310 is subsequently separated. For example, the thickness of the support wafer 740S can be in a range of 60 micrometers to 1 millimeter, although lesser and greater thicknesses can also be used.

[0230] Referring to FIG. 7 The ultraviolet radiation can be irradiated through the carrier wafer 310 onto the LTHC layer 311. The LTHC layer 311 generates heat and is decomposed when irradiated with the ultraviolet radiation. The carrier wafer 310 can be separated from the reconstituted wafer including the first semiconductor die 701, the second semiconductor die 702, the third semiconductor die 703, the first MC matrix 721M, and the second MC matrix 722M, and the support wafer 740S. A suitable cleaning process can be performed to remove residual material portions from the decomposed LTHC layer 311.

[0231] The bond structure of the first semiconductor die 701 can be physically exposed when the LTHC layer 311 is removed. The physically exposed bond structure of the first semiconductor die 701 can include the front bond structure 98 or the backside bond structure 28. The solder material portion 290 can be attached to the physically exposed bond structure of the first semiconductor die 701.

[0232] Referring to FIG. 8 , FIGS. 1A-5CThe reconstituted wafer is singulated along the singulation channels, which can coincide with the boundaries between adjacent pairs of unit areas UA. In other words, the first mold compound matrix 721M, the second mold compound matrix 722M, and the support wafer 740S are singulated along the singulation channels. Each singulated portion of the reconstituted wafer comprises a composite package 800. Each composite package 800 can comprise the first semiconductor die 701, the first mold compound die frame 721, which is a singulated portion of the first mold compound matrix 721M, the second semiconductor die 702, the optional third semiconductor die 703, the solder material portion 790 (also referred to as an inter-die bond solder material portion), the underfill material portion 792, the second mold compound die frame 722, which is a singulated portion of the second mold compound matrix 722M, and the support plate 740, which is a singulated portion of the support wafer 740S. While the present disclosure is described using embodiments in which the second semiconductor die 702 and the third semiconductor die 703 are bonded to the first semiconductor die 701 through the solder material portion 790, the present disclosure expressly contemplates embodiments in which the second semiconductor die 702 and / or the optional third semiconductor die 703 are attached to the first semiconductor die 701 through a metal-to-metal bond, in which mating pairs of the bond structure are in direct contact with each other and interdiffuse into each other to provide a bond interface.

[0233] With reference to FIGS. 1A-5C The package substrate 200 can be bonded to the composite package 800. The package substrate 200 can be a core package substrate that includes a core substrate 210, or a coreless package substrate that does not include a package core. Alternatively, the package substrate 200 can comprise a system-on-integrated packaging substrate (SoIS) that includes a redistribution layer, a dielectric interposer, and / or at least one interposer (e.g., a silicon interposer) formed therein. Such a system integrated package substrate can include layer-to-layer interconnections using solder material portions, micro-bumps, underfill material portions (e.g., a mold underfill material portion), and / or adhesive films. While the present disclosure is described using a core package substrate, it should be understood that the scope of the present disclosure is not limited to any particular type of substrate package. For example, a SoIS can be used in place of a core package substrate. In embodiments that use a SoIS, the core substrate 210 can comprise a glass epoxy board that includes an array of through-plate holes. An array of through-core via structures 214 that include a metal material can be disposed in the through-plate holes. Each of the through-core via structures 214 can or can not include a cylindrical hollow portion therein. Optionally, a dielectric liner (not shown) can be used to electrically isolate the through-core via structures 214 from the core substrate 210.

[0234] The package substrate 200 can include a board-side surface laminar circuit (SLC) 240 and a chip-side surface laminar circuit (SLC) 260. The board-side SLC can include a board-side insulating layer 242 having board-side wiring interconnects 244 formed therein. The chip-side SLC 260 can include a chip-side insulating layer 262 having chip-side wiring interconnects 264 formed therein. The board-side insulating layer 242 and the chip-side insulating layer 262 can include a photosensitive epoxy material that can be photo-patterned and subsequently cured. The board-side wiring interconnects 244 and the chip-side wiring interconnects 264 can include copper that can be deposited within a pattern in the board-side insulating layer 242 or the chip-side insulating layer 262 by electroplating.

[0235] In one embodiment, the chip-side surface laminar circuit 260 includes chip-side wiring interconnects 264 connected to an array of substrate bonding pads 268. The array of substrate bonding pads 268 can be configured to allow bonding by C4 solder balls. The board-side surface laminar circuit 240 includes board-side wiring interconnects 244 connected to an array of board-side bonding pads 248. The array of board-side bonding pads 248 is configured to allow bonding by solder joints having a larger size than C4 solder balls. While the present disclosure is described using embodiments in which the package substrate 200 includes both the chip-side surface laminar circuit 260 and the board-side surface laminar circuit 240, the present disclosure expressly contemplates embodiments in which one of the chip-side surface laminar circuit 260 and the board-side surface laminar circuit 240 is omitted or replaced with an array of bonding structures (e.g., micro-bumps). In illustrative examples, the chip-side surface laminar circuit 260 can be replaced with an array of micro-bumps or any other array of bonding structures.

[0236] The composite package 800 can be attached to the package substrate 200 by solder material portions 290, also referred to as package-substrate-bonding (FSB) solder material portions 290. Specifically, each FSB solder material portion 290 can be bonded to a corresponding one of the substrate bonding pads 268 and a corresponding one of the bonding structures located on the composite package 800. A reflow process can be performed to reflow the FSB solder material portions 290 so that the FSB solder material portions 290 can each be bonded to a corresponding one of the substrate bonding pads 268 and the bonding structures 28.

[0237] A bottom fill material can be applied into the gap between the composite package 800 and the package substrate 200. The bottom fill material can include any bottom fill material known in the art. A portion of the bottom fill material can be formed around the FSB solder material portion 290 in the gap between the composite package 800 and the package substrate 200. This portion of the bottom fill material is referred to in this disclosure as a package-substrate bottom fill material portion 292, or as a PS bottom fill material portion 292.

[0238] Referring to FIG. 9 , a printed circuit board (PCB) 100 can be provided that includes a PCB substrate 110 and PCB bond pads 188. The PCB 100 includes printed circuits (not shown) on at least one side of the PCB substrate 110. An array of solder joints 190 can be formed to bond the array of board-side bond pads 248 to the array of PCB bond pads 188. The solder joints 190 can be formed by disposing an array of solder balls between the array of board-side bond pads 248 and the array of PCB bond pads 188, and by reflowing the array of solder balls. An additional bottom fill material portion, referred to in this disclosure as a board-substrate bottom fill material portion 192, or as a BS bottom fill material portion 192, can be formed around the solder joints 190 by applying a bottom fill material and shaping it. The package substrate 200 is attached to the PCB 100 via the array of solder joints 190.

[0239] Referring to FIG. 10 , according to embodiments of the present disclosure, a first alternative embodiment structure can be derived from the embodiment structure shown in FIG. 11 by replacing one or more semiconductor dies (701, 702, 703) with at least one dummy die 710. In the example shown, FIG. 12 the third semiconductor die 703 in the embodiment structure of

[0240] Referring to FIG. 11 , according to embodiments of the present disclosure, a second alternative embodiment structure can be derived from the embodiment structure shown in FIG. 13 and FIG. 14 by omitting the support plate 740. In this embodiment, the process step for attaching the support wafer 740S can be omitted.

[0241] Referring to FIG. 15 , according to embodiments of the present disclosure, a third alternative embodiment structure can be derived from the embodiment structure shown in FIG. 14embodiment structure that does not use the second semiconductor die 702, the third semiconductor die 703, and the second mold compound die frame 722. In this embodiment, the process steps for attaching the support wafer 740S can be omitted. FIG. 14 and FIG. 16 the process steps described.

[0242] Referring to FIG. 14 According to embodiments of the present disclosure, a fourth alternative embodiment structure can result from FIG. 15 the embodiment structure that does not use the support plate 740. In this embodiment, the process steps for attaching the support wafer 740S can be omitted.

[0243] According to embodiments of the present disclosure, FIG. 17 is a flowchart showing steps for forming a device structure.

[0244] Referring to steps 1910 and FIG. 14 The dielectric material layer 70, the metal interconnect structure 76, and the edge ring metal structure 61 can be formed on the semiconductor substrate 8. The edge ring metal structure 61 laterally surrounds the metal interconnect structure 76 without any lateral opening therethrough.

[0245] Referring to steps 1920 and FIG. 8 A cap metal ring 91 is formed on a top surface portion of the edge ring metal structure 61. In plan view, the cap metal ring 91 laterally surrounds the entirety of the metal interconnect structure 76.

[0246] Referring to steps 1930 and FIG. 9 At least one passivation dielectric layer 80 can be formed on the dielectric material layer 70.

[0247] Referring to steps 1940 and FIG. 18 FIG. 17 FIG. 19 FIGS. 1A-5C FIGS. 1A-5C FIGS. 1A-5C FIGS. 1A-5C FIGS. 1A-5C The first semiconductor die 701 can be formed by dicing the at least one passivation dielectric layer 80, the dielectric material layer 70, and the semiconductor substrate 8.

[0248] In one embodiment, the edge ring seal structure 61 includes two longitudinal portions parallel to the first sidewall SW1 of the first semiconductor die 700, two lateral portions parallel to the second sidewall SW2 of the first semiconductor die 700, and four slanted corner portions SCS connecting a respective one of the two longitudinal portions and a respective one of the two lateral portions. In one embodiment, each corner region of the at least one passivation dielectric layer 80 located between a vertical plane VP and a vertical line does not have any metal material other than a corresponding single slanted rod portion of the cap metal ring 91, the vertical plane VP including an inner sidewall of the four slanted corner portions SCS of the edge ring seal structure 61, and the vertical line including a nearest corner edge CE of the first semiconductor die 700.

[0249] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, the present disclosure provides a device structure including a composite package. The composite package includes a first semiconductor die 701 including: a semiconductor substrate 8; a dielectric material layer 70 covering the semiconductor substrate 8; an edge ring seal structure 61 laterally surrounding the dielectric material layer 70 without any lateral opening therethrough; at least one passivation dielectric layer 80 covering the dielectric material layer 70; and a cap metal ring 91 contacting a top surface portion of the edge ring seal structure 61 and laterally surrounding a lower portion 92A of the at least one passivation dielectric layer 80, wherein: the edge ring seal structure 61 includes two longitudinal portions parallel to a first sidewall SW1 of the first semiconductor die 701; two lateral portions parallel to a second sidewall SW2 of the first semiconductor die 701; and four slanted corner portions SCS connecting a corresponding one of the two longitudinal portions and a corresponding one of the two lateral portions; and each corner region of the at least one passivation dielectric layer 80 between a vertical plane VP and a vertical line does not have any metal material other than a corresponding single slanted rod portion of the cap metal ring 91, the vertical plane VP including an inner sidewall of the four slanted corner portions SCS of the edge ring seal structure 61, and the vertical line including a nearest corner edge CE of the first semiconductor die 701.

[0250] In some embodiments, the device structure further includes a first mold compound die frame 721 laterally surrounding the first semiconductor die 701. In some embodiments, the device structure further includes: a second semiconductor die 702 located above or below the first semiconductor die 701 and bonded to the first semiconductor die 701; and a second mold compound die frame 722 laterally surrounding the first semiconductor die 701 and contacting a horizontal surface of the first mold compound die frame 721, wherein sidewalls of the second mold compound die frame 722 are vertically coincident with sidewalls of the first mold compound die frame 721.

[0251] In some embodiments, an entirety of a region of the at least one passivation dielectric layer 80 between an outer sidewall of the cap metal ring 91 and a combination of the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 701 does not have a metal material formed therein. In some embodiments, at least one metal rod structure 95 is formed in a peripheral region of the at least one passivation dielectric layer 80 between the outer sidewall of the cap metal ring 91 and a sidewall of the first semiconductor die 701, the at least one metal rod structure 95 having a same material composition as the cap metal ring 91 and extending laterally parallel to a corresponding sidewall of the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 701.

[0252] In some embodiments, the cap metal ring 91 includes two first bar portions parallel to the first sidewall SW1 of the first semiconductor die 701, two second bar portions parallel to the second sidewall SW2 of the first semiconductor die 701, and four inclined bar portions connecting a corresponding one of the two first bar portions and a corresponding one of the two second bar portions and located at a corresponding corner region of the at least one passivation dielectric layer 80. In some embodiments, each of the four inclined bar portions has a width in a range from 3.2 micrometers to 7.2 micrometers.

[0253] In some embodiments, each region where one of the four inclined bar portions adjoins a corresponding one of the two first bar portions and the two second bar portions is laterally spaced from a sidewall selected from both the first sidewall SW1 and the second sidewall SW2 of the first semiconductor die 701 by an offset distance in a range from 27 micrometers to 90 micrometers. In some embodiments, a ratio of a length of one of the two first bar portions to a length of one of the first sidewalls SW1 of the first semiconductor die 701 is in a range from 0.8500 to 0.9948, and a ratio of a length of one of the two second bar portions to a length of one of the second sidewalls SW2 of the first semiconductor die 701 is in a range from 0.8500 to 0.9948.

[0254] In some embodiments, the dielectric material layer 70 covers the semiconductor substrate 8 and has the metal interconnect structure 76 formed therein, and the edge cap seal structure 61 extends vertically from the semiconductor substrate 8 to a bottom surface of the at least one passivation dielectric layer 80. In some embodiments, the at least one passivation dielectric layer 80 includes a first passivation dielectric layer 81 contacting a topmost surface of the dielectric material layer 70, at least one second passivation dielectric layer 82 contacting a topmost surface of the cap metal ring 91, and a third passivation dielectric layer 83 covering and vertically spaced apart from the cap metal ring 91. In some embodiments, the first semiconductor die 701 includes a field effect transistor 510 on or above the semiconductor substrate 8.

[0255] According to another aspect of the present disclosure, the present disclosure provides a device structure including a composite package 800. The composite package 800 includes a first semiconductor die 701 including a semiconductor substrate 8, a dielectric material layer 70 covering the semiconductor substrate 8, an edge ring seal structure 61 laterally surrounding the dielectric material layer 70 without any lateral opening therethrough, at least one passivation dielectric layer 80 covering the dielectric material layer 70, a cap metal ring 91 contacting a top surface portion of the edge ring seal structure 61 and laterally surrounding a lower portion 92A of the at least one passivation dielectric layer 80, and a spacer metal ring 92 formed in the at least one passivation dielectric layer 80 and located within the cap metal ring 91 and having a topmost surface located above a horizontal plane including a topmost surface of the cap metal ring 91.

[0256] In other embodiments, the lower portion 92A of the spacer metal ring 92 has the same material composition as the cap metal ring 91 and includes a horizontal surface that is within a horizontal plane that includes a topmost surface of the cap metal ring 91; and the upper portion 92B of the spacer metal ring 92 has a different material composition than the cap metal ring 91.

[0257] In other embodiments, the at least one passivation dielectric layer 80 includes: a first passivation dielectric layer 81 that contacts a topmost surface of the dielectric material layer 70; at least one second passivation dielectric layer 82 that contacts a topmost surface of the cap metal ring 91; and a third passivation dielectric layer 83 that covers and is vertically spaced apart from the cap metal ring 91.

[0258] In yet another embodiment, the present disclosure provides a method of forming a device structure, including: forming a dielectric material layer, a metal interconnect structure, and an edge ring seal structure on a semiconductor substrate, wherein the edge ring seal structure laterally surrounds the metal interconnect structure without any lateral opening therethrough; forming a cap metal ring on a top surface portion of the edge ring seal structure, wherein the cap metal ring laterally surrounds an entirety of the metal interconnect structure in a top view; forming at least one passivation dielectric layer on the dielectric material layer; and forming a first semiconductor die by cutting the at least one passivation dielectric layer, the dielectric material layer, and the semiconductor substrate, wherein: the edge ring seal structure includes two longitudinal portions parallel to a first sidewall of the first semiconductor die; two lateral portions parallel to a second sidewall of the first semiconductor die; and four oblique corner portions connecting a corresponding one of the two longitudinal portions and a corresponding one of the two lateral portions; and each corner region of the at least one passivation dielectric layer between a vertical plane and a vertical line does not have any metal material other than a corresponding single oblique rod portion of the cap metal ring, the vertical plane including an inner sidewall of the four oblique corner portions of the edge ring seal structure, and the vertical line including a nearest corner edge of the first semiconductor die.

[0259] In yet other embodiments, further comprising a first mold compound matrix around the first semiconductor die, wherein the first sidewall and the second sidewall of the first semiconductor die contact the first mold compound matrix.

[0260] In yet other embodiments, further comprising: bonding a second semiconductor die to the first semiconductor die; forming a second mold compound matrix around the second semiconductor die; and cutting the first mold compound matrix and the second mold compound matrix, wherein remaining portions of the first mold compound matrix and the second mold compound matrix laterally surround the first semiconductor die and the second semiconductor die.

[0261] In yet other embodiments, an entirety of a region of the at least one passivation dielectric layer between an outer sidewall of the cap metal ring and a combination of the first sidewall and the second sidewall of the first semiconductor die does not have any metal material formed therein.

[0262] In yet other embodiments, at least one metal bar structure is formed in a peripheral region of at least one passivation dielectric layer located between the outer sidewall of the cap metal ring and the sidewall of the first semiconductor die, the at least one metal bar structure having the same material composition as the cap metal ring and extending laterally parallel to a corresponding sidewall of the sidewall of the first semiconductor die.

[0263] Various embodiments of the present disclosure can be used to reduce mechanical stress applied to corner regions of semiconductor die 700 (which is laterally surrounded by the mold compound die frame (721, 722) in the composite package 800) during operation due to the mismatch of the coefficient of thermal expansion between semiconductor die 700 and components of the mold compound die frame (721, 722). Simulations performed by the applicant of the present disclosure show that the mechanical stress at the four corner edges CE of the semiconductor die 700 of the present disclosure is reduced by up to 60%, and the mechanical stress at the junction between the inner inclined corner portion and a corresponding one of the longitudinal and lateral portions of the edge ring seal structure 61 is reduced by up to 30% compared to a reference structure that does not use any features of the present disclosure.

[0264] The above summarizes the features of several embodiments to make the person skilled in the art can more understand the idea of the embodiments of the present disclosure. Each embodiment described using the word "comprises" is also discloses additional embodiments, in which the word "comprises" is replaced by "consists essentially of" or the word "consists of", unless the present disclosure otherwise explicitly discloses. Whenever two or more elements are listed in the same paragraph or different paragraphs as alternatives, Markush groups comprising a list of two or more elements are also implicitly disclosed. Whenever auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the execution of a process step, embodiments in which the above-mentioned element or the above-mentioned process step is not executed are also explicitly envisaged, as long as the resulting device or apparatus can provide equivalent results. Therefore, whenever the formation of the above-mentioned element or the execution of the above-mentioned process step is omitted, the auxiliary verb "can" applied to the formation of the element or the execution of the process step should also be interpreted as "may" or "may or may not", which can provide the same results or equivalent results, including somewhat superior results and somewhat inferior results. The person skilled in the art should understand that other processes and structures can be easily designed or modified on the basis of the embodiments of the present disclosure to achieve the same purpose and / or advantages as the embodiments introduced herein. The person skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions and replacements can be made without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the appended claims.

Claims

1. A device structure comprising a composite package, characterized by, The composite package includes a first semiconductor die including: a semiconductor substrate; a plurality of dielectric material layers overlying the semiconductor substrate; an edge ring seal structure laterally surrounding the plurality of dielectric material layers; at least one passivation dielectric layer overlying the plurality of dielectric material layers; and a cap metal ring contacting a top surface portion of the edge ring seal structure and laterally surrounding a lower portion of the at least one passivation dielectric layer, wherein: the edge ring seal structure includes two longitudinal portions parallel to first sidewalls of the first semiconductor die, two lateral portions parallel to second sidewalls of the first semiconductor die, and four angled corner portions connecting a respective one of the two longitudinal portions and a respective one of the two lateral portions; and each corner region of the at least one passivation dielectric layer between a vertical plane including an inner sidewall of the four angled corner portions of the edge ring seal structure and a vertical line including a nearest corner edge of the first semiconductor die does not have any metal material other than a respective single angled rod portion of the cap metal ring.

2. The device structure comprising a composite package of claim 1, wherein, Further including a first mold compound die frame laterally surrounding the first semiconductor die.

3. The device structure comprising a composite package of claim 2, wherein, Further including: a second semiconductor die over or under the first semiconductor die and bonded to the first semiconductor die; and a second mold compound die frame laterally surrounding the first semiconductor die and contacting a horizontal surface of the first mold compound die frame, wherein sidewalls of the second mold compound die frame are vertically coincident with sidewalls of the first mold compound die frame. the cap metal ring includes two first rod portions parallel to the first sidewalls of the first semiconductor die, two second rod portions parallel to the second sidewalls of the first semiconductor die, and four angled rod portions connecting a respective one of the two first rod portions and a respective one of the two second rod portions and located at a respective corner region of the at least one passivation dielectric layer.

4. The device structure comprising a composite package according to any one of claims 1 to 3, wherein, a respective width of the four angled rod portions is in a range of 3.2 microns to 7.2 microns.

5. The device structure comprising a composite package of claim 4, wherein, each region of the four angled rod portions adjacent to a respective one of the two first rod portions and the two second rod portions is laterally spaced from a sidewall selected from both of the first sidewalls and the second sidewalls of the first semiconductor die by an offset distance in a range of 27 microns to 90 microns.

6. The device structure comprising a composite package of claim 4, wherein, 7. The device structure including a composite package of claim 4, wherein: a ratio of a length of one of the two first rod portions to a length of one of the first sidewalls of the first semiconductor die is in a range of 0.8500 to 0.9948; and a ratio of a length of one of the two second rod portions to a length of one of the second sidewalls of the first semiconductor die is in a range of 0.8500 to 0.9948.

8. The device structure including a composite package of any one of claims 1 to 3, wherein: the plurality of dielectric material layers overlying the semiconductor substrate have a plurality of metal interconnect structures formed therein; and the at least one passivation dielectric layer overlying the plurality of dielectric material layers has a plurality of metal interconnect structures formed therein. The edge ring seal structure extends vertically from the semiconductor substrate to a bottom surface of the at least one passivation dielectric layer.

9. The device structure comprising a composite package of any one of claims 1 to 3, wherein, The at least one passivation dielectric layer includes: a first passivation dielectric layer contacting a topmost surface of the plurality of dielectric material layers; at least a second passivation dielectric layer contacting a topmost surface of the cap metal ring; and a third passivation dielectric layer covering and vertically spaced apart from the cap metal ring.

10. A device structure comprising a composite package, characterized by The composite package includes a first semiconductor die including: a semiconductor substrate; a plurality of dielectric material layers covering the semiconductor substrate; an edge ring seal structure laterally surrounding the plurality of dielectric material layers without any lateral opening therethrough; at least one passivation dielectric layer covering the plurality of dielectric material layers; a cap metal ring contacting a top surface portion of the edge ring seal structure and laterally surrounding a lower portion of the at least one passivation dielectric layer; a spacer metal ring formed in the at least one passivation dielectric layer and within the cap metal ring and having a topmost surface above a horizontal plane containing a topmost surface of the cap metal ring.

Images