Constant current module and circuit structure

Abstract

The utility model provides a constant current module and a circuit structure. The constant current module comprises a high electron mobility field effect transistor based on III-V compounds and a source feedback resistor. The source feedback resistor comprises a built-in source resistor of the transistor or the built-in source resistor of the transistor and an external source resistor connected to the source. According to the utility model, the source feedback resistor is arranged in the constant current module, so that the gain is reduced, the stability is improved, the high-frequency performance is improved, the phenomena of ringing and the like are avoided, the transient response is not too slow, the pole frequency is more controllable, the occurrence probability of self-oscillation is reduced, and the service life of the constant current module is prolonged. The power density of the transistor can be controlled, the working temperature of the transistor can be reduced, the service life of the transistor can be prolonged, the knee-point voltage of the transistor can be obviously reduced, the influence caused by transistor production process errors can be reduced or eliminated, and the yield of the transistor can be improved.

Description

Technical Field

[0001] This utility model relates to a semiconductor constant current device, specifically to a constant current module based on GaN and other III-V compounds and its application in lighting and other fields. Background Art

[0002] The primary function of a semiconductor constant current device is to provide a constant current output in electronic circuits. This device automatically regulates the current flowing through it, ensuring that the current remains constant even when the power supply voltage changes. By limiting current flow, it helps prevent overcurrent, thus protecting sensitive electronic components from damage. It has various applications in circuits, such as LED lighting drivers, charging modules, and other current control modules.

[0003] Existing semiconductor constant current devices mainly include constant current diodes (CRDs) and Si-based constant current integrated circuit chips (constant current ICs). CRDs are primarily fabricated based on Si-based junction field-effect transistor (JFET) technology. Si-based constant current ICs are generally manufactured using semiconductor CBD processes. They control the output current by sampling the output voltage, passing it through a voltage comparator, and forming a closed-loop negative feedback. However, these Si-based constant current devices typically have the following drawbacks: low power density, high thermal resistance, and low operating temperature; low withstand voltage (CRDs are generally below 200V, and Si-based constant current ICs are generally below 700V); poor radiation resistance; and high losses at high frequencies. Summary of the Invention

[0004] The main objective of this invention is to provide a constant current module and circuit structure. The constant current module uses a high electron mobility field-effect transistor based on a III-V compound and sets a source feedback resistor that works in conjunction with the transistor, thereby overcoming the defects of the prior art.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this utility model includes:

[0006] One aspect of this invention provides a constant current module comprising a high electron mobility field-effect transistor based on a III-V compound and a source feedback resistor, wherein the source of the transistor is connected in series with the source feedback resistor, and the resistance value R of the source feedback resistor is... S Satisfy equations I to II;

[0007] Equation I is:

[0008]

[0009] Equation II is:

[0010]

[0011] Among them, V knee μ is the initial saturation voltage of the constant current module. n ε is the gate electron mobility of the transistor. * ε o These are the relative permittivity and the vacuum permittivity, respectively; d is the barrier layer thickness of the transistor; and W... g L is the gate width of the transistor. g R is the gate length of the transistor. D V is the parasitic drain resistance at the drain terminal of the transistor. GS V is the gate-source voltage of the transistor. TH L is the threshold voltage of the transistor. gd R is the gate-drain distance of the transistor. sh(2DEG) R is the sheet resistance of the two-dimensional electron gas in the transistor. C(2DEG) The contact resistivity between the source or drain ohmic metal of the transistor and the two-dimensional electron gas.

[0012] Another aspect of this utility model provides a circuit structure that includes the constant current module and at least one load module, wherein the load module is connected in series with a high electron mobility field-effect transistor within the constant current module.

[0013] Compared with the prior art, this utility model has at least the following beneficial effects:

[0014] Firstly, this utility model employs high electron mobility field-effect transistors based on III-V compounds, such as GaN-based HMET, within the constant current module. This provides advantages such as low initial saturation voltage, high driving efficiency, high reliability, high withstand voltage, strong resistance to lightning surges, strong radiation resistance, stable current in the constant current region, high driving power, high power density, low thermal resistance, and the ability to operate at high junction temperatures.

[0015] Secondly, by setting a source feedback resistor in the constant current module in conjunction with the transistor, this invention can significantly improve the load-carrying capacity of the constant current module, reduce its gain, improve its stability, enhance its high-frequency performance, avoid ringing and other phenomena, prevent its transient response from being too slow, and make its pole frequency more controllable, reducing the probability of self-oscillation. In addition, it helps to control its power density, reduce its operating temperature, extend its lifespan, and significantly reduce its knee voltage. Furthermore, it can reduce or eliminate the impact of transistor manufacturing process errors, improving device yield. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit schematic diagram of a constant current module in one embodiment of this utility model;

[0018] Figure 2 This is a small-signal model diagram of a constant current module in one embodiment of this utility model;

[0019] Figure 3 This is a schematic diagram illustrating the output impedance calculation principle of a constant current module in one embodiment of this utility model.

[0020] Figure 4 This is a small-signal equivalent circuit diagram of a constant current module in one embodiment of this utility model;

[0021] Figure 5 This is a schematic diagram of the parasitic parameter circuit structure of a constant current module in one embodiment of this utility model;

[0022] Figure 6 This is a schematic diagram illustrating the output impedance calculation principle of a constant current module in one embodiment of this utility model.

[0023] Figure 7 The transient response test results are for an existing passive feedback resistor constant current module.

[0024] Figure 8 This is the transient response test result of a constant current module with an active feedback resistor in one embodiment of this utility model;

[0025] Figure 9 This is a schematic diagram of a high-frequency model of a constant current module in one embodiment of this utility model;

[0026] Figure 10 This is an equivalent circuit diagram of a high-frequency model of a constant current module in one embodiment of this utility model;

[0027] Figure 11 This is a thermal resistance simulation test diagram of a constant current module in one embodiment of this utility model;

[0028] Figure 12 This is a test graph showing how the output characteristics of a constant current module change with W in one embodiment of this utility model;

[0029] Figure 13This is a schematic diagram of the structure of the first constant current module in one embodiment of this utility model;

[0030] Figure 14 This is a schematic diagram of the structure of the second constant current module in one embodiment of this utility model;

[0031] Figure 15 yes Figure 13 or Figure 14 The circuit structure diagram of the constant current module is shown below;

[0032] Figure 16 This is a schematic diagram of the structure of the third constant current module in one embodiment of this utility model;

[0033] Figure 17 yes Figure 16 The circuit structure diagram of the constant current module is shown below;

[0034] Figure 18 This is a circuit structure diagram of the fourth constant current module in one embodiment of this utility model;

[0035] Figure 19 yes Figure 18 The diagram shows the structure of the constant current module.

[0036] Figure 20 is included Figure 15 A schematic diagram of the lighting circuit of the constant current module shown.

[0037] Figure 21 is included Figure 17 A schematic diagram of the lighting circuit of the constant current module shown.

[0038] Figure 22 is included Figure 18 A schematic diagram of the lighting circuit of the constant current module shown.

[0039] Figure 23 This is a test graph showing the transfer characteristics of a GaN-based constant current IC in Example 1 at 25℃~250℃;

[0040] Figure 24 This is a pulse test diagram of a GaN-based constant current IC in Example 1 at 0-200V;

[0041] Figure 25 This is a test graph showing the performance of a GaN-based constant current IC under a 1.5kV pulse voltage in Example 1.

[0042] Figure 26 These are knee voltage test graphs of sample A in Example 1 and sample B in Comparative Example 1;

[0043] Figure 27The results are the DC test results of sample A in Example 1 at 25°C and the pulse test results in the range of 25 to 170°C.

[0044] Figure 28 The results are the DC test results of sample B in Comparative Example 1 at 25°C and the pulse test results in the range of 25 to 170°C.

[0045] Figure 29 These are the transconductance versus gate-source voltage curves of sample A in Example 1 and sample B in Comparative Example 1.

[0046] Figure 30 This is a schematic diagram of the structure of a transistor in Example 2;

[0047] Figure 31 This is a test graph showing the output characteristics of a GaN-based constant current module in Example 2 as a function of the resistance of an external source.

[0048] Figure 32 This is a schematic diagram of the structure of a transistor in Example 3. DETAILED DESCRIPTION

[0049] To fully understand the purpose, technical content, and features of this utility model, the following detailed description of the invention and its implementation process is provided in conjunction with specific embodiments and accompanying drawings.

[0050] Some embodiments of this utility model provide a constant current module comprising a high electron mobility field-effect transistor (HEMT) based on a III-V compound and a source feedback resistor, wherein the source of the transistor is connected in series with the source feedback resistor, and the resistance value R of the source feedback resistor is... S Satisfy equations I to II;

[0051] Equation I is:

[0052]

[0053] Equation II is:

[0054]

[0055] Among them, V knee μ is the initial saturation voltage of the constant current module. n ε is the gate electron mobility of the transistor. * ε o These are the relative permittivity and the vacuum permittivity, respectively; d is the barrier layer thickness of the transistor; and W... g L is the gate width of the transistor. g R is the gate length of the transistor. D V is the parasitic drain resistance at the drain terminal of the transistor. GSV is the gate-source voltage of the transistor. TH L is the threshold voltage of the transistor. gd R is the gate-drain distance of the transistor. sh(2DEG) R is the sheet resistance of the two-dimensional electron gas in the transistor. C(2DEG) The contact resistivity between the source or drain ohmic metal of the transistor and the two-dimensional electron gas.

[0056] In one embodiment, the source of the transistor is used to connect to the negative terminal of the power supply or to ground via the source feedback resistor, the gate of the transistor is used to connect to the negative terminal of the power supply or to ground, and the drain of the transistor is used to connect to the positive terminal of the power supply.

[0057] In one embodiment, the source feedback resistor includes the transistor's built-in source resistor or the transistor's built-in source resistor and an external source resistor connected in series with the transistor's source.

[0058] Furthermore, if the resistance values ​​of the built-in source resistor and the external source resistor are defined as R... IS 、R ES Then R S =R IS +R ES .

[0059] Where R ES When = 0, R IS Satisfy Equations III-IV;

[0060] Equation III is:

[0061]

[0062] Equation IV is:

[0063]

[0064] Among them, L gs I is the gate-source distance of the transistor. DS(sat) The saturation current intensity of the transistor.

[0065] Where R ES / R IS When >5, define R S =R ES And R ES Satisfying the V-type and VI-type;

[0066] Equation V is:

[0067]

[0068] Formula VI is:

[0069]

[0070] Among them, L ES W is the distance between the two ohmic access regions in the external source resistor. ES R is the width of the external source resistor. sh(RES) R is the sheet resistance of the external source resistor. C(RES) To match the contact resistivity between the ohmic metal in the ohmic access area and the external source resistor.

[0071] The following combination Figure 1 This invention provides a typical embodiment of the present invention to illustrate the basic working principle of a constant current module (hereinafter referred to as "constant current IC"), wherein the source terminal of HEMT 11 (hereinafter referred to as "device") is connected in series with a source feedback resistor 12, and the drain current I of HEMT is... D Due to the negative feedback effect of the source feedback resistor, a constant current output is formed. Figure 1 In the diagram, "+" and "-" represent the positive and negative terminals of the constant current module, respectively. 13 represents the load.

[0072] The resistance value R of the source feedback resistor S Under the condition that equations I to IV are satisfied, when the drain voltage V of HEMT D When rising, I D The voltage also begins to rise, and the voltage drop across the source feedback resistor also begins to rise, causing the voltage applied across the HEMT to be less than V. D The increase in I, thus making D The rate of increase decreases, which in turn manifests as a decrease in the transconductance of the constant current module.

[0073] For further details, please refer to Figure 2 The small-signal model of the constant current IC is shown, and the specific calculation process of the small-signal model is shown in Equations 1 to 3 below.

[0074]

[0075] As can be seen from the above calculations, With R S G gets bigger m Change to g m The weak function, i.e., I D It also becomes g m The constant current IC of this invention is more stable during operation after the source feedback resistor is added, as it is a weak function of the current.

[0076] For further details, please refer to Figure 3 As shown, the output impedance of the constant current IC described in this invention is calculated based on equations 4 to 6 below.

[0077]

[0078] R out =R S +(1+g m *R S )*r O Formula 6

[0079] As can be seen, after adding the source feedback resistor, the output impedance of the constant current IC changes from r O Change to [R] S +(1+g m *R S )*r O The efficiency is significantly improved, thus greatly enhancing its load-bearing capacity.

[0080] It should be noted that other second-order effects of the constant current IC were not considered in the above calculations. In the above calculations 1 to 6, r O R is the output impedance of the constant current IC. L This represents the resistance value of the load.

[0081] For further details, please refer to Figure 4 As shown, if other second-order effects of the constant current IC are also disregarded, and the gain of the constant current IC of this invention is calculated based on the following equations 7 to 10, where the current I flowing through the load is... X for:

[0082]

[0083] The voltage V across the source feedback resistor X for:

[0084]

[0085] Conversely, when the source feedback resistor is absent, the gain of the corresponding circuit is -g. m *R L .

[0086] Based on the above, it can be seen that after adding the source feedback resistor, and with the source feedback resistor's resistance value R... S When equations I to IV are satisfied, the gain of the constant current IC decreases and its stability improves.

[0087] Furthermore, in this invention, by adding the source feedback resistor, the high-frequency performance of the constant current IC can be improved, especially when a large step signal is applied to the drain. Due to the introduction of the source feedback resistor, the device will not experience ringing or other phenomena. In some cases, when a high-frequency signal is applied to the constant current IC, the parasitic parameters of the device need to be considered, and the corresponding equivalent circuit structure is as follows: Figure 5As shown, C GS 、C GD 、C DS These are the gate-source, gate-drain, and source-drain capacitances of the device, respectively.

[0088] In this invention, the device typically applies a voltage to the drain and grounds the gate during operation. For ease of calculation, C can be ignored. GS 、C DS The small-signal model for calculating output impedance is as follows: Figure 6 As shown, without considering other higher-order effects of the device, the corresponding calculation process is shown in Equations 11 to 14.

[0089] Among them, flowing through C GD Current I CGD for:

[0090] I CGD =V X *s*C GD Formula 11

[0091] Flow through R S Current I RS for:

[0092] I RS =I X -V X *s*C GD Formula 12

[0093] The current equation of the loop is

[0094]

[0095] When R S When the value is 0, the output impedance of the device is It can be seen that after the source feedback resistor is added, both the resistive and capacitive parameters of the output impedance of the constant current IC are improved.

[0096] When the source feedback resistor is absent, applying a large step signal to the drain of a device will result in the transient response of the corresponding constant current IC as follows: Figure 7 As shown, a noticeable ringing phenomenon can be observed. When the source-side feedback resistor is added, the transient response of the constant current IC based on the same device is as follows: Figure 8 As shown, the ringing phenomenon disappears. Furthermore, adding the source feedback resistor can prevent the ringing phenomenon without slowing down the transient response of the constant current IC.

[0097] In this invention, adding the source feedback resistor makes the pole frequency of the constant current IC controllable, reducing the probability of self-oscillation in the system. For example... Figure 9The high-frequency model of a constant current IC is shown. If the device used is a GaN-based HEMT, unlike MOS, GaN-based HEMTs do not have a substrate potential, so C does not need to be considered. DB Capacitor. R in In practical applications, it refers to the output impedance of the preceding stage; when used as a discrete component, it can be the gate parasitic resistance of the device. R D It is the load in the circuit. For example... Figure 10 The equivalent circuit diagram of the constant current IC is shown below. Its high-frequency gain can be derived from this diagram. The specific calculation process is shown in Equations 15 to 24 below.

[0098] Among them, flowing through R D Current I X for:

[0099]

[0100] Write the current equations for the input and output nodes respectively.

[0101]

[0102] Simplifying the two equations above, we get

[0103]

[0104] The gain of the circuit is

[0105]

[0106] Organized

[0107]

[0108] From the perspective of the transfer function, it is a second-order transfer function, including one zero and two poles. The zero and R... S It's irrelevant; this is predictable. This zero point is due to the input and output passing through C. GD Directly coupled, with R S There is no direct relationship.

[0109] Since the expression for the transfer function is too complex, the principal pole approximation can be used, |ω p1 |<<|ω p2 |

[0110]

[0111] If ω p2 The distance to the origin is ω p1 The distance to the origin is much greater, then That is, the coefficient of s is equal to

[0112] Therefore, the principal pole is

[0113]

[0114] At the same time, the second pole, s, can also be calculated. 2 The coefficient is Therefore, the secondary pole is

[0115]

[0116] R is contained in both the principal pole and the secondary pole. S It can be controlled by R S To determine the poles of the control system.

[0117] V in Equation 15-19 x The excitation voltage added to facilitate the calculation of the output impedance is a transient variable and can be any value.

[0118] In this invention, adding the source feedback resistor allows for control of the power density of the constant current IC, reducing its operating temperature and extending its lifespan. Without the source feedback resistor, the constant current IC's output current is at a large value, resulting in a high power density that cannot be improved. With the source feedback resistor, the constant current IC's output current becomes controllable, allowing control over the size of the source feedback resistor to regulate the output current. Simultaneously, the power density of the constant current IC also becomes controllable. For example, as shown... Figure 11 As shown, if the thermal resistance of the Si-based GaN HEMT device is 53.57 K / W and its current is 40 mA, and the maximum operating junction temperature is 170 °C, then the maximum allowable operating voltage of the corresponding constant current IC is ~68 V. If the source feedback resistor is used for modulation, its current can be controlled at 20 mA and the maximum operating voltage can be expanded to 136 V, which greatly increases the application range of the constant current IC.

[0119] The addition of the source feedback resistor in this invention can also control the output current and reduce the initial saturation voltage of the device. During normal operation, a constant current IC typically operates in two regions: a linear region and a saturation region. When the drain voltage is low (below the initial saturation voltage), the device operates in the linear region, following the formula:

[0120]

[0121] When the drain voltage increases to the initial saturation voltage, the device begins to enter the saturation region, following the formula:

[0122]

[0123] Initial saturation voltage (V) knee The initial saturation voltage (IVS) is an important performance parameter of constant current ICs. It represents the voltage applied to the drain terminal when the device transitions from the linear region to the saturation region. Parameters affecting the IVS voltage include: R... S 、R D , I DS(sat) The relationship between them is as follows:

[0124]

[0125] When the source feedback resistor is added, R S Get bigger, and I DS(sat) It becomes smaller. If we want to improve V by changing W... knee For example, regarding a constant current IC of this utility model, Figure 12 The diagram shows the changes in saturation current and initial saturation voltage as W changes. It can be seen that as W changes, V... knee It remains unchanged. Due to the presence of the source feedback resistor, the knee voltage of the constant current IC is significantly reduced. In Equations 25-26, V DS R is the source-drain voltage of the transistor. D This represents the drain parasitic resistance; the definitions of the other parameters are as described above.

[0126] In mass production, adding the source feedback resistor can improve device yield. During manufacturing processes, errors inevitably exist, causing the output current of the produced device to deviate from the predetermined value. Adding the source feedback resistor can correct this output current, and this correction is reflected in the device's transfer characteristics. Taking a device with a gate voltage of 0V as an example, without the source feedback resistor, the current produced by the process is within ±5% * I of the set value. Assuming the added R... S The resistance value is R S The slope of the load line is -(1 / R) S The angle θ between the straight line and the x-axis is θ = arctan(-(1 / R)). S The relationship between the effective correction curve of the feedback resistor and the transfer curve is ±5% * I * sin(90° - arctan(-(1 / R)). S This can be further simplified to Therefore, the introduction of the source feedback resistor can improve the yield of the process.

[0127] In one embodiment, the external source resistor includes, but is not limited to, heterojunction 2DEG resistors, n-GaN resistors, p-GaN resistors, silicon resistors, metal thin-film resistors, metal compound thin-film resistors, and resistors formed from other materials. The metal thin-film resistor can be made of Ni, Al, Cr, Ti, W, Au, Ag, Pd, or a multilayer composite structure of these metals. The metal compound thin-film resistor can be made of TiN, TaN, ITO, IGZO, etc., and is not limited to these.

[0128] In one embodiment, the constant current module includes a semiconductor layer, the semiconductor layer including a channel layer and a barrier layer disposed on the channel layer, the source, drain and gate being disposed on a designated region of the semiconductor layer and electrically combined with the channel layer and the barrier layer in the designated region to form the transistor.

[0129] In one embodiment, the external source resistor is integrated with the transistor within a chip, the chip including the semiconductor layer having a first region and a second region, the first region and the second region being distributed along a direction parallel to the surface of the semiconductor layer, the first region being the designated region, and at least a portion of the semiconductor material in the second region being electrically bonded to the positive and negative electrodes to form the external source resistor; or, the external source resistor includes a resistive material layer disposed on the second region, the resistive material layer being electrically connected to the source of the transistor and the negative electrode of the power supply, respectively.

[0130] In one embodiment, the external source resistor comprises a two-dimensional electron gas distributed in the second region, or the external source resistor comprises a semiconductor resistor layer formed by transforming at least a portion of the barrier layer and / or channel layer in the second region, wherein the resistance of the semiconductor resistor layer is greater than the resistance of the barrier layer and / or channel layer; and, within the semiconductor layer, the transistor and the external source resistor are electrically isolated from each other.

[0131] In one embodiment, the resistive material layer comprises a metal thin film and / or a metal compound thin film coated on the second region.

[0132] In one embodiment, the semiconductor layer is disposed within a chip, and the chip is disposed separately from the external source resistor. For example, the chip and the external source resistor can be disposed as separate devices on a circuit board and electrically connected via conductive lines in the circuit board.

[0133] In one embodiment, the channel layer includes, but is not limited to, GaN, AlGaN, InGaN, or AlInGaN.

[0134] In one embodiment, the barrier layer includes, but is not limited to, AlGaN, AlInN, AlN, AlScN, or AlInGaN.

[0135] In one embodiment, the transistor comprises a GaN-based HEMT.

[0136] In one embodiment, the transistor is a depletion-type HEMT.

[0137] In one embodiment, the transistor has a Schottky gate contact structure or a MIS gate structure.

[0138] In one embodiment, the transistor is a field-plate-free structure, or the transistor has one or more field plates, such as one or more of a gate field plate, a source field plate, and a drain field plate.

[0139] In one embodiment, the semiconductor layer is further provided with an electrical isolation structure, which includes an ion implantation isolation structure or a mesa etching isolation structure, and can be formed by processing the semiconductor layer by ion implantation, dry etching or wet etching.

[0140] In one embodiment, the semiconductor layer is disposed on a substrate, which may be a homogeneous substrate or a heterogeneous substrate of the semiconductor layer, such as, but not limited to, Si, SiC, sapphire, GaN, AlN, diamond substrates, or composite substrates thereof.

[0141] In one embodiment, the semiconductor layer may further include conventional structural layers such as buffer layers, space layers, and capping layers.

[0142] In one embodiment, conventional structural layers such as an insulating dielectric layer and a passivation layer may also be disposed on the semiconductor layer. The material of the insulating dielectric layer may be selected from one or more combinations of insulating materials such as silicon nitride, silicon oxide, aluminum oxide, high dielectric constant materials, organic polymers, ceramic materials, and oxide semiconductors.

[0143] In one embodiment, the chip may further include encapsulating adhesive, encapsulation bracket, etc. Applicable encapsulation brackets include, but are not limited to, PPA, STC, PLCC, SMA, SMB, SMC, SMF, SOT, SOP, TSSOP, ceramic brackets, and metal brackets. Corresponding packaging methods include, but are not limited to, TO, DIP, SOP, QFP, PLCC, BGA, and CSP.

[0144] For example, please refer to Figure 13In a typical embodiment of this invention, a constant current module 200 integrates an HMET (Heterojunction Electron Transistor) with an external source resistor within a single chip. The chip includes a semiconductor layer comprising a channel layer 202 and a barrier layer 203 sequentially grown on a substrate 201. The channel layer 202 and barrier layer 203 form a heterojunction, in which a two-dimensional electron gas 204 (2DEG) is distributed. The semiconductor layer also has a first region and a second region along a direction parallel to its surface. The first region has a source 205, a gate 206, and a drain 207 of the HEMT (Heterojunction Electron Transistor) respectively disposed on its surface to facilitate the formation of the HMET in conjunction with the heterojunction in the first region. The second region has a positive electrode 208 and a negative electrode 209 of an external source resistor respectively disposed on its surface to facilitate the formation of the external source resistor in conjunction with the two-dimensional electron gas in the second region; that is, the external source resistor can be a heterojunction 2DEG resistor. The source 205, drain 207, positive electrode 208, and negative electrode 209 can each form an ohmic contact with the semiconductor layer. An electrical isolation region 210 is distributed between the first and second regions to electrically isolate the external source resistor from the HEMT. This electrical isolation region can extend from the surface of the barrier layer to the interior of the channel layer, or from the surface of the barrier layer to the substrate surface. This electrical isolation region can be a high-resistivity region formed by ion implantation of the semiconductor layer, or a groove formed by etching the semiconductor layer. The resistance value of the internal source resistor of the HEMT mainly depends on the two-dimensional electron gas in the gate-source region and the source ohmic contact resistance, while the resistance value of the external source resistor mainly depends on the two-dimensional electron gas in the second region, which are respectively as follows: Figure 13 As shown in dashed boxes a and b, the gate 206 can be electrically connected to the negative terminal 209 of the external source resistor and the negative terminal of the chip via a side lead 211. Simultaneously, a thickened electrode and a source field plate 212 can be disposed above the gate 206. The thickened electrode and source field plate 212 are partially electrically contacted with the source 205 and electrically connected to the positive terminal 208 of the external source resistor via a wire. The drain 207 is electrically connected to the positive terminal of the chip. One or more insulating dielectric layers 213 can also be disposed on the surface of the semiconductor layer in this chip to isolate the aforementioned electrodes from each other and achieve passivation of the semiconductor layer surface. These one or more insulating dielectric layers can be continuous layers, and the aforementioned electrodes can be exposed through corresponding windows opened in these continuous insulating dielectric layers. Furthermore, a gate field plate structure that cooperates with the gate can also be disposed in this chip.

[0145] For example, please refer to Figure 14In another typical embodiment of this invention, the HMET within a constant current module 300 and an external source resistor can also be integrated into a single chip. This chip includes a semiconductor layer comprising a channel layer 302 and a barrier layer 303 sequentially grown on a substrate 301. The channel layer 302 and the barrier layer 303 form a heterojunction, in which a two-dimensional electron gas 304 (2DEG) is distributed. Simultaneously, the semiconductor layer has a first region and a second region along a direction parallel to its surface. The source 305, gate 306, and drain 307 of the HEMT are respectively disposed on the surface of the first region to facilitate the formation of the HMET in conjunction with the heterojunction in the first region. The surface of the second region is respectively provided with the positive electrode 308 and the negative electrode 309 of the external source resistor. Simultaneously, a portion of the semiconductor layer in this second region is transformed into a semiconductor resistive layer 310 through ion implantation, ion diffusion, or other methods. The remaining semiconductor layer in this second region is transformed into a high-resistivity semiconductor layer 311 through ion implantation, ion diffusion, or other methods, thereby forming an electrical isolation region in this second region. The semiconductor resistive layer can be surrounded or covered by the high-resistivity semiconductor layer, thus electrically isolating it from the HMET. The positive electrode 308 and the negative electrode 309 are electrically connected to the semiconductor resistive layer 310 to form the external source resistor; that is, the external source resistor can be an n-GaN resistor or a p-GaN resistor. The source electrode 305 and the drain electrode 307 can form ohmic contacts with the semiconductor layer, respectively. The drain electrode 307 is electrically connected to the positive electrode of the chip. Furthermore, one or more electrically isolated regions can be formed around the HEMT in the semiconductor layer, extending from the barrier layer surface to the channel layer or from the barrier layer surface to the substrate surface. These electrically isolated regions can be high-resistivity regions formed by ion implantation of the semiconductor layer or grooves formed by etching the semiconductor layer. The resistance value of the HMT's built-in source resistor mainly depends on the two-dimensional electron gas in the gate-source region and the source ohmic contact resistance, while the resistance value of the external source resistor mainly depends on the resistance of the semiconductor resistive layer, as shown below. Figure 14 As shown in the dashed boxes a' and b', the gate 306 can be electrically connected to the negative terminal 309 of the external source resistor and the negative terminal of the chip via a side lead 312. Simultaneously, a thickened electrode and a source field plate 313 can be disposed above the gate 306. The thickened electrode and source field plate 313 are partially electrically contacted with the source electrode 305 and electrically connected to the positive terminal 308 of the external source resistor via a wire. One or more insulating dielectric layers 314 can also be disposed on the surface of the semiconductor layer in this chip to isolate the aforementioned electrodes from each other and achieve passivation of the semiconductor layer surface. These one or more insulating dielectric layers can be continuous layers, and the aforementioned electrodes can be exposed through corresponding windows opened in these continuous insulating dielectric layers.

[0146] In some cases, one or more layers of metals such as Ni, Al, Cr, Ti, W, Au, Ag, or Pd, or their alloys, can be deposited on the second region as a resistive layer and electrically connected to the positive and negative terminals of the external source resistor to form an external source resistor. Alternatively, one or more layers of metal compounds such as TiN, TaN, ITO, or IGZO can be deposited on the second region as a resistive layer and electrically connected to the positive and negative terminals of the external source resistor to form an external source resistor.

[0147] The circuit schematic of the constant current module in the above typical implementation scheme can be found in [reference needed]. Figure 15 These implementation schemes, through the monolithic integration of the HMET with the external source resistor, enable a smaller overall size and lower power consumption for the constant current module. Figure 15 In the diagram, 121 and 122 represent the built-in source resistor and external source resistor of the HEMT, respectively.

[0148] For example, please refer to Figure 16 In a typical embodiment, the constant current module 400 of this invention can also utilize the built-in source resistor of the HEMT as the source feedback resistor. The constant current module 400 can be a chip, which includes a channel layer 402 and a barrier layer 403 sequentially grown on a substrate 401. The channel layer 402 and the barrier layer 403 form a heterojunction, in which a two-dimensional electron gas 404 (2DEG) is distributed. By setting the source 405, gate 406, and drain 407 of the HEMT on the semiconductor layer, an HEMT device structure can be formed. The source 405 and drain 407 can form ohmic contacts with the semiconductor layer, respectively. The gate 406 can be electrically connected to the negative electrode of the chip via a side lead 408. At the same time, a thickened electrode and a source field plate 409 can be set above the gate 406. The thickened electrode and the source field plate 409 are partially electrically contacted with the source 405 and electrically connected to the negative electrode of the chip via wires. The drain 407 is electrically connected to the positive terminal of the chip. Multiple electrical isolation regions 410 can also be formed in this semiconductor layer to achieve mesa isolation for the HEMT. These electrical isolation regions can extend from the surface of the barrier layer to the interior of the channel layer, or from the surface of the barrier layer to the substrate surface. They can be high-resistivity regions formed by ion implantation of the semiconductor layer, or grooves formed by etching the semiconductor layer. The resistance value of the built-in source resistor of the HEMT mainly depends on the two-dimensional electron gas in the gate-source region and the source ohmic contact resistance, such as... Figure 15 As shown in the dashed box c. In this chip, one or more insulating dielectric layers 411 may be disposed on the surface of the semiconductor layer to isolate the aforementioned electrodes from each other and to passivate the semiconductor layer surface. These one or more insulating dielectric layers may be continuous layers, and the aforementioned electrodes may be exposed through corresponding windows formed in these continuous insulating dielectric layers. Furthermore, a gate field plate structure that cooperates with the gate may also be provided in this chip. A circuit schematic of this typical embodiment can be found in [reference needed]. Figure 17 This simplifies the structure of the constant current module, facilitating the achievement of maximum output current. Figure 17 The 121 in the text represents the built-in source resistor of the HEMT.

[0149] For example, please refer to Figure 18-19 In a typical embodiment, in the constant current module 500 of this invention, the HEMT 11 is disposed within a chip, and an external source resistor 122' is connected in series with the chip but disposed separately. The chip includes a channel layer 502 and a barrier layer 503 sequentially grown on a substrate 501, forming a heterojunction in which a two-dimensional electron gas 504 (2DEG) is distributed. An HEMT device structure can be formed by disposed of the source 505, gate 506, and drain 507 on the semiconductor layer. The source 505 and drain 507 can form ohmic contacts with the semiconductor layer, respectively. The gate 506 can be led out via a side lead 508 and electrically connected to the negative terminal of the constant current module. Simultaneously, a thickened electrode and a source field plate 509 can be disposed above the gate 506. The thickened electrode and source field plate 509 are partially electrically contacted with the source 505, and then connected in series with an external source resistor before being electrically connected to the negative terminal of the constant current module. The drain 507 is electrically connected to the positive terminal of the constant current module. Multiple electrical isolation regions 510 can also be formed in the semiconductor layer to achieve mesa isolation for the HEMT. These electrical isolation regions can extend from the surface of the barrier layer to the interior of the channel layer, or from the surface of the barrier layer to the substrate surface. They can be high-resistivity regions formed by ion implantation of the semiconductor layer, or grooves formed by etching the semiconductor layer. The resistance value of the built-in source resistor of the HEMT mainly depends on the two-dimensional electron gas in the gate-source region and the ohmic contact resistance of the source, such as... Figure 19 As shown in the dashed box d, one or more insulating dielectric layers 511 can be disposed on the surface of the semiconductor layer in this chip to isolate the aforementioned electrodes from each other and achieve passivation of the semiconductor layer surface. These one or more insulating dielectric layers can be continuous layers, and the aforementioned electrodes can be exposed through corresponding windows opened in these continuous insulating dielectric layers. Furthermore, a gate field plate structure that cooperates with the gate can also be provided in this chip. This typical implementation allows the operating performance of the constant current module, especially its constant current value, to be flexibly adjusted by changing the external source resistor. For example, the external source resistor can be placed inside the package bracket or on the PCB board, connected in series with the source of the HEMT, and then connected to its gate to form the negative electrode of the constant current module. By changing the resistance value R of the external source resistor… S The magnitude of the output current value is adjusted by increasing R. S This can reduce the output current and decrease R. S It can increase the output current.

[0150] In addition, compared to constant current modules that only use built-in source resistors as source feedback resistors, constant current modules with external source resistors can have a smaller chip area, and the constant current value of the constant current module is easier to control.

[0151] In the above typical embodiments, the substrate material can be SiC, Si, sapphire, GaN, AlN, or diamond, etc.; the channel layer material can be GaN, InGaN, AlGaN, or AlInGaN, etc.; and the barrier layer material can be AlGaN, InAlN, AlN, AlScN, or AlInGaN, etc. The HEMT can be a depletion-mode device, and its gate can form a Schottky contact with the semiconductor layer, or a gate dielectric layer can be disposed between the gate and the semiconductor layer, i.e., forming a Schottky gate contact or a MIS gate structure. Furthermore, the HEMT can also employ a grooved gate structure or a p-type gate structure, etc.

[0152] In the above typical implementation scheme, the structure of the transistor can be changed accordingly to cope with different working scenarios. For example, it can have only conventional source, drain and gate without adding field plates; it can only add gate field plate; it can add two field plates, such as gate field plate and source field plate; it can add three or even more field plates.

[0153] Some embodiments of this utility model provide a circuit structure including the constant current module and at least one load module, wherein the constant current module and the load module are connected in series. For example, the load module is connected in series with the drain of a high electron mobility field-effect transistor within the constant current module. The load module may be a light-emitting module or other electrical functional module.

[0154] For example, please refer to Figure 20-21 , can be used Figure 15-18 The constant current module shown is used to construct a lighting circuit. Specifically, multiple LED beads 13' and the constant current module can be connected in series between the positive and negative terminals of the power supply. The power supply voltage is greater than the sum of the total turn-on voltage of the LED bead string and the saturation voltage of the constant current module, and the current of the LED beads is consistent with the output current of the constant current module. The power supply can be a DC power supply or an AC power supply. When using an AC power supply, the working circuit formed by the constant current module and LED beads connected in series can be connected in series with a rectifier bridge before being electrically connected to the power supply.

[0155] Some embodiments of this utility model also provide a constant current output control method, which includes: connecting the constant current module and the load module in series to a DC power supply, and connecting the drain of the high electron mobility field-effect transistor to the positive terminal of the DC power supply, the gate to the negative terminal of the DC power supply or ground, and the source to the negative terminal of the DC power supply or ground via a source feedback resistor, thereby controlling the current intensity of the constant current flowing through the load module.

[0156] In some embodiments, the constant current output control method may further include adjusting the current intensity of the constant current flowing through the load module by adjusting the value of the source feedback resistor in the constant current module. This method is particularly suitable for cases where the HEMT and the external source resistor in the constant current module are discrete components. In this case, the external source resistor is easier to replace, allowing the constant current module to provide constant currents with different current intensities, thereby meeting the needs of different application scenarios.

[0157] The technical solution of this utility model will be further described in detail below with reference to several embodiments. However, the implementation of this utility model is not limited to these specific details, and it can also be implemented in other ways different from those described herein. Therefore, the specific embodiments presented in this utility model are only examples and not limitations.

[0158] Example 1 This example provides a method for fabricating a GaN-based constant current module (hereinafter referred to as constant current IC), which includes the following steps:

[0159] S1. A semiconductor epitaxial layer is formed by sequentially growing an Fe-GaN buffer layer with a thickness of approximately 200 nm, an unintentionally doped GaN layer with a thickness of approximately 300 nm, a GaN channel layer with a thickness of approximately 80 nm, an AlN space layer with a thickness of approximately 0.7 nm, an AlGaN barrier layer with a thickness of approximately 26 nm, and a GaN capping layer with a thickness of approximately 3 nm on a silicon carbide substrate using MOCVD process.

[0160] S2. Active region isolation is performed on the semiconductor epitaxial layer by means of ICP etching process, etc., with an etching depth greater than 80nm.

[0161] S3. Silicon nitride with a thickness of about 5nm-50nm and silicon nitride with a thickness of about 150nm-300nm are grown on the semiconductor epitaxial layer using LPCVD and PECVD processes, respectively, to serve as the dielectric layer of the gate field plate of HEMT (hereinafter referred to as transistor).

[0162] S4. Windows are opened on the dielectric layer using photolithography and AOE dry etching processes to expose the source and drain regions of the transistor and the positive and negative electrode regions of the external source resistor. Ohmic metals Ti / Al / Ni / Au (approximately 22 / 240 / 55 / 65nm thick) are deposited on these exposed areas. Then, the layers are annealed at approximately 870℃ for 35s to form ohmic contacts between the source and drain of the transistor and the positive and negative electrodes of the external source resistor and the semiconductor epitaxial layer.

[0163] S5. The gate trench pattern is fabricated on the dielectric layer by photolithography and AOE dry etching processes. Then, the gate field plate pattern is fabricated by photolithography and other processes. The gate field plate metal Ni / Au / Ti (thickness of about 50 / 200 / 20nm) is then deposited by evaporation. The connection between the external source resistor and the transistor is completed at the same time as the gate is formed.

[0164] S6. The source field plate dielectric layer is fabricated using PECVD technology, which can be a silicon nitride layer with a thickness of 100nm-300nm. Then, the wires between the source field plate patterned transistors and resistors are processed on the source field plate dielectric layer using photolithography and AOE dry etching processes. After that, the gate field plate metal Ti / Au (thickness of about 30 / 250nm) is deposited to complete the fabrication of the source field plate.

[0165] S7. A passivation layer is fabricated using PECVD technology. This layer can be a silicon nitride layer with a thickness of approximately 100nm-300nm. Then, openings are etched on the passivation layer using photolithography and AOE dry etching processes to expose the drain and gate PAD.

[0166] S8. Thin the substrate by using a thinning machine to thin the silicon carbide substrate to 150 micrometers, and then use a grinding machine to grind the substrate to 80-200 micrometers.

[0167] S9. Perform laser slicing on the thinned sample and then wire bond encapsulate it.

[0168] In this embodiment, a GaN-based constant current IC sample (referred to as sample A) was finally prepared with a constant current value of 6mA.

[0169] The size of the GaN HEMT in sample A is: L g =3um, Lgs=3um, Lgd=20um, W g =150um, R IS =15Ω, R ES =420Ω, R S =436Ω, R D =23Ω, Vknee=3V, Electrical parameters: V GS =0V, V TH = -3.38V, Physical parameter: μ n =1300, ε * =9.15, ε o =8.85E-14, d=2.45E-6, Rsh=325, Rc=1.

[0170] The GaN HEMT in sample A was tested using a B1505A power device analyzer. The static bias was set to source ground, drain connected to 10V, and a voltage of -6V to 1V was applied to the gate. The test interval was 0.01V. The device was scanned, and the relationship between the source-drain current and the gate-source voltage was measured. The test system stage had a heating function; after heating, the system was allowed to stabilize for 5 minutes after reaching the set temperature before testing.

[0171] Figure 23 The transfer characteristics of GaN HEMT in sample A are shown in the range of 25℃ to 250℃. It can be seen that this GaNHEMT exhibits good temperature characteristics under high-temperature conditions; the calculated temperature coefficient is -0.31% / ℃ within the temperature range of 25℃ to 250℃.

[0172] Sample A was tested using a B1505A power device analyzer. Specifically, the negative terminal of sample A was grounded, and a pulse was applied to the positive terminal. The test range was 0-200V, with an interval of 0.5V, a pulse width of 500µs, and a period of 5ms, in order to eliminate the thermal effect of the constant current module.

[0173] The constant current characteristics of sample A are as follows: Figure 24 As shown in the figure, it can be seen that in the pulse test from 0 to 200V, sample A exhibits good constant current characteristics in both linear and logarithmic coordinates.

[0174] In particular, sample A still exhibits good constant current characteristics under extremely high voltage excitation. For example, Figure 25 The diagram shows the operation of sample A under a 1.5kV pulse voltage, demonstrating that it still exhibits excellent constant current characteristics.

[0175] Comparative Example 1: The GaN-based constant current IC (referred to as Sample B) and its preparation method provided in this comparative example are basically the same as those of Sample A in Example 1, except that no external source resistor is set.

[0176] The properties of sample B were tested according to the method in Example 1. (See also...) Figure 26 As can be seen, compared to sample B without an external source resistor (corresponding to no R...), ES (Curve), Sample A had an external source resistor added (corresponding to no R) ES (The curve) shows a significant decrease in voltage at its knee point.

[0177] Figure 27 The results of DC test on sample A at 25°C and pulse test results at different temperatures of 25, 30, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160 and 170°C are shown.

[0178] Please see again Figure 28 The results show the DC test results of sample B at 30°C and the pulse test results at different temperatures of 30, 40, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, and 170°C. These test results reflect the junction temperature of sample B at different heat dissipation rates.

[0179] Will Figure 27 and Figure 28 By comparing the data, it is clear that the constant current module has a lower junction temperature after adding an external source resistor.

[0180] Figure 29 The relationship between transconductance and gate-source voltage for samples A and B is shown. It can be seen that after adding an external source resistor, the constant current module has lower transconductance and higher stability.

[0181] Example 2 This example provides a GaN-based constant current module (hereinafter referred to as constant current IC) including a HEMT and an external source resistor. The HEMT is packaged in a chip, and the chip and the external source resistor are separately disposed and electrically connected by leads, forming a configuration as shown below. Figure 18 The circuit structure shown is shown.

[0182] The structure of this HEMT can be referenced. Figure 30 It includes: a substrate 601, an epitaxial layer consisting of a channel layer 602 and a barrier layer 603 sequentially grown on the substrate, an insulating dielectric layer 604 deposited on the epitaxial layer, a source electrode 605 and a drain electrode 606 forming ohmic contacts with the epitaxial layer, and a gate electrode 607 connected to the epitaxial layer. The gate electrode 607 can be a T-type gate or similar. In this HEMT, an electrical isolation region 608 can be formed using ion implantation, etching, or other methods to achieve mesa isolation.

[0183] The method for preparing HEMT in this embodiment may include the following steps:

[0184] S1. Referring to step S1 of Example 1, a semiconductor epitaxial layer is grown on a silicon carbide substrate using the MOCVD process.

[0185] S2. Active region isolation is performed on the semiconductor epitaxial layer by means of ICP etching process, etc., with an etching depth greater than 80nm.

[0186] S3. Silicon nitride with a thickness of about 5nm-50nm and silicon nitride with a thickness of about 150nm-300nm are grown on the semiconductor epitaxial layer using LPCVD and PECVD processes, respectively, to serve as the dielectric layer of the gate field plate of HEMT (hereinafter referred to as transistor).

[0187] S4. Windows are opened on the dielectric layer using photolithography and AOE dry etching processes to expose the source and drain regions of the transistor. Ohmic metals Ti / Al / Ni / Au (approximately 22 / 240 / 55 / 65nm thick) are deposited on these exposed regions. Then, the transistors are annealed at approximately 870℃ for 35s to form ohmic contacts between the source and drain regions and the semiconductor epitaxial layer.

[0188] S5. The gate trench pattern is fabricated on the dielectric layer by photolithography and AOE dry etching processes, and then gate metal Ni / Au / Ti (thickness approximately 50 / 200 / 20nm) is deposited by vapor deposition.

[0189] S6~S8: Basically the same as steps S7~S9 in Example 1.

[0190] A chip prepared using the method described in this embodiment is electrically connected to external source resistors with different resistance values ​​to form a chip having Figure 18 The constant current IC with the circuit structure shown has the following output characteristics as a function of the external source resistor: Figure 31 As shown.

[0191] Clearly, the solution in this embodiment allows for more flexible control of the constant current value of the GaN-based constant current IC.

[0192] Example 3: The GaN-based constant current module (hereinafter referred to as constant current IC) provided in this example is basically the same as that in Example 2, except that: (See...) Figure 32 The HEMT has a field-free gate structure 607'. This HEMT can be fabricated using essentially the same method as in Example 2.

[0193] The above embodiments are merely intended to illustrate the technical concept and effects of this utility model, so that those skilled in the art can understand the content of this utility model and implement it accordingly. However, these embodiments do not constitute a limitation on the scope of protection of this utility model. Any equivalent changes or modifications made based on the spirit and technical concept of this utility model should be covered by the claims of this utility model.

Claims

1. A constant current module, characterized in that, The transistor includes a high electron mobility field-effect transistor based on a III-V compound and a source feedback resistor. The source of the transistor is connected in series with the source feedback resistor. The source feedback resistor includes either the transistor's built-in source resistor or the transistor's built-in source resistor and an external source resistor connected in series with the transistor's source. The source of the transistor is used to connect to the negative terminal of a power supply or to ground through the source feedback resistor. The gate of the transistor is used to connect to the negative terminal of a power supply or to ground. The drain of the transistor is used to connect to the positive terminal of a power supply. The constant current module includes a semiconductor layer, which includes a channel layer and a barrier layer disposed on the channel layer. The source, drain, and gate are disposed on a designated area of ​​the semiconductor layer and electrically combined with the channel layer and the barrier layer in the designated area to form the transistor. The external source resistor is integrated with the transistor in a chip, and the chip includes the semiconductor layer; Alternatively, the semiconductor layer is disposed within a chip, and the chip is disposed separately from the external source resistor.

2. The constant current module according to claim 1, characterized in that: The semiconductor layer has a first region and a second region, which are distributed along a direction parallel to the surface of the semiconductor layer. The first region is the designated region. At least a portion of the semiconductor material in the second region is electrically bonded to the positive and negative electrodes to form the external source resistor. Alternatively, the external source resistor includes a resistive material layer disposed on the second region, which is electrically connected to the source of the transistor and the negative electrode of the power supply, respectively.

3. The constant current module according to claim 2, characterized in that: The external source resistor includes a two-dimensional electron gas distributed in the second region, or the external source resistor includes a semiconductor resistor layer formed by transforming at least a portion of the barrier layer and / or channel layer in the second region, wherein the resistance of the semiconductor resistor layer is greater than the resistance of the barrier layer and / or channel layer; and, within the semiconductor layer, the transistor and the external source resistor are electrically isolated from each other.

4. The constant current module according to claim 2, characterized in that: The resistive material layer includes a metal thin film and / or a metal compound thin film coated on the second region.

5. The constant current module according to claim 1, characterized in that: The external source resistor includes one or more combinations of heterojunction 2DEG resistors, n-GaN resistors, p-GaN resistors, silicon resistors, metal thin film resistors, and metal compound thin film resistors.

6. The constant current module according to claim 1, characterized in that: An electrical isolation structure is provided within the semiconductor layer, which includes an ion implantation isolation structure or a mesa etching isolation structure.

7. The constant current module according to claim 1, characterized in that: An insulating dielectric layer is also disposed on the semiconductor layer.

8. The constant current module according to claim 1, characterized in that: The transistor includes a GaN-based HEMT.

9. The constant current module according to claim 1, characterized in that: The transistor is a depletion-type HEMT.

10. The constant current module according to claim 1, characterized in that: The transistor has a Schottky gate contact structure or a MIS gate structure.

11. The constant current module according to claim 1, characterized in that: The transistor is a fieldless structure, or the transistor has one or more field plates.

12. The constant current module according to claim 1, characterized in that: The resistance value R of the source feedback resistor S Satisfy equations I to II; Equation I is: Equation II is: Among them, V knee μ is the initial saturation voltage of the constant current module. n ε is the gate electron mobility of the transistor. * ε o These are the relative permittivity and the vacuum permittivity, respectively; d is the barrier layer thickness of the transistor; and W... g L is the gate width of the transistor. g R is the gate length of the transistor. D V is the parasitic drain resistance at the drain terminal of the transistor. GS V is the gate-source voltage of the transistor. TH L is the threshold voltage of the transistor. gd R is the gate-drain distance of the transistor. sh(2DEG) R is the sheet resistance of the two-dimensional electron gas in the transistor. C(2DEG) The contact resistivity between the source or drain ohmic metal of the transistor and the two-dimensional electron gas.

13. The constant current module according to claim 12, characterized in that: If the resistance values ​​of the built-in source resistor and the external source resistor are defined as R... IS 、R ES Then R S =R IS +R ES ; And, when R ES When = 0, R IS Satisfy Equations III-IV; Equation III is: Equation IV is: Among them, L gs I is the gate-source distance of the transistor. DS(sat) The saturation current intensity of the transistor; When R ES / R IS When >5, define R S =R ES And R ES Satisfying the V-type and VI-type; Equation V is: Formula VI is: Among them, L ES W is the distance between the two ohmic access regions in the external source resistor. ES R is the width of the external source resistor. sh(RES) R is the sheet resistance of the external source resistor. C(RES) To match the contact resistivity between the ohmic metal in the ohmic access area and the external source resistor.

14. A circuit structure, characterized in that, It includes a constant current module and a load module as described in any one of claims 1-13, wherein the load module and the constant current module are connected in series.

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