Ethernet test system for central controller
By connecting Ethernet ports in series into a test link in the central controller, the problem of low Ethernet port testing efficiency is solved, achieving resource-saving and cost-reducing testing results.
Patent Information
- Application Number
- CN202423018019.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-12-06
AI Technical Summary
In existing technologies, the Ethernet port testing of the central controller is inefficient and resource-intensive, requiring separate connection to a host computer for testing.
The Ethernet ports in the central controller are interconnected to form a test link, and tests are performed on a per-link basis to reduce test resource consumption and program quantity.
It improves Ethernet testing efficiency and reduces testing costs and resource requirements.
Smart Images
Figure CN223502882U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of testing technology, and more particularly to an Ethernet testing system for a central controller. Background Technology
[0002] As electronic and electrical architectures evolve towards centralized computing architectures, the central controller (Core SuperComputer, CSC) in vehicles integrates more and more functions, such as intelligent driving control, cockpit control, and vehicle control. This has led to a more complex internal structure design for the central controller and the need to set up a large number of Ethernet ports to implement various functions.
[0003] In order to test each Ethernet port in the central controller, the relevant technology requires connecting each Ethernet port to a host computer and running the corresponding test program, which is a low-efficiency testing method. Utility Model Content
[0004] To overcome the problems existing in related technologies, this disclosure provides an Ethernet testing system for a central controller.
[0005] According to a first aspect of the present disclosure, an Ethernet testing system for a central controller is provided, comprising: an electronic control unit and a host computer;
[0006] The electronic control unit includes at least one printed circuit board (PCB), and each PCB includes multiple Ethernet ports and at least one controller;
[0007] Each controller in the electronic control unit is connected to the host computer through at least a portion of the Ethernet ports in the electronic control unit to form a test link corresponding to each controller.
[0008] Each Ethernet port is located in at least one test link, and Ethernet ports in the same test link are connected in series.
[0009] In some embodiments, when the electronic control unit comprises multiple PCBs, the multiple PCBs include a main PCB and at least one secondary PCB, and each secondary PCB has at least one Ethernet port connected to the main PCB.
[0010] In some embodiments, the controller in the secondary PCB is connected to the host computer via at least a portion of the Ethernet ports in the secondary PCB and at least a portion of the Ethernet ports in the primary PCB.
[0011] In some embodiments, when multiple Ethernet ports with the same transmission rate are included in the same sub-PCB, the Ethernet ports with the same transmission rate in the sub-PCB are connected in series and located in the same test link.
[0012] In some embodiments, in the same sub-PCB, Ethernet ports with the same transmission rate are connected in series, with one end connected to any Ethernet port in the sub-PCB that is connected to the main PCB, and the other end connected to the controller in the sub-PCB. The controllers connected to the Ethernet ports with different transmission rates are different.
[0013] In some embodiments, the host computer is connected to an Ethernet port on the main PCB.
[0014] In some embodiments, in the main PCB, the Ethernet port for connecting to the secondary PCB is connected in series with any Ethernet port connected to the host computer.
[0015] In some embodiments, for any two test links in an Ethernet test system, the Ethernet ports shared by the two test links are connected in series.
[0016] In some embodiments, the number of host computers is the same as the number of PCBs, and the controllers in different PCBs are connected to different host computers.
[0017] In some embodiments, the controller is a system-on-a-chip or a microcontroller unit.
[0018] The technical solutions provided in this disclosure may have the following beneficial effects:
[0019] The Ethernet testing system for a central controller provided in this disclosure includes an electronic control unit (ECU) and a host computer. The ECU includes at least one printed circuit board (PCB), each PCB containing multiple Ethernet ports and at least one controller. Each controller in the ECU is connected to the host computer via at least a portion of its Ethernet ports, forming a test link corresponding to each controller. Each Ethernet port is located in at least one test link, and Ethernet ports within the same test link are interconnected. The solution provided in this disclosure, by interconnecting Ethernet ports to construct a test link, allows Ethernet testing to be performed on a link-by-link basis during the testing process, improving Ethernet testing efficiency. Attached Figure Description
[0020] Figure 1 This diagram illustrates the structure of an Ethernet testing system for a central controller according to an embodiment of the present disclosure.
[0021] Figure 2 This illustration shows a schematic diagram of another central controller Ethernet test system according to an embodiment of the present disclosure.
[0022] Figure label:
[0023] 100 - Electronic control unit; 110 - PCB; 111 - Ethernet port; 112 - Controller; 200 - Host computer. Detailed Implementation
[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0025] Furthermore, the terms “first,” “second,” etc., used in this disclosure are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0026] The central controller (Core Super Computer, CSC) is the core control unit used to control and manage various systems, subsystems, and functional domain controllers within a vehicle. It can be implemented through an electronic control unit (ECU).
[0027] For example, the central controller can exchange data with other controllers via Ethernet to ensure the coordinated operation of various vehicle systems, thereby enabling control functions such as intelligent driving control, cockpit control, and vehicle control.
[0028] As the central controller integrates more and more functions, its internal structure design becomes more complex, and the number of Ethernet ports for data exchange is also increasing.
[0029] In order to test the Ethernet links in the central controller, the relevant technology requires that each Ethernet port in the central controller be connected to a host computer for testing and monitoring. This method greatly increases the workload of testing and requires a lot of testing resources.
[0030] In view of this, the solution provided in this disclosure embodiment can connect the Ethernet ports in the central controller in series to form a test link, and perform Ethernet testing on a unit basis during the testing process, thereby improving the Ethernet testing efficiency and reducing the occupation of test resources.
[0031] The exemplary embodiments of this disclosure will now be described in detail.
[0032] Figure 1 This diagram illustrates the structure of an Ethernet testing system for a central controller according to an embodiment of the present disclosure. Figure 1As shown, the Ethernet testing system includes an electronic control unit 100 and a host computer 200.
[0033] The electronic control unit 100 includes at least one printed circuit board (PCB 110), and each PCB 110 includes multiple Ethernet ports 111 and at least one controller 112.
[0034] Each controller 112 in the electronic control unit 100 is connected to the host computer 200 through at least a portion of the Ethernet ports 111 in the electronic control unit 100 to form a test link corresponding to each controller 112.
[0035] Each Ethernet port 111 is located in at least one test link, and the Ethernet ports 111 in the same test link are connected in series.
[0036] In some embodiments, the controller 112 in PCB 110 may be a system-on-chip (SOC) or a microcontroller unit (MCU). The host computer 200 may be a computer used to monitor the Ethernet test status.
[0037] In the Ethernet testing system provided in this embodiment, for a test link where the controller 112 is a SOC, an Ethernet test program (e.g., iperf) can be run on the SOC, and the test data fed back by the test program can be monitored by the host computer 200 to achieve the test of the test link.
[0038] For the test link where controller 112 is an MCU, since the MCU cannot execute Ethernet test programs, the host computer 200 can actively send a PING command to the MCU and obtain the data fed back by the MCU to test the test link.
[0039] Of course, for the test link where the controller 112 is a SOC, the test can also be performed by sending a PING command from the host computer 200 to the SOC. This embodiment of the present disclosure will not elaborate on this method.
[0040] In this embodiment of the disclosure, by connecting multiple Ethernet ports in series between the controller and the host computer to form a test link, the consumption of test resources can be reduced and the test efficiency can be improved. Specifically, when using the Ethernet test system in this embodiment of the disclosure for testing, testing can be performed on a per-test-link basis. Since the Ethernet ports in the same test link are interconnected and ultimately connected to the controller, if a test link is determined to be in a normal state through testing, it can be confirmed that all Ethernet ports contained in that test link are in a normal state. Furthermore, since each Ethernet port is located in at least one test link, testing the test link can cover all Ethernet ports in the electronic control unit.
[0041] Therefore, the Ethernet testing system provided in this disclosure simplifies the Ethernet testing process from testing each Ethernet port individually to testing each constructed test link individually. Since the number of test links is significantly lower than the number of Ethernet ports, the number of test programs that need to be configured and run is greatly reduced, significantly improving testing efficiency. Furthermore, the fewer test links also reduce the number of host computers required, thereby saving equipment resources and lowering testing costs.
[0042] Figure 2 This diagram illustrates the structure of another Ethernet test system for a central controller, as shown in an embodiment of this disclosure. Figure 1 The difference is that, Figure 2 The electronic control unit in the system consists of multiple PCBs.
[0043] Please refer to Figure 2 ,exist Figure 2 The Ethernet test system shown includes three PCBs: PCB1, PCB2, and PCB3.
[0044] PCB1 includes switch 1 and SOC1. P1, P2, ..., P8, and P9 in switch 1 are all Ethernet ports in PCB1, and SOC1 is the controller in PCB1.
[0045] PCB2 includes Switch 2, Switch 3, SOC2, and SOC3. P1, P2, ..., P15, P16 in Switch 2, and P1, P2, ..., P6, P9 in Switch 3 are all Ethernet ports on PCB2. SOC2 and SOC3 are the controllers on PCB2.
[0046] PCB3 includes Switch 4, SOC4, SOC5, and MCU4. P1, P2, ..., P7, P8 in Switch 4 are Ethernet ports in PCB3, and SOC4, SOC5, and MCU4 are controllers in PCB3.
[0047] In some embodiments, when the electronic control unit includes multiple PCBs, the multiple PCBs may include a main PCB and at least one secondary PCB, and each secondary PCB has at least one Ethernet port connected to the main PCB.
[0048] For example in Figure 2 In the diagram, PCB1 is the main PCB, and PCB2 and PCB3 are secondary PCBs. PCB2 is connected to Ethernet port P9 in PCB1 via Ethernet port P16, and PCB3 is connected to Ethernet port P8 in PCB1 via Ethernet port P8.
[0049] It is understandable that the terms "main PCB" and "sub-PCB" are used here only to indicate the connection relationship between the various PCBs, and not to indicate the importance of the PCBs. That is, in the electronic control unit, all sub-PCBs are connected to the same main PCB via Ethernet ports, but there is no difference in importance between the main PCB and sub-PCBs in terms of the functions they perform.
[0050] For example, consider an actual electronic control unit (ECU) in a vehicle. Functionally, the main PCB can act as a data receiving and forwarding center for the network. It can forward data entering the vehicle network to the corresponding secondary PCBs and forward data generated by the secondary PCBs to the appropriate devices. Different secondary PCBs can implement different control functions. For example, a secondary PCB can be used for data processing and decision-making related to intelligent driving, or for controlling the cockpit system in the vehicle.
[0051] Therefore, when the electronic control unit consists of multiple PCBs, it is necessary to ensure that the network between each network port and the controller within the same PCB is unobstructed, as well as the network between each sub-PCB and the main PCB.
[0052] For example, the controller in the secondary PCB can be connected to the host computer via at least a portion of the Ethernet ports in the secondary PCB and at least a portion of the Ethernet ports in the primary PCB. In other words, the construction of the test link in the secondary PCB also relies on at least a portion of the Ethernet ports in the primary PCB to test the network transmission status between the secondary and primary PCBs.
[0053] For example, the host computer is connected to the Ethernet port on the main PCB, thereby ensuring that the test data received by the host computer is data transmitted through the Ethernet port of the main PCB. For example, in Figure 2 In the process, host computer 1 is connected to Ethernet port P1 in PCB1 (i.e., main PCB), host computer 2 is connected to Ethernet port P2 in PCB1, and host computer 3 is connected to Ethernet port P5 in PCB1.
[0054] Accordingly, in the main PCB, the Ethernet port used to connect to the secondary PCB is interconnected with any Ethernet port connected to the host computer, enabling the host computer to test the network transmission status between the main PCB and the secondary PCB. For example, in Figure 2 In the diagram, Ethernet port P9 on PCB1 is connected to PCB2, and Ethernet port P1 is connected to host computer 1. Ethernet port P8 on PCB1 is connected to PCB3, and Ethernet port P5 is connected to host computer 3.
[0055] In some embodiments, when multiple Ethernet ports with the same transmission rate are included in the same sub-PCB, the Ethernet ports with the same transmission rate in the sub-PCB are connected in series and located in the same test link.
[0056] Furthermore, within the same PCB, Ethernet ports with the same transmission rate are connected in series, with one end connected to any Ethernet port on the main PCB that is connected to the main PCB, and the other end connected to the controller on the PCB. Moreover, Ethernet ports with different transmission rates are connected in series to different controllers.
[0057] For example in Figure 2 In the example, PCB2 contains both 100Mbps and 1Gbps Ethernet ports. The 100Mbps Ethernet ports on PCB2 can be interconnected to form 100Mbps Link 1. One end of Link 1 is connected to Ethernet port P16 on PCB2, which is used for connecting to PCB1, and the other end is connected to SOC3. Similarly, the 1Gbps Ethernet ports on PCB2 can be interconnected to form 1Gbps Link 1. One end of 1Gbps Link 1 is connected to Ethernet port P16 on PCB2, which is used for connecting to PCB1, and the other end is connected to SOC2.
[0058] In this embodiment of the disclosure, the test links corresponding to the Ethernet ports can be distinguished based on the transmission rate of the Ethernet ports, thereby enabling targeted monitoring of the network performance of Ethernet ports with different rates, so as to more effectively manage and optimize network performance.
[0059] Understandably, the main PCB may contain Ethernet ports that require establishing a connection between the host computer and the secondary PCB, for example... Figure 2 P1 and P5 in PCB1. Therefore, even if there are multiple Ethernet ports with different transmission rates in the main PCB, Ethernet ports with the same rate are not necessarily all connected in series.
[0060] In some embodiments, for any two test links in an Ethernet test system, the shared Ethernet ports between the two test links are sequentially connected in series. In other words, closed Ethernet loops should be avoided in interleaved test links to prevent network storms, thereby improving the stability of the test network.
[0061] In some embodiments, the number of host computers can be the same as the number of PCBs, with controllers on different PCBs connected to different host computers. This disclosure allows for the independent testing and management of Ethernet ports on different PCBs by setting up different host computers, thereby reducing the number of host computers required during Ethernet testing.
[0062] The above provides an exemplary description of the solution provided in this disclosure. The following will continue to combine... Figure 2 This document details the design concept of the Ethernet test system for the central controller in the embodiments of this disclosure.
[0063] exist Figure 2 Based on the connection relationship between PCB1 and PCB2 and PCB3, two gigabit Ethernet test links and two 100 Mbps Ethernet test links can be set up respectively.
[0064] The design of the Gigabit Ethernet test link is as follows:
[0065] ①Gigabit link 1 between PCB1 and PCB2:
[0066] Host computer 1 → Switch 1P1 → Switch 1P9 → Switch 2P16 → … → Switch 2P6 → Switch 2P9 → SOC2.
[0067] ②Gigabit link 2 between PCB1 and PCB3:
[0068] Host computer 3 → Switch 1P5 → Switch 1P8 → Switch 4P8 → … → Switch 4P7 → SOC4.
[0069] Meanwhile, in order to take into account the Ethernet path conditions of MCU3 and SOC5, the following two additional links are established: Switch 4P7 → Switch 4P5 → MCU4; Switch 4P8 → Switch 4P1 → SOC5.
[0070] The design of the 100 Mbps Ethernet test link is as follows:
[0071] ①100Mbps link 1 between PCB1 and PCB2:
[0072] Host computer 1 → Switch 1P1 → Switch P9 → Switch 2P16 → … → Switch 3P9 → SOC3.
[0073] ②100Mbps Link 2 in PCB1:
[0074] Host computer 2 → Switch 1P2 → Switch 1P3 → Switch 1P4 → Switch 1P7 → SOC1.
[0075] Please continue to refer to Figure 2 ,based on Figure 2 The Ethernet testing system shown can reduce the number of host computers to 3.
[0076] The host computer 1 is used to monitor the running status of iperf (Ethernet test program) on SOC2 in gigabit link 1, and to detect bandwidth and packet loss rate. At the same time, it periodically sends PING messages to 100 Mbps link 1 to detect the response status of SOC3, and thus determine the connectivity of this link.
[0077] The host computer 2 is used to monitor the operating status of iperf on SOC1 in the 100 Mbps link 2, and to detect bandwidth and packet loss rate.
[0078] The host computer 3 is used to monitor the operating status of iperf on SOC4 in Gigabit Link 2, and to detect bandwidth and packet loss rate. At the same time, in order to test the Ethernet path status of MCU4 and SOC5, it periodically sends PING messages to Gigabit Link 2 to detect the response status of MCU4 and SOC5, and thus determine the connectivity of this link.
[0079] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0080] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. An Ethernet testing system for a central controller, characterized in that, include: Electronic control unit and host computer; The electronic control unit includes at least one printed circuit board (PCB), and each PCB includes multiple Ethernet ports and at least one controller; Each controller in the electronic control unit is connected to the host computer through at least a portion of the Ethernet ports in the electronic control unit to form a test link corresponding to each controller. Each Ethernet port is located in at least one test link, and Ethernet ports in the same test link are connected in series.
2. The system according to claim 1, characterized in that, In the case where the electronic control unit includes multiple PCBs, the multiple PCBs include a main PCB and at least one auxiliary PCB, and each auxiliary PCB has at least one Ethernet port connected to the main PCB.
3. The system according to claim 2, characterized in that, The controller in the secondary PCB is connected to the host computer via at least a portion of the Ethernet ports in the secondary PCB and at least a portion of the Ethernet ports in the primary PCB.
4. The system according to claim 2, characterized in that, When multiple Ethernet ports with the same transmission rate are contained in the same PCB, the Ethernet ports with the same transmission rate in the PCB are connected in series and located in the same test link.
5. The system according to claim 4, characterized in that, In the same PCB, Ethernet ports with the same transmission rate are connected in series. One end of each port is connected to any Ethernet port in the sub-PCB that is connected to the main PCB, and the other end is connected to the controller in the sub-PCB. The controllers connected to the Ethernet ports with different transmission rates are different.
6. The system according to claim 2, characterized in that, The host computer is connected to the Ethernet port in the main PCB.
7. The system according to claim 6, characterized in that, In the main PCB, the Ethernet port used to connect to the secondary PCB is connected in series with any Ethernet port connected to the host computer.
8. The system according to claim 1, characterized in that, For any two test links in the Ethernet test system, the Ethernet ports shared by the two test links are connected in series.
9. The system according to claim 1, characterized in that, The number of host computers is the same as the number of PCBs, and the controllers in different PCBs are connected to different host computers.
10. The system according to claim 1, characterized in that, The controller is a system-on-a-chip or a microcontroller unit.