Integrated circuit device

Abstract

Devices having isolation metal structures are provided. An integrated circuit device includes: a semiconductor substrate; a first gate structure and a second gate structure over the semiconductor substrate and aligned in a straight line; and an isolation structure between and separating the first gate structure and the second gate structure, in which the isolation structure has a selected shape and includes an air gap having a selected size.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Utility Model Content

[0004] Some embodiments of this disclosure provide an integrated circuit device comprising: a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and includes an air gap having a selected size.

[0005] Some embodiments disclosed herein provide an integrated circuit device comprising: a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and is substantially free of air gaps.

[0006] Some embodiments of this disclosure provide an integrated circuit device comprising: a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has an air gap, wherein the isolation structure has a total depth, and wherein the air gap has a height of at least half of the total depth. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a flowchart illustrating a method according to some embodiments;

[0009] Figure 2 This is a flowchart illustrating a method according to some embodiments;

[0010] Figure 3 This is a flowchart illustrating a method according to some embodiments;

[0011] Figure 4 This is a flowchart illustrating a method according to some embodiments;

[0012] Figure 5 The figure shows a top view of a semiconductor device according to some embodiments;

[0013] Figures 6 to 13 Based on some embodiments Figure 1 and Figure 2 A cross-sectional view of the apparatus during the continuous manufacturing phase of the method;

[0014] Figure 14 It is by Figure 1 , Figure 2 ,or Figure 3 A perspective view of the apparatus formed by the method;

[0015] Figure 15 Based on some embodiments Figure 11 Manufacturing stage Figure 14 A Y-shaped cross-sectional view of the device taken along the gate structure;

[0016] Figure 16 Based on some embodiments Figure 11 Manufacturing stage Figure 14 A Y-shaped cross-sectional view of the device taken along the interlayer dielectric material (between the gate lines);

[0017] Figure 17 Based on some embodiments Figure 11 Manufacturing stage Figure 14 An X-shaped cross-sectional view of the device taken along the groove;

[0018] Figures 18 to 25 Based on some embodiments Figure 1 and Figure 2 A perspective view of the apparatus during the continuous manufacturing phase of the method;

[0019] Figure 26 It includes Figure 25 Perspective views of the device at the manufacturing stage, including a Y-shaped cross-sectional view (through the source / drain region) and an X-shaped cross-sectional view;

[0020] Figure 27 It includes Figure 25Perspective views of the device at the manufacturing stage, including a Y-shaped cross-sectional view (through the gate structure) and an X-shaped cross-sectional view;

[0021] Figures 28 to 30 It is based on some embodiments (such as in Figure 13 Y-shaped cross-sectional view of an alternative embodiment of the isolation structure at the manufacturing stage.

[0022] [Symbol Explanation]

[0023] 10: Method

[0024] 20: Method

[0025] 30: Method

[0026] 40: Method

[0027] 100: Device

[0028] 103: Multi-layer structure

[0029] 105: Fins / Structure

[0030] 107: Gate electrode

[0031] 109: Isolation Structure / Structure

[0032] 111: Gate line / line

[0033] 200: Part

[0034] 201:Substrate

[0035] 203: Multi-layer stacking

[0036] 205: First Floor

[0037] 207: Second Floor

[0038] 209: Quarantine Zone

[0039] 211: Dummy gate dielectric

[0040] 301: Dummy Gate Stack

[0041] 303: Dummy gate electrode

[0042] 305: First Hard Mask

[0043] 307: Second Hard Mask

[0044] 503: Source / Drain Region

[0045] 701: Nanostructures / Nanosheets

[0046] 703: Gate Dielectric

[0047] 801: Gate Cap

[0048] 803: Masking layer / mask

[0049] 804: Arrow

[0050] 860: Photoresist

[0051] 861: Bottom layer

[0052] 862: Intermediate Layer

[0053] 863: Top Layer

[0054] 870: Opening

[0055] 901: Trench

[0056] 902: Sidewall

[0057] 903: Bottom of the trench

[0058] 904: Groove opening / groove mouth

[0059] 906: Middle maximum value

[0060] 907: Minimum value

[0061] 920: Seam

[0062] 930: Bottleneck position

[0063] 953: ILD Structure

[0064] 980: Small air gap / air gap

[0065] 981: Top of the air gap

[0066] 982: Bottom of the air gap

[0067] 990: Full air gap / Large air gap / Air gap

[0068] 991: Top of the air gap

[0069] 992: Bottom of the air gap

[0070] 1117: District

[0071] 9021: Sidewall

[0072] 9022: Sidewall

[0073] S11~S16: Operation

[0074] S21~S29: Operation

[0075] S31~S39: Operation

[0076] S41~S44: Operation

[0077] W: Lateral width Detailed Implementation

[0078] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0079] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “on top,” “upper,” “top,” “below,” “lying,” “under,” “below,” “lower,” “bottom,” “side,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0080] In some embodiments herein, "material structure" refers to a structure comprising at least 50 wt.% of the identified material, for example, at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material; and a structure formed from the "material" comprises at least 50 wt.% of the identified material, for example, at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material. For example, in some embodiments, the tungsten structure and the structure formed from tungsten are each a structure comprising at least 50 wt%, at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 99 wt% of tungsten.

[0081] For simplicity, this document may not describe in detail typical technologies associated with semiconductor device manufacturing. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. In particular, the various processes in semiconductor device manufacturing are well-known; therefore, for simplicity, many typical processes will be mentioned only briefly or omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon fully reading this disclosure, the structures disclosed herein can be used with a variety of technologies and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the figures may represent multiple components.

[0082] This document describes embodiments of semiconductor devices and methods for manufacturing such devices. The methods described herein can be readily integrated into current process flows. For example, the methods described herein can be integrated into complementary metal-oxide-semiconductor (CMOS) manufacturing processes, including fin FET, nanowire, and nanosheet device processes. A versatile insulator formation method is provided, depending on the desired process or device conditions. Furthermore, the methods described herein relate to isolation structures, such as the formation of “diced polysilicon” isolation structures or “diced metal” isolation structures that split gate lines, such as dummy gate lines or metal gate lines, in two during manufacturing. After manufacturing, the isolation structures separate the metal gate structures from each other.

[0083] In some embodiments herein, a final isolation processing method (i.e., after the metal gate is formed) is performed. Specifically, a dummy gate line is formed and then removed to define a gate cavity. The metal gate line is formed in the gate cavity before being etched or cut to form a "cut-metal" trench. An isolation structure is then formed in the trench. In such embodiments, the isolation structure may be referred to as a cut-metal isolation structure.

[0084] In some embodiments herein, an isolation-first (i.e., prior to metal gate formation) processing method is performed. Specifically, dummy gate lines are formed. Next, the dummy gate lines are etched or diced to form “diced dummy” or “diced polysilicon” trenches. An isolation structure is then formed in the trenches. Next, the remaining portion of the dummy gate lines is removed to define gate cavities. Metal gate lines are then formed in the gate cavities. Specifically, a metal gate structure may be formed in each gate cavity. In such embodiments, the isolation structure may be referred to as a diced polysilicon or diced dummy isolation structure.

[0085] The embodiments described herein are provided for forming isolation structures with desired device performance and / or desired process yield conditions.

[0086] Processing yield is affected when isolation gap defects cause drain-to-gate short circuits. Specifically, isolation can be formed using undesirable gaps, such as those formed when deposited isolation material coalesces over cavities. These gaps can be exposed during etching and then filled with metal during gate formation. If the gaps are too large, the filling metal can cause short circuits. The method described herein avoids such short circuits and improves process yield by reducing or eliminating gaps in the isolation structure. More specifically, the method described herein can form trenches with a shape that consistently improves the ability to deposit isolation material in the absence of gaps or voids. Additionally, the method may include selecting the structure of the isolation structure, i.e., the shape of the isolation structure, to provide the desired improved process yield. Generally, it has been found that improved device yield and a wider process window are achieved when gaps in the isolation structure are reduced or eliminated.

[0087] Device performance may include low effective capacitance (C) eff Low effective capacitance can be improved by using an isolation structure with full / large voids or cavitation. The method of this paper achieves low effective capacitance by forming an isolation structure with full / large voids or air gaps. More specifically, the method of this paper forms trenches with a shape that consistently increases the size of voids or air gaps while depositing isolation material to form the isolation structure.

[0088] Furthermore, the method described herein can achieve a balance between improved device yield and low effective capacitance by forming an isolation structure with small voids or air gaps. More specifically, the method described herein can form trenches with a shape that provides a consistent formation of an isolation structure with relatively small voids or air gaps.

[0089] In addition, in embodiments where an air gap is formed in the isolation structure, the position of the air gap can be fine-tuned by modifying the shape of the trench forming the isolation structure. For example, a selected depth of the air gap can be identified, and the trench can be etched into a shape such that when the trench is filled with isolation material, an air gap is formed at the selected depth.

[0090] In some embodiments, the isolation structure may be a single-layer membrane or a multi-layer membrane. For multi-layer membranes, the isolation structure may be formed of one material or different materials. Using multi-layer membranes combined with air gaps of selected sizes to form the isolation structure can provide the conditions for achieving specific device requirements.

[0091] The embodiments disclosed herein offer advantages over the prior art. Although it is understood that other embodiments may offer different advantages, not all advantages need to be discussed herein, and no particular advantage needs to be used in all embodiments.

[0092] Now for reference Figure 1 The illustration shows method 10. Figure 1In method 10, a structure is formed over a substrate at operation S11. The structure may include a fin structure formed from a portion of the substrate and layers covering the substrate, such as during the formation of the fin structure to process a gate-all-around (GAA) device.

[0093] At operation S12, method 10 includes forming a gate line over the structure. In some embodiments, the gate line may be formed of a sacrificial material (such as polysilicon) to be removed during a later processing. In some embodiments, the gate line may be formed of a non-sacrificial material, such as a metal used to form a metal gate structure.

[0094] At operation S13, method 10 includes patterning a mask above the gate line. Specifically, the mask may be patterned to form one or more openings directly above, i.e., vertically above, the portion of the gate line to be removed.

[0095] At operation S14, method 10 includes etching through the gate line to form a trench. For example, an etching process can be performed to remove one or more portions of the gate line located directly beneath one or more openings in a mask. Each opening completely separates the gate line into two adjacent gate line portions. In other words, no remaining portion of the gate line extends between the adjacent gate line portions. Furthermore, the etching process can continue beneath the gate line, such as etching into an underlying shallow trench isolation (STI) feature or etching into the underlying semiconductor substrate.

[0096] At operation S15, method 10 includes forming a cut isolation structure in the trench. For example, method 10 may deposit a single layer of isolation material, multiple layers of isolation material, or multiple layers of at least two types of isolation material. In embodiments, each layer of the isolation material is conformally deposited. In some embodiments, the isolation material merges at a selected height to enclose cavitation within the isolation structure. In other embodiments, merging of the isolation material at the upper height is avoided to prevent cavitation formation.

[0097] Method 10 may include further processing at operation S16 to complete the fabrication of a semiconductor device or integrated circuit. For example, according to some embodiments, the further processing may include forming an interlayer dielectric and a metallization layer, forming source / drain contacts to the source / drain regions, and forming source / drain vias and gate vias.

[0098] It should be understood that method 10 includes steps characteristic of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore is only briefly described herein. Additionally, extra steps may be performed before, after, and / or during method 10.

[0099] Now for reference Figure 2 The illustration shows method 20. Method 20 includes forming a structure over a substrate at operation S21. The structure may include a fin structure formed from a portion of the substrate and layers covering the substrate, such as during the formation of the fin structure to process a gate-all-around (GAA) device.

[0100] At operation S22, method 20 includes forming a dummy gate line over the structure. Specifically, the dummy gate line is formed from a sacrificial material (such as polysilicon) to be removed during a later processing.

[0101] At operation S23, method 20 includes forming an interlayer dielectric material adjacent to the dummy gate line.

[0102] At operation S24, method 20 includes removing the dummy gate line to form a gate cavity. Specifically, the gate cavity is located between and bounded by interlayer dielectric materials.

[0103] At operation S25, method 20 includes forming a metal gate line in the gate cavity. For example, a parallel metal gate line may be formed in a parallel gate cavity.

[0104] At operation S26, method 20 includes patterning a mask above the metal gate line. Specifically, the mask may be patterned to form one or more openings directly above, i.e., vertically above, the portion of the metal gate line to be removed.

[0105] At operation S27, method 20 includes etching through the metal gate line to form a trench. For example, an etching process can be performed to remove one or more portions of the metal gate line directly beneath one or more openings in a mask. Each opening completely separates the metal gate line into two adjacent metal gate line portions or metal gate structures. In other words, no remaining portion of the metal gate line extends between adjacent metal gate line portions or metal gate structures. Furthermore, the etching process can continue beneath the metal gate line, such as etching into an underlying shallow trench isolation (STI) feature or etching into an underlying semiconductor substrate.

[0106] At operation S28, method 20 includes forming a cut metal isolation structure in the trench. For example, method 10 may deposit a single layer of isolation material, multiple layers of isolation material, or multiple layers of at least two types of isolation material. In embodiments, each layer of the isolation material is conformally deposited. In some embodiments, the isolation material merges at a selected height to enclose cavitation within the isolation structure. In other embodiments, merging of the isolation material at the upper height is avoided to prevent cavitation formation.

[0107] Method 20 may include further processing at operation S29 to complete the fabrication of a semiconductor device or integrated circuit. For example, according to some embodiments, the further processing may include forming an interlayer dielectric and a metallization layer, forming source / drain contacts to the source / drain regions, and forming source / drain vias and gate vias.

[0108] It should be understood that method 20 includes steps characteristic of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore is only briefly described herein. Additionally, extra steps may be performed before, after, and / or during method 20.

[0109] Now for reference Figure 3 The illustration shows method 30. Method 30 includes forming a structure over a substrate at operation S31. The structure may include a fin structure formed from a portion of the substrate and layers covering the substrate, such as during the formation of the fin structure to process a gate-all-around (GAA) device.

[0110] At operation S32, method 30 includes forming a dummy gate line over the structure. Specifically, the dummy gate line is formed from a sacrificial material (such as polysilicon) to be removed during a later processing.

[0111] At operation S33, method 30 includes forming an interlayer dielectric material adjacent to the dummy gate line.

[0112] At operation S34, method 30 includes patterning a mask above the dummy gate line. Specifically, the mask may be patterned to form one or more openings directly above, i.e., vertically above, the portion of the dummy gate line to be removed and replaced with an isolation structure.

[0113] At operation S35, method 30 includes etching through the dummy gate line to form a trench. For example, an etching process may be performed to remove one or more portions of the dummy gate line located directly beneath one or more openings in a mask. Each opening completely separates the dummy gate line into two adjacent dummy gate line portions. In other words, no remaining portion of the dummy gate line extends between adjacent dummy gate line portions. Furthermore, the etching process may continue beneath the dummy gate line, such as etching into an underlying shallow trench isolation (STI) feature or etching into the underlying semiconductor substrate.

[0114] At operation S36, method 30 includes forming a diced isolation structure in the trench, i.e., dicing a dummy or dicing a polysilicon isolation structure. For example, method 10 may deposit a single layer of isolation material, multiple layers of isolation material, or multiple layers of at least two types of isolation material. In embodiments, each layer of the isolation material is conformally deposited. In some embodiments, the isolation material merges at a selected height to enclose cavitation within the isolation structure. In other embodiments, merging of the isolation material at the upper height is avoided to prevent cavitation formation.

[0115] At operation S37, method 30 includes removing one or more remaining portions of the dummy gate line to form one or more gate cavities. Specifically, the gate cavities are located between and delimited by adjacent cut isolation structures and interlayer dielectric material.

[0116] At operation S38, method 30 includes forming a metal gate structure in each gate cavity.

[0117] Method 30 may include further processing at operation S39 to complete the fabrication of a semiconductor device or integrated circuit. For example, according to some embodiments, further processing may include forming an interlayer dielectric and metallization layer, forming source / drain contacts to the source / drain regions, and forming source / drain vias and gate vias.

[0118] It should be understood that method 30 includes steps characteristic of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore is only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during method 30.

[0119] Now for reference Figure 4 The diagram illustrates method 40. Method 40 includes designing the layout of a semiconductor or integrated circuit device at operation S41. In some specific embodiments, the device includes a first gate structure and a second gate structure separated by an isolation structure. The device may be a GAA device.

[0120] At operation S42, method 40 includes determining desired device performance conditions and / or desired process yield conditions. For example, device yield may be given priority, and a minimum device yield may be selected as the desired process yield condition. Alternatively, desired device performance conditions, such as effective capacitance, may be selected. In other embodiments, a relatively low minimum device yield and a relatively high effective capacitance may be selected as the desired conditions.

[0121] At operation S43, method 40 includes selecting the structure of the isolation structure to provide the desired conditions. In some embodiments, the structure of the isolation structure comprises a selected shape.

[0122] At operation S44, method 40 includes performing an integrated circuit manufacturing process. The integrated circuit manufacturing process can be described as method 10, method 20, or method 30 described above. The integrated circuit manufacturing process may include forming a gate line over a semiconductor substrate; performing an etching process to remove a portion of the gate line and form a trench of a selected shape; and forming an isolation structure in the trench. The isolation structure may be selectively shaped as having no air gap, a small air gap, or a full air gap.

[0123] It should be understood that method 40 includes steps characteristic of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore is only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during method 40.

[0124] refer to Figure 5 This provides a top view of a semiconductor or integrated circuit device 100. Figure 5 In the device 100, there is a multilayer structure 103 which includes a plurality of nanosheets formed on a semiconductor substrate 201 (as shown in the following figures); fins 105 formed in the multilayer structure 103; and a plurality of gate electrodes 107 in the form of gate lines 111 above the fins 105. Figure 5 Further illustration shows multiple isolation structures 109 separating the two in the gate line 111.

[0125] although Figure 5 The following figures illustrate three fins 105, but it should be understood that any suitable number of fins 105 can be formed in the multilayer structure 103 to form the desired GAA semiconductor device 100, depending on the required design and number of fins. Furthermore, any suitable number of gate electrodes 107 / gate lines 111 and isolation structures 109 can be formed to form the desired GAA semiconductor device 100.

[0126] exist Figure 5In the diagram, the X-axis extends through the length of the fin 105. Furthermore, the Y-axis extends through the length of the gate line 111, which has been separated by the two isolation structures 109, and through the two isolation structures 109. The following cross-sectional view is taken along the Y-axis.

[0127] Figures 6 to 13 The diagram is based on the method used to form the above. Figure 5 The operation of method 10 and method 20 of apparatus 100. Specifically, the isolation final (i.e., after the metal gate is formed) processing method is performed.

[0128] Now for reference Figure 6 According to some embodiments, a method for manufacturing a semiconductor device 100 includes forming a multilayer structure 103 over a semiconductor material such as a substrate, and forming a structure 105 such as a fin 105 in the multilayer structure 103.

[0129] In embodiments, substrate 201 is a semiconductor substrate, which may, for example, be a silicon substrate, a silicon-germanium substrate, a germanium substrate, a III-V material substrate (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof), or a substrate formed from other semiconductor materials using, for example, high-band-to-band tunneling (BTBT). Substrate 201 may be doped or undoped. In some embodiments, substrate 201 may be a bulk semiconductor substrate, such as a bulk silicon substrate of a wafer, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like.

[0130] Figure 6 The illustration depicts a deposition process for forming a multilayer structure 103 during an intermediate stage of manufacturing a GAA semiconductor device 100, according to some embodiments. Specifically, Figure 6 A series of depositions are further illustrated, which are performed to form a multilayer stack 203 of alternating materials of a first layer 205 and a second layer 207 over a substrate 201.

[0131] According to some embodiments, the first layer 205 may be formed using a first semiconductor material having a first lattice constant, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like. In some embodiments, the first layer 205 of the first semiconductor material (e.g., SiGe) is epitaxially grown on the substrate 201 using deposition techniques such as epitaxial growth, vapor-phase epitaxy (VPE), or molecular beam epitaxy (MBE), although other deposition processes may also be used, such as chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), combinations thereof, or the like. In some embodiments, the first layer 205 is formed with a thickness from about 3 nm to about 10 nm. However, any suitable thickness can be used while remaining within the scope of the embodiments.

[0132] After a first layer 205 has been formed over substrate 201, a second layer 207 may be formed over the first layer 205. According to some embodiments, the second layer 207 may be formed using a second semiconductor material having a second lattice constant different from the first lattice constant of the first layer 205, such as silicon (Si), SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like. In a particular embodiment where the first layer 205 is silicon-germanium, the second layer 207 is a material such as silicon. However, any suitable combination of materials may be used for the first layer 205 and the second layer 207.

[0133] In some embodiments, a second layer 207 is epitaxially grown on the first layer 205 using a deposition technique similar to that used to form the first layer 205. However, the second layer 207 can use any of the deposition techniques suitable for forming the first layer 205 as described above, or any other suitable technique. According to some embodiments, the second layer 207 is formed to a thickness similar to that of the first layer 205. However, the second layer 207 can also be formed to a different thickness than the first layer 205. According to some embodiments, the second layer 207 can be formed to a thickness from about 5 nm to about 15 nm. However, any suitable thickness can be used.

[0134] After the second layer 207 is formed over the first layer 205, the deposition process is repeated to form a series of alternating layers of material in the first layer 205 and the second layer 207 until the desired top layer of the multilayer stack 203 has been formed. According to this embodiment, the first layer 205 may be formed with the same or similar first thickness, and the second layer 207 may be formed with the same or similar second thickness. However, the first layer 205 may have different thicknesses from each other, and / or the second layer 207 may have different thicknesses from each other, and any combination of thicknesses may be used for the first layer 205 and the second layer 207. According to this embodiment, the top layer of the multilayer stack 203 is formed as the second layer 207; however, in other embodiments, the top layer of the multilayer stack 203 may be formed as the first layer 205. Furthermore, although embodiments comprising three first layers 205 and three second layers 207 are disclosed herein, the multilayer stack 203 may have any suitable number of layers (e.g., nanosheets). For example, the multilayer stack 203 may comprise from two to ten nanosheets. In some embodiments, the multilayer stack 203 may include an equal number of first layers 205 to second layers 207; however, in other embodiments, the number of first layers 205 may differ from the number of second layers 207. According to some embodiments, the multilayer stack 203 may be formed with a height from about 12 nm to about 100 nm. However, any suitable height may be used.

[0135] Figure 6 Further illustrations depict a patterning process for a multilayer structure 103 and the formation of isolation regions 209, such as shallow trench isolation (STI) regions, during an intermediate stage of manufacturing a GAA semiconductor device 100, according to some embodiments. The patterning process is used to form fins 105 in the multilayer structure 103 and trenches between the fins 105 to prepare for the formation of the isolation regions 209. According to some embodiments, the patterning process for forming the fins 105 includes applying a photoresist over the multilayer stack 203, followed by patterning and developing the photoresist to form a mask over the multilayer stack 203. After the mask is formed, the mask is then used during an etching process, such as an anisotropic etching process, to transfer the pattern of the mask into the underlying layer, thereby forming trenches through the multilayer stack 203, and transferring the pattern into the substrate 201 to define the fins 105, wherein the fins 105 are separated by the trenches.

[0136] Furthermore, while a single masking process has been described, this is for illustrative purposes and not intended to be limiting, as gate-all-around (GAA) device structures can be patterned using any suitable method. For example, one or more optical lithography processes can be used to pattern the structure, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0137] In embodiments, isolation region 209 is formed as a shallow trench isolation region by depositing dielectric material in the trench. According to some embodiments, the dielectric material used to form isolation region 209 may be, for example, an oxide material (e.g., a flowable oxide), a high-density plasma (HDP) oxide, or similar materials. The dielectric material may be formed after optional cleaning and lining of the trench using a chemical vapor deposition (CVD) method (e.g., HARP process), a high-density plasma CVD method, or other suitable formation method to fill or overfill the area surrounding fin 105. In some embodiments, a post-placement annealing process (e.g., oxide densification) is performed to densify the material of isolation region 209 and reduce its wet etching rate. Chemical mechanical polishing (CMP), etching, combinations thereof, or similar methods may be performed to remove any excess material from isolation region 209.

[0138] After a dielectric material has been deposited to fill or overfill the area surrounding the fin 105, the dielectric material can then be recessed from the surface of the fin 105 to form an isolation region 209. The recess can be performed to expose at least a portion of the sidewalls of the fin adjacent to the top surface of the fin 105. The dielectric material can be recessed using wet etching by immersing the top surface of the fin 105 in an etchant selective for the dielectric material, although other methods such as reactive ion etching, dry etching, chemical oxide removal, or dry chemical cleaning can also be used.

[0139] Figure 6Further illustration shows the formation of a dummy gate dielectric 211 above the exposed portion of fin 105. After the isolation region 209 has been formed, the dummy gate dielectric 211 can be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known and used in the art for forming a gate dielectric. Depending on the gate dielectric formation technique, the thickness of the dummy gate dielectric 211 on the top may differ from the thickness of the dummy dielectric on the sidewalls. In some embodiments, the dummy gate dielectric 211 can be formed by depositing a material such as silicon, followed by oxidizing or nitriding the silicon layer to form a dielectric such as silicon dioxide or silicon oxynitride. In such embodiments, the dummy gate dielectric 211 can be formed as a self-limiting... to approximately Such as The thickness. In other embodiments, the dummy gate dielectric 211 may also be formed from a high dielectric constant (high k) material, such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or combinations thereof, with an equivalent oxide thickness of approximately to approximately Such as Or smaller. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials can also be used as the dummy gate dielectric 211.

[0140] exist Figure 7 In some embodiments, the method may continue, wherein a sacrificial or dummy gate stack 301 is formed over the fin 105. According to some embodiments, the dummy gate stack 301 includes a dummy gate dielectric 211, a dummy gate electrode 303 over the dummy gate dielectric 211, a first hard mask 305 over the dummy gate electrode 303, and a second hard mask 307 over the first hard mask 305.

[0141] In some embodiments, the dummy gate electrode 303 comprises a conductive material and may be selected from the group consisting of: polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or similar materials. The dummy gate electrode 303 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The thickness of the dummy gate electrode 303 may be [adjusted / reduced]. to approximately The top surface of the dummy gate electrode 303 may have a non-planar top surface and may be planarized prior to patterning or gate etching of the dummy gate electrode 303. At this point, ions may or may not be introduced into the dummy gate electrode 303. Ions may be introduced, for example, by ion implantation techniques.

[0142] After the dummy gate electrode 303 has been formed, the dummy gate dielectric 211 and the dummy gate electrode 303 can be patterned. In an embodiment, patterning can be performed by initially forming a first hard mask 305 over the dummy gate electrode 303 and then forming a second hard mask 307 over the first hard mask 305.

[0143] According to some embodiments, the first hard mask 305 comprises a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxide (SiO), titanium nitride (TiN), silicon oxynitride (SiON), combinations thereof, or the like. The first hard mask 305 can be formed using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable materials and formation methods may be utilized. The first hard mask 305 can be formed as a self-contained... to approximately Such as The thickness.

[0144] The second hard mask 307 comprises a dielectric material different from that of the first hard mask 305. The second hard mask 307 may comprise any of the materials suitable for forming the first hard mask 305 and may use any of the processes suitable for forming the first hard mask 305, and may be formed to the same or similar thickness as the first hard mask 305. In embodiments where the first hard mask 305 comprises silicon nitride (SiN), the second hard mask 307 may be, for example, oxide (OX). However, the second hard mask may be formed using any suitable dielectric material, process, and thickness.

[0145] After forming the first hard mask 305 and the second hard mask 307, the first hard mask 305 and the second hard mask 307 can be patterned. The patterning of the first hard mask 305 and the second hard mask 307 occurs in the X dimension, that is, for... Figures 6 to 13 The cross-sectional view is shown, extending a certain distance into and out of the drawing. Subsequently, various processes can be performed to form the desired structure, including etching dummy gate material to form different dummy gate stacks, forming spacers, etching openings for the source / drain regions, epitaxial growth of the source / drain regions, implantation processes, and other typical gate treatments.

[0146] exist Figure 8The method can continue, wherein the first hard mask 305 and the second hard mask 307 are removed. According to some embodiments, the first hard mask 305 and the second hard mask 307 can be removed using one or more etching processes and / or chemical mechanical polishing (CMP). Thus, the dummy gate electrode 303 is exposed after the removal of the first hard mask 305.

[0147] exist Figure 9 The method can continue, wherein the dummy gate electrode 303 and the dummy gate dielectric 211 are removed. Figure 9 Further illustrations of some embodiments illustrate a wire release process for forming nanostructures 701, i.e., vertically spaced nanosheets, from the second layer 207. Figure 9 The formation of the gate dielectric 703 above the nanostructure 701 is further illustrated according to some embodiments.

[0148] After exposure by removing the first hard mask 305, the dummy gate electrode 303 can be removed to expose the underlying dummy gate dielectric 211. In an embodiment, the dummy gate electrode 303 is removed using, for example, one or more wet or dry etching processes that utilize etchants selective for the material of the dummy gate electrode 303. However, any suitable removal process may be used.

[0149] After the dummy gate dielectric 211 has been exposed by removing the dummy gate electrode 303, the dummy gate dielectric 211 can be removed. In an embodiment, the dummy gate dielectric 211 can be removed using, for example, a wet etching process, although any suitable etching process can be used.

[0150] After the dummy gate dielectric 211 has been removed (which also exposes the sides of the first layer 205), the first layer 205 can be removed between the substrates 201 and between the second layer 207 in the wire release process step. The wire release process step may also be referred to as a wafer release process step, a wafer formation process step, a nanosheet formation process step, or a wire formation process step. In an embodiment, a wet etching process can be used to remove the first layer 205, selectively removing the material of the first layer 205 (e.g., silicon-germanium (SiGe)) without significantly removing the material of the substrate 201 and the second layer 207 (e.g., silicon (Si)). However, any suitable removal process can be used.

[0151] For example, in an embodiment, an etchant such as high-temperature HCl can be used to selectively remove the material of the first layer 205 (e.g., SiGe) without substantially removing the material of the substrate 201 and / or the material of the second layer 207 (e.g., Si). Alternatively, the wet etching process can be performed at a temperature of approximately 560°C to approximately 400°C to approximately 600°C for a duration of approximately 100 seconds to approximately 600 seconds, such as approximately 300 seconds. However, any suitable etchant, process parameters, and time can be used.

[0152] By removing the material of the first layer 205, the side of the second layer 207 ( Figure 9 The re-marked nanostructure 701 is exposed. According to some embodiments, the nanostructure 701 is perpendicularly separated or spaced apart from each other at a spacing of about 5 nm to about 15 nm, such as about 10 nm. The nanostructure 701 includes a channel region between opposite sources / drains in the source / drain region 503, having a channel length (in the X direction in the in-and-out direction) from about 5 nm to about 180 nm, such as about 10 nm, and a channel width in the Y direction from about 8 nm to about 100 nm, such as about 30 nm. In embodiments, the nanostructure 701 is formed to have the same thickness as the original thickness of the second layer 207, such as from about 3 nm to about 15 nm, such as about 8 nm, although the thickness can also be reduced using an etching process.

[0153] In some embodiments, the wire release step may include an optional step of partially removing material from the second layer 207 during the removal of the first layer 205 (e.g., by over-etching). Thus, the thickness of the nanostructure 701 is formed to have a reduced thickness compared to the original thickness of the second layer 207. Thus, the thickness of the nanostructure 701 may be less than the original thickness of the second layer 207.

[0154] although Figure 9 The illustration shows three nanostructures 701, but any suitable number of nanostructures 701 can be formed from the nanosheets provided in the multilayer stack 203. For example, the multilayer stack 203 can be formed to include any suitable number of first layers 205 and any suitable number of second layers 207. Thus, a multilayer stack 203 containing fewer first layers 205 and fewer second layers 207 forms one or two nanostructures 701 after removing the first layer 205. However, a multilayer stack 203 containing many first layers 205 and many second layers 207 forms four or more nanostructures 701 after removing the first layer 205.

[0155] Figure 9Further illustration shows the formation of a gate dielectric 703 above the nanostructure 701 according to some embodiments. In embodiments, the gate dielectric 703 comprises a high-k material (e.g., K greater than or equal to 9) deposited via processes such as atomic layer deposition, chemical vapor deposition, or the like, such as Ta2O5, Al2O3, Hf oxides, Ta oxides, Ti oxides, Zr oxides, Al oxides, La oxides (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO), combinations of these materials, or the like. In some embodiments, the gate dielectric 703 comprises a nitrogen-doped oxide dielectric that is initially formed prior to the formation of a dielectric material with a high metal content (e.g., K value > 13). The gate dielectric 703 may be deposited to a thickness of about 1 nm to about 3 nm, although any suitable material and thickness may be used. In some embodiments, the gate dielectric 703 surrounds the nanostructure 701, thereby forming a channel region between the source / drain regions.

[0156] exist Figure 10 In the process, the method can continue, wherein a metal gate line 111 is formed above the fin structure (e.g., Figure 5 (As shown in the diagram). For example, according to some embodiments, method 10 includes forming a gate electrode 107 and a gate cap 801, both forming a metal gate line. After the gate dielectric 703 has been formed, the gate electrode 107 is formed to surround the nanostructure 701. For example, the inter-sheet portion of the metal gate is located between the nanosheets 701.

[0157] In some embodiments, the gate electrode 107 is formed using a multilayer, with each layer sequentially deposited adjacent to each other using a highly conformal deposition process such as atomic layer deposition, although any suitable deposition process may be used. According to some embodiments, the gate electrode 107 may include a capping layer, a barrier layer, an n-metal work function layer, a p-metal work function layer, and a filler material.

[0158] The capping layer may be formed adjacent to the gate dielectric 703 and may be formed of a metallic material, such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. The metallic material may be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0159] The barrier layer may be formed adjacent to the capping layer and may be formed of a material different from the capping layer. For example, the barrier layer may be formed of a material such as one or more layers of metallic materials, such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. The barrier layer may be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0160] The n-metal work function layer may be formed adjacent to the barrier layer. In embodiments, the n-metal work function layer is a material such as W, Cu, AlCu, TiAlC, TiAlN, TiAl, Pt, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer may be deposited using atomic layer deposition (ALD), CVD, or similar processes. However, the n-metal work function layer may be formed using any suitable material and process.

[0161] The p-metal work function layer may be formed adjacent to the n-metal work function layer. In embodiments, the first p-metal work function layer may be formed of metallic materials such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar metallic materials. Furthermore, the p-metal work function layer may be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, or similar methods, although any suitable deposition process may be used.

[0162] After forming the p-metal work function layer, a filler material is deposited to fill the remaining portion of the opening. In embodiments, the filler material may be a combination of materials such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or similar materials, and may be formed using deposition processes such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, or combinations thereof, or similar methods. However, any suitable material may be used.

[0163] After the opening left by removing the dummy gate electrode 303 has been filled, the materials of the gate electrode 107 and the gate dielectric 703 can be planarized to remove any material remaining outside the opening after removing the dummy gate electrode 303. In a particular embodiment, removal can be performed using a planarization process such as chemical mechanical polishing, although any suitable planarization and removal process can be utilized. According to some embodiments, the gate electrode can be formed to a length of about 8 nm to about 30 nm. However, any suitable length can be used.

[0164] After formation, the gate electrode 107 can be recessed. According to some embodiments, etching processes such as wet etching, dry etching, combination etching, or similar etching processes can be used to recess the gate electrode 107. After recessing, the height of the gate electrode 107 above the topmost of the nanostructure 701 is, for example, about 8 nm to about 30 nm. However, any suitable height can be used.

[0165] The gate cap 801 can be formed by initially depositing a dielectric material over the gate electrode 107 to fill and / or overfill the trench. In some embodiments, the gate cap 801 is formed using a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or the like. According to some embodiments, the gate cap 801 is formed using a metal oxide such as zirconium (Zr), hafnium (Hf), aluminum (Al), or the like. Furthermore, the gate cap 801 can be formed using suitable deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations thereof, or the like. However, any suitable material and deposition process can be used. After deposition, the gate cap 801 can be planarized using a planarization process such as chemical mechanical polishing. After planarization, the gate cap 801 has a vertical thickness of about 10 nm to about 30 nm. However, any suitable thickness can be used.

[0166] exist Figure 11 In some embodiments, the method may continue, wherein a trench 901 is formed in a metal gate dicing process. After the gate cap 801 has been planarized, a masking layer 803 may be deposited over the planar surface of the gate cap 801. After deposition, the masking layer 803 is patterned to expose the underlying material of the gate cap 801, including the desired location of the isolation structure 109 to be formed.

[0167] After patterning, the masking layer 803 serves as an etching mask to etch the underlying material, thereby forming trenches 901 (e.g., trenches, recesses, channels, or the like). In the etching process, the materials of the gate cap 801 and the gate electrode 107 are etched using an anisotropic etching process. In some embodiments, the etching process continues through the gate dielectric 703 and into the isolation region 209. Trenches 901 may be formed between adjacent fins 105 and may be formed to cut through one or more gate electrodes 107. According to some embodiments, both trenches 901 are formed to cut through two adjacent gate electrodes 107 and are located on opposite sides of one of the fins 105. After the trenches 901 have been formed, the masking layer 803 may be removed.

[0168] exist Figure 12 In some embodiments, method 10 may continue, wherein an isolation structure 109 is formed. After trench 901 has been formed, isolation structure 109 is formed by initially depositing a dielectric material to fill and overfill trench 901. According to some embodiments, isolation structure 109 is formed using any dielectric material and deposition process suitable for forming gate cap 801. In some embodiments, the dielectric material used to form isolation structure 109 is the same as the dielectric material used to form gate cap 801, although the dielectric material may be different. For example, in embodiments where gate cap 801 is formed using silicon nitride (SiN), isolation structure 109 may also be formed using silicon nitride in a deposition process such as atomic layer deposition (ALD). However, any suitable dielectric material and deposition process may be used. According to some embodiments, isolation structure 109 is formed with a width of about 5 nm to about 50 nm, such as about 10 nm. However, any suitable width may be used.

[0169] The isolation structure 109 divides the two relatively long gate electrodes 107 or lines 111 into a plurality of relatively short segmented gate electrodes 107 and isolates the segmented gate electrodes 107 from each other. In addition, excess dielectric material of the isolation structure 109 outside the trench 901 can be retained and used as a masking layer in the Continuous Poly On Diffusion Edge (CPODE) process.

[0170] exist Figure 13 In this process, a chemical mechanical planarization (CMP) process is performed to remove the overlay portion of the deposited isolation material, thereby forming an isolation structure 109.

[0171] Now for reference Figures 14 to 17 The illustration shows further details of the device 100. Figure 14 This is a perspective view of an embodiment of device 100, in which a portion of the metal gate has been removed to allow observation of the internal structure. Figure 14 In one embodiment, the isolation structure 109 is formed in the trench, while the shielding layer 803 remains above the device 100. For example... Figure 14 As shown, two metal gate lines 111 extend in the Y direction and are separated from each other by a source / drain region 503 and an interlayer dielectric (ILD) structure 953 located above the source / drain region 503. As used herein, "source / drain region" may refer to the source region alone or together depending on the context. Note that the ILD structure 953 is formed around the dummy gate electrode and defines the gate cavity during the gate replacement process.

[0172] Figure 15 It is a section taken along metal gate line 111. Figure 14 Y-shaped cross-sectional view of device 100. Figure 15 The illustration shows the fabrication stage after the etched trench 901 and before the formation of the isolation structure 109 within the trench 901. As shown, the trench 901 separates the two stacks of the nanostructure 701.

[0173] Figure 16 It is a cut along the 953 segment of the ILD structure. Figure 14 Y-shaped cross-sectional view of device 100. Figure 16 The illustration shows the manufacturing stage after the trench 901 has been etched and before the isolation structure 109 is formed in the trench 901. As shown, the trench 901 separates the two source / drain regions 503.

[0174] like Figure 15 and Figure 16 As shown, trench 901 extends vertically and laterally through metal gate line 111, vertically through ILD structure 953, and into underlying shallow trench isolation (STI) region 209.

[0175] Figure 17 It was cut along trench 901. Figure 14An X-shaped cross-sectional view of the device 100 is shown, and adjacent unetched portions of the device 100 are illustrated in phantom form. Figure 17 The illustration shows the manufacturing stage after the etched trench 901 and before the formation of the isolation structure 109 in the trench 901.

[0176] Figures 18 to 24 This is a perspective view illustrating an embodiment of an etched trench 901 through gate line 111.

[0177] exist Figure 18 In the figure, four parallel gate lines 111 extend in the Y direction and are separated from each other by the ILD structure 953. As shown, the gate lines 111 and the ILD structure 953 are located above the fins 105 formed on the substrate 201 and separated by the STI region 209.

[0178] exist Figure 19 In Figure 18 A mask 803 is formed above the structure of the device 100. The mask may include multiple layers, such as a silicon nitride layer, a silicon layer, and a silicon nitride layer.

[0179] exist Figure 20 In the middle, as shown by arrow 804, perform photoresist removal or stripping.

[0180] exist Figure 21 In Figure 20 A photoresist 860 is formed and patterned on the top of the device structure. As shown, the photoresist 860 includes a bottom layer 861, a middle layer 862, and a top layer 863. The top layer 863 is patterned with an opening 870, which covers the region 1117 of the gate line 111 to be removed.

[0181] exist Figure 22 In the middle, the intermediate layer 862 is etched through the opening 870, and the top layer 863 is removed.

[0182] exist Figure 23 In the middle, the bottom layer 861 is etched through the opening 870, and the middle layer 862 is removed.

[0183] exist Figure 24 In the process, the masking layer 803 is etched through the opening 870, and the bottom layer 861 is removed. As shown, the area 1117 of the metal line 111 to be removed is uncovered.

[0184] exist Figure 25 In the middle, the gate line 111 and the ILD structure 953 surrounded by the selected gate line 111 are etched through the opening 870. Figure 26 yes Figure 25 A perspective view of the structure, providing a Y-shaped cross-section through the source / drain region 503. Figure 27 yes Figure 25A perspective view of the structure, providing a Y-shaped cross-section through the gate line 111.

[0185] Cross-reference Figures 25 to 27 The groove 901 has a sidewall 902. Although Figures 25 to 27 The sidewall 902 is essentially planar, but it is envisioned that an etching process for etching trench 901 can be performed to form a sidewall 902 corresponding to trench 901 having the desired cross-sectional shape.

[0186] For example, Figures 28 to 30 It is a Y-shaped cross-sectional view of the groove 901 that forms the isolation structure or structure 109.

[0187] exist Figure 28 The figure illustrates a portion 200 of the device 100, which includes a V-shaped trench 901 formed by the etching process described above. As shown, a V-shaped isolation structure 109 is formed within the V-shaped trench 901. The isolation structure extends through the metal gate line forming the metal gate electrode 107 and into the isolation region 209.

[0188] The trench extends from the bottom 903 to the opening 904. The lateral width W of the V-shaped trench 901 and the V-shaped isolation structure 109 in the Y direction, from sidewall 9021 to sidewall 9022, continuously increases from the bottom 903 to the opening 904. As shown, the lateral width increases at a constant rate from near the bottom 903 to the opening 904, such that the maximum width is at the opening 904.

[0189] As shown in the figure, the V-shaped groove 901 and the isolation structure 109 have a total vertical depth D in the Z direction from the groove opening 904 to the groove bottom 903. In some embodiments, the V-shaped groove 901 and the isolation structure 109 have a depth D in a ratio of at least 3:1 to the maximum width, such as at least 4:1, at least 5:1, at least 6:1, at least 7:1, at least 8:1, at least 9:1, or at least 10:1. In some embodiments, the V-shaped groove 901 and the isolation structure 109 have a depth in a ratio of no more than 12:1 to the maximum width, such as no more than 10:1, no more than 9:1, no less than 8:1, no more than 7:1, no more than 6:1, no more than 5:1, or no more than 4:1.

[0190] exist Figure 28 In this embodiment, the isolation structure 109 formed within the trench 901 does not have any air gaps. In some embodiments, the isolation structure 109 may have a seam 920, wherein one or more layers of isolation material formed on and growing therefrom on the sidewall 9021 are in contact with one or more layers of isolation material formed on and growing therefrom on the sidewall 9022.

[0191] As used herein, the air gap-free isolation structure 109 has a total air content of less than 2% of the volume, such as less than 1.5%, 1%, 0.5%, 0.1%, 0.05%, or 0.01% of the volume.

[0192] exist Figure 29 The figure illustrates a portion 200 of the device 100, which includes a spear-shaped trench 901 formed by the etching process described above. As shown, a spear-shaped isolation structure 109 is formed within the spear-shaped trench 901. The isolation structure extends through the metal gate line forming the metal gate electrode 107 and into the isolation region 209.

[0193] The trench extends from the bottom 903 to the opening or apex 904. The lateral width W of the spear-shaped trench 901 and the spear-shaped isolation structure 109 in the Y direction, from sidewall 9021 to sidewall 9022, continuously increases from the bottom 903 to a maximum value 906, decreases to a minimum value 907, and then increases again from the minimum value to the opening 904. The width at the minimum value 907 is less than the width at the maximum value 906 and less than the width at the opening 904. In some embodiments, the width at the maximum value 906 is greater than the width at the opening 904. In some embodiments, the width at the maximum value 906 is less than the width at the opening 904. In some embodiments, the width at the maximum value 906 is substantially equal to the width at the opening 904.

[0194] As shown in the figure, the spear-shaped groove 901 and the isolation structure 109 have a total vertical depth D in the Z direction from the groove opening 904 to the groove bottom 903. In some embodiments, the spear-shaped groove 901 has a depth D in a ratio of at least 3:1 to its maximum width, such as at least 4:1, at least 5:1, at least 6:1, at least 7:1, at least 8:1, at least 9:1, or at least 10:1. In some embodiments, the spear-shaped groove 901 has a depth in a ratio of no more than 12:1 to its maximum width, such as no more than 10:1, no more than 9:1, no more than 8:1, no more than 7:1, no more than 6:1, no more than 5:1, or no more than 4:1.

[0195] exist Figure 29 In the groove 901, the isolation structure 109 formed has a small air gap 980. Specifically, when one or more layers of isolation material formed and grown on the sidewall 9021 come into contact with one or more layers of isolation material formed and grown on the sidewall 9022 at the bottleneck position 930 above the small air gap 980, the small air gap 980 is closed.

[0196] As used herein, the isolation structure 109 with small air gaps has a total air content greater than 2% of the volume, such as greater than 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, or 20%. As used herein, the isolation structure 109 with small air gaps has a total air content less than 25% of the volume, such as less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, or 3%.

[0197] The vertical height of the air gap 980 can be selected, such that the isolation structure 109 forms an air gap 980 with the selected vertical height. As shown, the air gap 980 has a vertical height H1 in the Z direction from the top 981 of the air gap to the bottom 982 of the air gap. As used herein, the small air gap has a vertical height H1 of at least one-tenth of the total depth D, i.e., 0.1 (D), such as at least 0.2 (D), 0.3 (D), or 0.4 (D). As used herein, the small air gap has a vertical height H1 of no more than 0.5 (D), such as no more than 0.4 (D), 0.3 (D), or 0.2 (D).

[0198] The depth of the air gap 980 can be selected so that the isolation structure 109 forms an air gap 980 at the selected depth. For example, it is desirable for the top 981 of the air gap to be located at a selected vertical depth D1 from the groove opening 904 in the Z direction.

[0199] In some embodiments, the depth D1 is at least one-tenth of the total depth D, i.e., 0.1(D), such as at least 0.2(D), 0.3(D), 0.4(D), 0.5(D), 0.6(D), 0.7(D), or 0.8(D). In some embodiments, the depth D1 is not greater than 0.9(D), such as not greater than 0.8(D), 0.7(D), 0.6(D), 0.5(D), 0.4(D), 0.3(D), or 0.2(D).

[0200] exist Figure 30 The figure illustrates a portion 200 of the device 100, which includes a carrot-shaped trench 901 formed by the etching process described above. As shown, a carrot-shaped isolation structure 109 is formed within the carrot-shaped trench 901. The isolation structure extends through the metal gate line forming the metal gate electrode 107 and into the isolation region 209.

[0201] The groove extends from the bottom 903 to the opening 904. The lateral width W of the carrot-shaped groove 901 and the carrot-shaped isolation structure 109 in the Y direction, from sidewall 9021 to sidewall 9022, continuously increases from the bottom 903 to the upper position 908, and decreases from the upper position 908 to the opening 904. As shown, the lateral width of the groove 901 increases rapidly from the bottom 903, then slows down, and increases constantly to the upper position 908. In this way, the carrot shape is defined.

[0202] As shown in the figure, the carrot-shaped groove 901 and the isolation structure 109 have a total vertical depth D in the Z direction from the groove opening 904 to the groove bottom 903. In some embodiments, the carrot-shaped groove 901 has a depth D in a ratio of at least 3:1 to its maximum width, such as at least 4:1, at least 5:1, at least 6:1, at least 7:1, at least 8:1, at least 9:1, or at least 10:1. In some embodiments, the carrot-shaped groove 901 has a depth in a ratio of no more than 12:1 to its maximum width, such as no more than 10:1, no more than 9:1, no more than 8:1, no more than 7:1, no more than 6:1, no more than 5:1, or no more than 4:1.

[0203] exist Figure 30 In the groove 901, the isolation structure 109 has a full air gap or a large air gap 990. Specifically, when one or more layers of isolation material formed on and growing from the sidewall 9021 come into contact with one or more layers of isolation material formed on and growing from the sidewall 9022 at the bottleneck position 930 above the full air gap 990, the full air gap 990 is closed.

[0204] As used herein, the isolation structure 109 having a full air gap 990 has a total air content greater than 20% of the volume, such as greater than 25%, 30%, 35%, 40%, 45%, or 50% of the volume. As used herein, the isolation structure 109 having a full air gap 990 has a total air content less than 90% of the volume, such as less than 80%, 70%, 60%, 55%, 50%, 45%, 40%, 30%, or 25% of the volume.

[0205] The vertical height of the air gap 990 can be selected, such that the isolation structure 109 forms an air gap 990 with the selected vertical height. As shown, the air gap 990 has a vertical height H2 in the Z direction from the top 991 to the bottom 992. As used herein, the vertical height H2 of the entire air gap is at least half of the total depth D, i.e., 0.5 (D), such as at least 0.6 (D), 0.7 (D), 0.8 (D), or 0.9 (D). As used herein, the entire air gap has a vertical height H2 not greater than 0.95 (D), such as not greater than 0.9 (D), 0.8 (D), 0.7 (D), or 0.6 (D).

[0206] The depth of the air gap 990 can be selected so that the isolation structure 109 forms an air gap 990 at the selected depth. For example, it is desirable for the top 991 of the air gap to be located at a selected vertical depth D2 from the groove opening 904 in the Z direction.

[0207] In some embodiments, the depth D2 is at least one-twentieth of the total depth D, i.e., 0.05(D), such as at least 0.1(D), 0.2(D), 0.3(D), 0.4(D), or 0.5(D). In some embodiments, the depth D2 is not greater than 0.5(D), such as not greater than 0.4(D), 0.3(D), 0.2(D), or 0.1(D).

[0208] As described herein, methods are provided for providing isolation structures with desired properties. The isolation structure can be used to isolate adjacent metal gate structures or electrodes. The isolation structure can be formed using methods optimized for yield, methods optimized for forming isolation structures with low effective capacitance, or methods balancing yield and effective capacitance performance.

[0209] A method of manufacturing an integrated circuit device includes forming a gate line over a semiconductor substrate; patterning a mask over the gate line, wherein an opening in the mask is located over a region of the gate line to be removed; performing an etching process through the opening to form a trench; and forming an isolation structure in the trench, wherein the isolation structure is selectively shaped to be gapless, have a small air gap, or have a full air gap.

[0210] In some embodiments of the method, the gate line is a dummy gate line, and the method further includes: after forming an isolation structure in the trench, removing the dummy gate line to form a gate cavity; and forming a metal gate structure in the gate cavity and adjacent to the isolation structure.

[0211] In some embodiments of the method, the gate line is a metal gate line, and the method further includes: forming a dummy gate line over a semiconductor substrate; forming an interlayer dielectric adjacent to the dummy gate line; and removing the dummy gate line to form a gate cavity; wherein forming the gate line over the semiconductor substrate includes forming a metal gate line in the gate cavity.

[0212] In some embodiments of the method, performing an etching process through an opening to form a trench includes forming a V-shaped trench; forming an isolation structure in the trench includes forming a gapless isolation structure.

[0213] In some embodiments of the method, performing an etching process through an opening to form a trench includes forming a spear-shaped trench; forming an isolation structure in the trench includes forming an isolation structure with small air gaps.

[0214] In some embodiments of the method, performing an etching process through an opening to form a trench includes forming a carrot-shaped trench; forming an isolation structure in the trench includes forming an isolation structure with a full air gap.

[0215] In some embodiments of the method, forming an isolation structure in the trench includes depositing a single layer of isolation material.

[0216] In some embodiments of the method, forming an isolation structure in the trench includes depositing multiple layers of isolation material to form a multilayer isolation structure.

[0217] In some embodiments of the method, forming an isolation structure in a trench includes performing a deposition process to deposit an isolation material in the trench, and the method further includes controlling an etching process and a deposition process to form a selected air gap at a desired depth within the isolation structure.

[0218] In one embodiment, a method of manufacturing an integrated circuit device includes designing a layout of an integrated circuit including a device comprising a first gate structure and a second gate structure separated by an isolation structure; determining desired device performance conditions and / or desired process yield conditions; selecting a structure of the isolation structure to provide the desired device performance conditions, wherein the structure of the isolation structure includes a selected shape; and performing an integrated circuit manufacturing process including: forming a gate line over a semiconductor substrate; performing an etching process to remove a portion of the gate line and form a trench having a selected shape; and forming an isolation structure in the trench, wherein the isolation structure is selectively shaped as having no air gap, having a small air gap, or having a full air gap.

[0219] In some embodiments of the method, the selected shape is V-shaped; forming an isolation structure in the trench includes forming an air gap-free isolation structure.

[0220] In some embodiments of the method, the selected shape is spear-shaped; forming an isolation structure in the trench includes forming an isolation structure with small air gaps.

[0221] In some embodiments of the method, the selected shape is carrot-shaped; forming an isolation structure in the trench includes forming an isolation structure with a full air gap.

[0222] In some embodiments of the method, the selected shape is carrot-shaped; forming an isolation structure in the trench includes forming an isolation structure with a full air gap.

[0223] In some embodiments of the method, forming an isolation structure in the trench includes depositing multiple layers of isolation material to form a multilayer isolation structure.

[0224] In some embodiments of the method, the structure of the isolation structure includes an air gap at a selected depth within the isolation structure; forming the isolation structure in the trench includes forming an isolation structure with a small air gap or a full air gap at the selected depth.

[0225] In another embodiment, a method includes determining the desired performance of an isolation structure based on the shape of the isolation structure and a selected size and a selected depth of the air gap therein; etching gate lines to form trenches that separate the gate lines into a first gate structure and a second gate structure; and forming an isolation structure in the trenches, wherein the isolation structure has an isolation structure shape and an air gap having a selected size and located at a selected depth.

[0226] In some embodiments of the method, etching the gate lines to form trenches includes forming V-shaped trenches, spear-shaped trenches, or carrot-shaped trenches.

[0227] In some embodiments of the method, the gate line is a dummy gate line, the first gate structure is a first dummy gate structure, and the second gate structure is a second dummy gate structure. The method further includes, after forming an isolation structure in a trench, removing the first dummy gate structure to form a first gate cavity; and forming a first metal gate structure in the first gate cavity and adjacent to the isolation structure.

[0228] In some embodiments of the method, the gate line is a metal gate line, the first gate structure is a first dummy gate structure, the second gate structure is a second dummy gate structure, and the method further includes forming a dummy gate line over a semiconductor substrate; forming an interlayer dielectric adjacent to the dummy gate line; removing the dummy gate line to form a gate cavity; and forming a metal gate line in the gate cavity before etching the gate line to form a trench.

[0229] In another embodiment, an integrated circuit device includes a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and includes an air gap having a selected size.

[0230] In some embodiments of the integrated circuit, the selected shape is spear-shaped and the selected size is a small air gap.

[0231] In some embodiments of the integrated circuit, the selected shape is carrot-shaped and the selected size is full air gap.

[0232] In some embodiments of the integrated circuit, the isolation structure has a total depth, while the air gap has a height that is at least half of the total depth.

[0233] In another embodiment, an integrated circuit device includes: a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and is substantially free of air gaps.

[0234] In some embodiments of the integrated circuit, the selected shape is V-shaped.

[0235] In some embodiments of integrated circuits, the isolation structure is formed with seams.

[0236] In some embodiments of the integrated circuit, the isolation structure that is not substantially formed with an air gap has a total air content of less than 2% by volume.

[0237] In another embodiment, an integrated circuit device includes: a semiconductor substrate; a first gate structure and a second gate structure located above the semiconductor substrate and aligned in a straight line; and an isolation structure located between and separating the first gate structure and the second gate structure, wherein the isolation structure has an air gap, wherein the isolation structure has a total depth, and wherein the air gap has a height of at least half of the total depth.

[0238] In some embodiments of the integrated circuit, the air gap has a height of 0.6 to 0.9 times the total depth.

[0239] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized in that, Include: A semiconductor substrate; A first gate structure and a second gate structure are located above the semiconductor substrate and aligned in a straight line; and An isolation structure is located between and separates the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and includes an air gap having a selected size.

2. The integrated circuit device as claimed in claim 1, characterized in that, The selected shape is a spear shape, and the selected size is a small air gap.

3. The integrated circuit device as claimed in claim 1, characterized in that, The selected shape is a carrot shape, and the selected size is a full air gap.

4. The integrated circuit device as claimed in claim 1, characterized in that, The isolation structure has a total depth, and the air gap has a height that is at least half of the total depth.

5. An integrated circuit device, characterized in that, Include: A semiconductor substrate; A first gate structure and a second gate structure are located above the semiconductor substrate and aligned in a straight line; and An isolation structure is located between and separates the first gate structure and the second gate structure, wherein the isolation structure has a selected shape and substantially does not form an air gap.

6. The integrated circuit device as claimed in claim 5, characterized in that, The selected shape is a V-shape.

7. The integrated circuit device as claimed in claim 5, characterized in that, The isolation structure has a seam.

8. The integrated circuit device as claimed in claim 5, characterized in that, The isolation structure, which does not actually have the air gap, has a total air content of less than 2% of its volume.

9. An integrated circuit device, characterized in that, Include: A semiconductor substrate; A first gate structure and a second gate structure are located above the semiconductor substrate and aligned in a straight line; and An isolation structure is located between and separates the first gate structure and the second gate structure, wherein the isolation structure has an air gap, wherein the isolation structure has a total depth, and wherein the air gap has a height that is at least half of the total depth.

10. The integrated circuit device as claimed in claim 9, characterized in that, The air gap has a height that is 0.6 to 0.9 times the total depth.

Images