Device

Abstract

The present disclosure relates to an apparatus. The semiconductor chip is covered by a non-LDS encapsulation material (i.e., an encapsulation material that does not include an LDS-activatable additive). One or more first vias are opened through the non-LDS encapsulation material toward the semiconductor chip. An LDS encapsulation material (i.e., an encapsulation material including an LDS-activatable additive) is molded on the non-LDS encapsulation material to fill the first via. One or more second vias aligned with the first vias are opened through the LDS encapsulation material toward the semiconductor chip. The second via has a liner of LDS encapsulation material. An electrical coupling formation for the semiconductor chip is provided via a laser direct structuring process of the LDS encapsulation material including a liner in the second via.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102023000020505, filed on October 4, 2023, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The instruction manual pertains to the manufacture of semiconductor devices.

[0004] One or more embodiments can be applied, for example, to a microelectromechanical system (MEMS) thermocouple generator including a fragile suspended membrane on a sealed cavity. Background Technology

[0005] Examples of possible applications of laser direct forming (LDS) technology in the manufacture of integrated circuit (IC) semiconductor devices are cited in U.S. Patent Application Publications No. 2021 / 0305191 and No. 2023 / 035470, which are incorporated herein by reference.

[0006] Laser direct forming (LDS), often referred to as direct copper interconnect (DCI), is a technique based on forming plastic material using a laser source. The laser-processed traces are then coated with a conductive material to provide a conductive pattern.

[0007] Laser-induced strip interconnect (LISI) is another name sometimes used for this technology.

[0008] At STMicroelectronics' LISIPACK TM In the product line, LDS molding compound is used to cover (encapsulate) the die, and electrical conductive lines (vias, traces) are "molded" in the LDS molding compound.

[0009] In some specific applications, there may already be non-LDS coatings (strips, molded films, thick passivation, etc.) that are inherently incompatible with the LDS processing flow because that layer does not contain any LDS additives.

[0010] There is a need in this field to contribute to solving the above problems. Utility Model Content

[0011] One or more embodiments relate to methods.

[0012] One or more embodiments relate to corresponding (integrated circuit, IC) semiconductor devices.

[0013] In one embodiment, the method includes: opening a via (path) in a first non-LDS layer facing a metal (e.g., copper) pad in the die, for example via laser drilling; filling the opened via (path) in the non-LDS layer with an LDS molding compound (thus also closing the die package); reopening the via (path) opened during the first step and then filled with the LDS molding compound, such that the via is lined with LDS material; and applying standard LDS (e.g., LISIPACK). TM The process is applied to LDS materials to provide connection formations such as vias on leads and traces.

[0014] In one embodiment, a method includes:

[0015] A semiconductor chip is provided, the semiconductor chip being covered by a first encapsulation material;

[0016] The first packaging material does not include laser direct forming (LDS) additives;

[0017] Open a first pathway through the first encapsulation material to reach the conductive structure;

[0018] A second encapsulation material is molded onto the first encapsulation material, and the first passage is filled;

[0019] The second encapsulation material includes LDS additive;

[0020] A second passage is opened, which is aligned with the first passage, and the second passage passes through the second encapsulation material to reach the conductive structure;

[0021] The second passage has a liner made of the second encapsulating material; and

[0022] The second encapsulation material, including the liner of the second passage, is provided with electrical coupling to the conductive structure via laser direct forming.

[0023] According to one embodiment, opening the second passage includes applying laser beam energy, and wherein the liner is laser-shaped by the laser beam energy.

[0024] According to one embodiment, the second passage is narrower than the first passage.

[0025] According to one embodiment, opening the first path includes applying laser beam energy, and opening the second path includes applying laser beam energy.

[0026] According to one embodiment, the liner is laser-shaped by the energy of the laser beam.

[0027] According to one embodiment, applying laser beam energy to open the first path includes using a first laser beam, and applying laser beam energy to open the second path includes using a second laser beam, wherein the second laser beam is narrower than the first laser beam.

[0028] According to one embodiment, the first laser beam and the second laser beam have the same alignment and different focus adjustments.

[0029] According to one embodiment, the conductive structure is a conductive pad on the semiconductor chip.

[0030] According to one embodiment, wherein the second encapsulation material covers the lead frame, and the semiconductor chip is mounted to the lead frame, the method further includes:

[0031] Open a third passage through the second encapsulation material to reach the lead frame; and

[0032] Electrical coupling to the lead frame is provided by laser direct forming of the second encapsulation material.

[0033] According to one embodiment, providing electrical coupling for the semiconductor chip includes:

[0034] Laser activation of the second encapsulation material in the liner of the second pathway; and

[0035] An electrically conductive material is grown in a second passage of the liner having a second encapsulation material activated by laser, thereby forming an electrically coupled member therein for the semiconductor chip.

[0036] In one embodiment, an apparatus includes:

[0037] Semiconductor chips;

[0038] A first packaging material, wherein the first packaging material covers the semiconductor chip;

[0039] The first packaging material does not include laser direct forming (LDS) additives;

[0040] A first path extends toward the semiconductor chip within the first encapsulation material;

[0041] A second encapsulation material is molded on the first encapsulation material and exists within the first passage;

[0042] The second encapsulation material includes LDS additive;

[0043] A second passage, which is aligned with the first passage, extends through the second encapsulation material;

[0044] The second passage has a liner made of the second encapsulating material; and

[0045] Electrical coupling for the semiconductor chip, the electrical coupling being provided via a laser-directly shaped electrical conduction structure at the liner of the second path.

[0046] According to one embodiment, the semiconductor chip includes a pre-conducting pad covered by the first packaging material, wherein a first path extends toward the semiconductor chip and reaches the pre-conducting pad, and wherein a second path extends toward the semiconductor chip and reaches the pre-conducting pad.

[0047] According to one embodiment, the device further includes:

[0048] A lead frame to which the semiconductor chip is mounted;

[0049] The second encapsulation material covers the lead frame;

[0050] A third path, the third path extending through the second encapsulation material to the lead frame; and

[0051] Electrical coupling for the lead frame is provided via a laser-directly shaped electrical conduction structure at the third path.

[0052] According to one embodiment, the electrical coupling for the semiconductor chip includes:

[0053] A laser-activated second encapsulation material, the laser-activated second encapsulation material being contained within the liner of the second passage; and

[0054] An electrically conductive material, which is grown in the second pathway at the laser-activated second encapsulation material.

[0055] The solutions described herein can be advantageously applied, for example, to microelectromechanical systems (MEMS) thermocouple generators that include a fragile suspended membrane on a sealed cavity. Attached Figure Description

[0056] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein Figures 1 to 5 These are examples of possible sequences of steps in the process of manufacturing (integrated circuit, IC) semiconductor devices. Detailed Implementation

[0057] The corresponding numbers and symbols in different diagrams generally refer to the corresponding parts, unless otherwise indicated.

[0058] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments, and the drawings are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the feature's extent.

[0059] In the following description, various specific details are illustrated to provide a thorough understanding of the various examples of embodiments provided in accordance with the description. Embodiments may be obtained without one or more of the specific details described herein, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

[0060] References to "an embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a specific configuration, structure, or feature described in relation to an embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one embodiment" that may appear at various points in this specification do not necessarily refer exactly to one embodiment and the same embodiment. Furthermore, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0061] The headings / references used herein are provided for convenience only and therefore do not define the extent of protection or the scope of embodiments.

[0062] Recently, laser direct forming (LDS), often referred to as direct copper interconnect (DCI), has been added to the conventional schemes for providing interconnects in integrated circuit (IC) semiconductor devices, as illustrated in documents such as U.S. Patent Nos. 9,171,739 and 10,796,981 or U.S. Patent Application Publication No. 2016 / 0324009, all of which are incorporated herein by reference.

[0063] As discussed in the introductory section of this specification, LDS is a technique based on molding plastic materials using a laser source.

[0064] LDS is now widely used in various industries in the industrial and consumer electronics markets, such as for high-performance antenna integration, where antenna designs can be directly formed on molded plastic parts.

[0065] In an exemplary process, the molded part can be produced using a commercially available insulating resin that includes additives suitable for LDS processing; currently widely available resins (such as polymer resins like PC, PC / ABS, ABS, LCP) and LDS additives (such as copper-based additives, copper-chromite seed-forming additives) can be used for that purpose.

[0066] A laser beam can be used to transfer (“shape” or “activate”) a desired electrical conduction pattern onto an LDS molding compound, which can then undergo metallization to ultimately determine the desired conduction pattern.

[0067] Metallization can involve electroless plating followed by electrolytic plating. Electroless plating, also known as chemical plating, is a type of industrial chemical process that produces a metal coating on various materials through the autocatalytic chemical reduction of metal cations in a liquid bath. In electrolytic plating, the electric field between the anode and the workpiece, which acts as the cathode, forces positively charged metal ions to move to the cathode, where they relinquish their charge and deposit themselves as metal onto the surface of the workpiece.

[0068] LDS can be applied to IC package series in which conventional wire bonding is replaced by copper-plated vias and wires (traces).

[0069] Referring to U.S. Patent Application Publications Nos. 2021 / 0305191, 2023 / 0035470, 2018 / 0342453, 2019 / 0115287, 2020 / 0203264, 2020 / 0321274, 2021 / 0050226, 2021 / 0050299, 2021 / 0183748, or 2021 / 0305203A1 (all incorporated herein by reference), these are possible examples of the application of LDS technology in the manufacture of semiconductor devices.

[0070] For example, LDS technology helps replace leads, clips, or strips with wires / vias created by processing the LDS material with a laser beam and then metallizing it (e.g., growing a metal such as copper via a plating process).

[0071] Electrically conductive couplings can be provided in the LDS material (e.g., once cured via thermosetting): such as molded vias (TMVs) extending through the LDS package between the top (front) surface of the LDS package and the corresponding leads in the electrically conductive pads and / or lead frames on the front or top surface of the chip or die; and such electrically conductive lines or traces extending at the electrically coupled molded vias and the front or top surface of the LDS package to provide the desired electrical connection (routing) pattern.

[0072] Electrical components (such as passive components like resistors) may be arranged along one or more lines or traces.

[0073] Providing such electrically conductive formings using LDS materials essentially involves: (e.g., by laser drilling) forming these formings in the LDS material at desired locations; and growing an electrically conductive material (e.g., a metal such as copper) at previously formed (activated) locations.

[0074] The associated back-end manufacturing can therefore involve a combination of laser processing, molding, and plating steps in a dedicated assembly using LDS molding compounds for covering and encapsulating the die.

[0075] Certain specific applications may involve specific non-LDS coatings, strips, molded films, thick passivations, etc., which are already present on semiconductor chips or dies: this could be, for example, the case of a microelectromechanical system (MEMS) thermocouple generator that includes a fragile suspended film on a sealed cavity.

[0076] In these applications, the protective layer may already exist as a thin layer of protective material that does not contain LDS additives that can be activated by laser and therefore cannot be plated with metal (e.g., copper) after laser drilling as specified in a conventional LDS processing procedure.

[0077] In other words, these applications appear to be inherently incompatible with LDS processing because the encapsulation layer does not contain any LDS additives that can be activated (shaped) and plated with electrically conductive materials such as copper.

[0078] The solution described in this article helps to apply LDS processing to these applications by “converting” other products that are incompatible with LDS processing to products that can apply LDS processing to them.

[0079] This may involve a dual-drilling method using a "binder" metal (e.g., Cu) deposition to integrate non-LDS layers into the LDS process (e.g., LISIPACK). TM ).

[0080] In the solution described herein, a (continuous) patch can be provided between the leadframe and the die pad, which can be plated (with copper) by forming one or more openings filled with LDS molding compound (in which "platerable" vias are formed) in a first non-LDS protective layer.

[0081] Figures 1 to 5 These are examples of possible sequences of steps in the process of manufacturing (integrated circuit, IC) semiconductor devices.

[0082] in addition, Figures 1 to 5 The sequence of steps is merely exemplary, to some extent: Figures 1 to 5 One or more steps shown in the diagram may be omitted, performed in a different manner (e.g., with other tools), and / or replaced by other steps; and / or additional steps may be added.

[0083] The fabrication of the integrated circuit (IC) semiconductor device 10 is shown Figures 1 to 5 An exemplary sequence of steps, the integrated circuit (IC) semiconductor device 10 includes a lead frame 12 having one or more (integrated circuit) chips or dies 14 attached to one or more die pads 12A in the lead frame 12, wherein electrically conductive leads 12B are wound around the die pads 12A, the die pads 12A having dies / multiple dies 14 mounted thereon, wherein metal (e.g., copper) pads 14A are provided at the front or top surface of the chip 14.

[0084] The term "lead frame" is currently used (see, for example, the USPC Uniform Terminology) to indicate a metal frame and electrical leads (here, 12B) that provide support for a semiconductor chip or die (here, 14) (here, 12A) and that the electrical leads are used to couple the semiconductor chip or die to other electrical components or contacts.

[0085] Essentially, the leadframe comprises an array of electrically conductive formations (such as leads 12B) extending inward from a peripheral location in the direction of the semiconductor chip or die 14, thus forming an array of electrically conductive formations originating from a die pad 12A configured to have at least one semiconductor chip or die attached thereto. This can be via a die attachment adhesive (e.g., die attachment film (DAF)).

[0086] For simplicity, the accompanying drawings show a single chip or die 14 mounted on a single die pad 12A and a single lead 12B; as used herein, the terms chip (one or more) and die / multiple dies are considered synonyms.

[0087] As Figures 1 to 5The starting point of the exemplary sequence, the "intermediate" product is considered to be, in response to (other conventional) manufacturing steps, a die 14 mounted on a die pad 12A in the lead frame 12, wherein a protective package 16 has been (already) molded on the die 14.

[0088] As shown in the figure, chip 14 includes electrically conductive pads 14A on its front or top surface.

[0089] Package 16 includes non-LDS coating, strip, molded film, thick passivation, etc., which already exist on the semiconductor chip or die.

[0090] Such non-LDS encapsulation material 16 (e.g., epoxy resin) is easily identifiable and therefore distinguishable from LDS encapsulation material because the non-LDS encapsulation material 16 is essentially free from LDS additives such as copper-based additives and copper-chromite nucleating additives.

[0091] More generally, such non-LDS encapsulation materials are easily identifiable because they cannot be activated (shaped) and plated with metals such as copper due to the lack (or low content) of LDS activating additives.

[0092] Packages 16 made of non-LDS materials covering the chip or die 14, 14A may have been provided for various reasons, which are not the focus of this discussion. By way of example, this could be the case of a microelectromechanical system (MEMS) thermocouple generator that includes a fragile suspended membrane on a sealed cavity.

[0093] Figure 1 The (other conventional) structure of the product illustrated in the middle is therefore an example of an application in which the (first) package 16 may already exist (as a thin layer of protective material), which does not contain LDS additives and therefore cannot be plated with metal (e.g., copper) after laser drilling as specified in a conventional LDS processing flow.

[0094] Figure 2 Yes Figure 1 The image shows an example of a product performing the first drilling step.

[0095] The purpose of this first drilling step (which can be performed via laser beam energy LB1, as is common in other art) is to open (“drill”) the non-LDS package layer 16 and form one or more (first) passages 18 (also referred to as “openings” for simplicity) extending from the front surface of the package 16 (opposite to the lead frame 12) toward the front or top surface of the chip 14 (i.e., toward the pad 14A in the example illustrated here).

[0096] Figure 2 The drilling step thus results in the "opening" of the protective layer 16 by forming one or more openings 18 therein (for simplicity and ease of explanation, a single opening, which is essentially a hole, is shown).

[0097] Advantageously, these first paths 18 are opened through the non-LDS package 16 to the extent that they are as close as possible to the total actual metal pad area on the chip 14 (as indicated here by pad 14A).

[0098] Figure 3 It is molded in Figure 2 An example of a (second) package 20 of LDS material (of any type known to those skilled in the art) on a component.

[0099] The fact that package 20 is made of LDS material means that, unlike the non-LDS package 16, package 20 contains LDS-activated additives (copper-based additives, copper-chromite nucleating additives, which may again be indicated by way of example).

[0100] Due to the presence of LDS activator additives, as specified in the conventional LDS processing flow, the LDS package 20 can be activated (shaped) and plated with a metal such as copper after laser drilling.

[0101] Figure 3 The molding process (as discussed below), this process is as follows Figure 2 and Figure 4 (The drilling process is performed between the two drilling steps shown in the diagram) This results in the LDS molding compound 20 being filled into the opening (passage) 18 in the non-LDS layer 16.

[0102] The LDS molding compound 20 (which can be molded using any molding technique known to those skilled in the art for that purpose) thus closes the encapsulation and fills the opening 18 previously opened in the non-LDS layer 16.

[0103] Figure 4 Yes Figure 3 The image shows an example of a product undergoing a second drilling step.

[0104] Figure 4 The second drilling step has the purpose of (partially) reopening the same passage 18, which is in Figure 2 The step is turned on during (in non-LDS layer 16), and then in Figure 3 During the molding step, LDS material 20 is filled into the passage 18 (suitable for plating within the framework of LDS treatment). This second drilling step forms a (second) passage 18' through the LDS material 20 (also referred to as an "opening" for simplicity).

[0105] Applied to Figure 4 The wording of the second drilling step "partially" highlights the fact that opening 18' is narrower (smaller radially) than opening 18, which is in Figure 4 During the second drilling step, the opening 18 is (re)opened in the LDS material 20, and this opening is in Figure 2 It is formed in non-LDS material during the first drilling step.

[0106] In that way, Figure 4 The openings 18' that are (re)opened during the second drilling step have their inner wall liners (as indicated by reference numeral 20) containing LDS material 20, which in turn contains LDS additives. Figure 3 It is molded during the molding process.

[0107] In summary, in the methods described herein:

[0108] One or more pathways 18 are opened in the non-LDS packaging material 16 (e.g., via laser beam LB1) toward the semiconductor chip or multiple chips 14, 14A: the exemplary semiconductor chip illustrated includes an electrically conductive front pad 14A, which is covered (encapsulated) by the non-LDS packaging material 16. Figure 2 Visible in the image, for example (e.g., via laser beam drilling LB1), is a passage 18 that faces and descends to the electrical conduction front pad 14A;

[0109] LDS packaging material 20 (i.e., material including LDS-activated additives) is molded onto one or more semiconductor chips 14, 14A covered by non-LDS packaging material 16, which has one or more open passages 18 leading to the semiconductor chips 14, 14A. In that manner, as... Figure 3 As illustrated in the diagram, LDS encapsulation material 20, including LDS-activated additives, is filled into one or more channels 18 facing the semiconductor chips 14, 14B; and

[0110] One or more passages 18 leading to semiconductor chips 14, 14A and filled with LDS packaging material (20) are partially reopened (e.g., via laser beam LB2: see Figure 4 (The path is indicated as 18'), and thus exhibits an inner liner 200 of LDS packaging material.

[0111] Furthermore, reopening the passages toward the semiconductor chips 14, 14A with the LDS packaging material 20 filled therein involves forming one or more openings 18' in such LDS packaging material 20, which are larger than the passages 18' opened in non-LDS material 16 (such as...). Figure 2 The one shown in the middle is narrower (with a smaller diameter / section).

[0112] Advantageously, similar Figure 2 The drilling process can be performed using laser beam energy LB2. Figure 4 Another drilling step, as is common in other conventional methods in the art.

[0113] At least in principle, it can be executed in other ways. Figure 2 The first "opening" step involves forming a pathway using processes other than laser drilling: etching is an example of those other processes. The first opening of non-LDS materials can be achieved using different techniques because activation is not required in this case.

[0114] Figure 4 The second "opening" performed by laser drilling is advantageous because it also activates the LDS layer in the first opening ("well"): Figure 4 In the case of the steps, it is therefore advantageous to reopen the laser beam drilling of the passage 18', to some extent, the laser beam energy LB2 can achieve the purpose of reopening ("re-drilling") the passage 18' while activating the LDS material of the liner 200, without the need for different laser treatments to activate the LDS additives in the LDS material.

[0115] Although Figure 2 and Figure 4 Different reference numerals (i.e., LB1 and LB2) were used, but in Figure 4 The laser beam source used in the steps can be for Figure 2 The same laser beam source is used for the steps.

[0116] This indicates an advantageous option, to some extent, that the same alignment of the same laser source for chip 14 / pad 16 can be achieved using different focus adjustments (drilling sizes).

[0117] Even if the first drilling step is performed on a non-molded leadframe and the second drilling step is performed on a molded leadframe, the alignment references can be the same in both instances. For example, they can be "ovals" on the edges of the regions of the leadframe that are not reached by the molding compound.

[0118] Laser beam energy can be provided with a first beam LB1 during the opening of one or more passages 18 in the non-LDS encapsulation material 16, and with a second beam LB2 during the reopening of one or more passages 18' filled with LDS encapsulation material 20. Advantageously, the second beam LB2 is narrower than the first beam LB1, such that the reopened passages 18' are narrower than the passages 18 opened in the non-LDS encapsulation material 16 to form the liner 200.

[0119] As in standard LDS processing procedures, it can be processed (e.g., by electroless / electrolytic plating) (e.g., through...) Figure 4 The laser beam (LB2) "activates" the liner 200 of the LDS material during the second drilling step of the drilling process.

[0120] deal with Figure 2 and Figure 4 The combination of two steps (with between them) Figure 3 The molding process (and therefore helps to produce similar products) Figure 1 The product shown in the middle is "recycled" for LDS processing; otherwise, it would appear unsuitable for LDS processing.

[0121] Figure 2 and Figure 4 The combination of two steps (with between them) Figure 3 The molding step helps to provide electrical coupling to semiconductor chips 14, 14A via direct laser forming, i.e., LDS treatment of LDS packaging material (i.e., packaging material including LDS-activating additives), when the semiconductor chip is (already) covered by non-LDS packaging material (i.e., packaging material that is not suitable for plating and is essentially free of LDS-activating additives).

[0122] For example (such as) Figure 5 (Example) can provide electrically conductive forming elements to electrically couple one or more semiconductor chips 14 to selected leads (outer pads) 12B in the lead frame 12.

[0123] like Figure 5 As illustrated, electrically coupled formations 221, 222, and 223 for semiconductor chips 14, 14A can be produced via direct laser forming, i.e., LDS treatment of LDS packaging material 20. This includes applying the LDS treatment to the liner 200 of the reopened passage(s) 18'.

[0124] like Figure 5 As illustrated in the diagram, these coupling elements may include:

[0125] The first molded through-hole (TMV) 221 includes a conductive material (such as copper) that is grown into the reopened via or via 18', which extends between the top (front) surface 20A of the LDS package material 20 and the electrically conductive pads 14A at the front or top surface of the chip or die 14.

[0126] The second molded through-hole (TMV) 222 includes a conductive material that grows into the (other) passage 180 and can interact with... Figure 4 The steps simultaneously form the passage 180 extending between the top (front) surface 20A of the LDS package 20 and the corresponding lead 12B in the lead frame 12; and

[0127] Electrically conductive lines or traces 223 include conductive material grown on the front or top surface 20A of the LDS package 20, electrically coupling a selected first via 221 in the first via 221 to a selected second via 222 in the second via 222, to provide a desired electrical connection (routing) pattern between the chip or die 14 and the lead 12B.

[0128] Providing electrically conductive forming elements 221, 222, and 223 essentially involves molding these forming elements (including the LDS “liner” 200 of the forming passage 18', such as...) in LDS material 20. Figure 4 As illustrated, the pathway 18' is partially reopened via laser beam energy, and an electrically conductive material (such as a metal like copper) is grown at the previously activated (formed) location.

[0129] For example, electrically coupled forming elements (such as molded vias TMV221) for semiconductor chips 14, 14A can be formed by laser activation (see...). Figure 4 The figure shows LDS encapsulation material (LB2) in the liner 200 of the reopened passage 18'; and electrically conductive material (e.g., electroless and electrolytic copper) grown in the reopened passage 18', which has LDS additives activated (shaped) by laser beam energy in the liner 200 of the LDS encapsulation material.

[0130] The relevant LDS processing can be along the solution line illustrated in the patent reference cited at the beginning of this specification.

[0131] Without prejudice to the fundamental principles, the details and embodiments may vary, even significantly, relative to the details and embodiments described above by way of example only, without departing from the scope of protection.

[0132] The claims are an integral part of the technical teachings of the embodiments provided herein. The scope of protection is defined by the appended claims.

Claims

1. An apparatus, characterized in that, The device includes: Semiconductor chips; A first packaging material, wherein the first packaging material covers the semiconductor chip; The first packaging material does not include laser direct forming (LDS) additives; A first pathway extends toward the semiconductor chip within the first encapsulation material; A second encapsulation material is molded on the first encapsulation material and exists within the first passage; The second encapsulation material includes LDS additive; A second passage, which is aligned with the first passage, extends through the second encapsulation material; The second passage has a liner made of the second encapsulating material; and Electrical coupling for the semiconductor chip, the electrical coupling being provided via a laser-directly shaped electrical conduction structure at the liner of the second path.

2. The apparatus according to claim 1, characterized in that, The semiconductor chip includes an electrical conduction front pad covered by the first packaging material, wherein a first path extends toward the semiconductor chip and reaches the electrical conduction front pad, and wherein a second path extends toward the semiconductor chip and reaches the electrical conduction front pad.

3. The apparatus according to claim 1, characterized in that, The device further includes: A lead frame to which the semiconductor chip is mounted; The second encapsulation material covers the lead frame; A third path, the third path extending through the second encapsulation material to the lead frame; and Electrical coupling for the lead frame is provided via a laser-directly shaped electrical conduction structure at the third path.

4. The apparatus according to claim 1, characterized in that, Electrical coupling for the semiconductor chip includes: A laser-activated second encapsulation material, wherein the laser-activated second encapsulation material is located within the liner of the second passage; and An electrically conductive material, which is grown in the second pathway at the laser-activated second encapsulation material.

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