BIOS detection circuit and terminal equipment

Abstract

The utility model relates to the technical field of firmware and embedded systems, and discloses a BIOS (Basic Input / Output System) detection circuit and terminal equipment, the BIOS detection circuit comprises a central processing unit module, a signal switching chip module, a signal switching button module, a first BIOS memory module and a second BIOS memory module; when the system does not detect that the BIOS data is damaged, the signal switching chip module outputs a first chip selection signal to the first BIOS memory module; when the system detects that BIOS data is damaged, the signal switching button module outputs a first control signal to the signal switching chip module, and the signal switching chip module receives the first control signal and outputs a second chip selection signal to the second BIOS memory module. On the basis, through the double-BIOS design and the signal switching mechanism, the main BIOS or the auxiliary BIOS is used for starting the system under different conditions, so that the problem of data damage of the BIOS is effectively solved, and the stability and the safety of the system are improved.

Description

Technical Field

[0001] This utility model relates to the fields of firmware technology and embedded system technology, and in particular to BIOS detection circuits and terminal devices. Background Technology

[0002] With the continuous development of computer technology, the BIOS (Basic Input / Output System), as a core component for computer startup and hardware initialization, plays a crucial role. To ensure the system can recover and boot normally in the event of BIOS corruption, many motherboard designs incorporate a BIOS ROM backup mechanism. Typically, engineers save a backup copy in a specific area of ​​the BIOS ROM and perform an integrity check during system startup. If corrupted or abnormal BIOS data is detected, it can be recovered by calling the data from the backup area, ensuring that terminal devices (e.g., laptops or desktops) can boot successfully. However, existing BIOS detection methods fail to cover all potential BIOS corruption scenarios in certain special situations, resulting in ineffective recovery. In such cases, the terminal device may fail to boot normally, potentially causing inconvenience to users. Therefore, improving the reliability of BIOS detection and recovery mechanisms to ensure successful BIOS data recovery under any circumstances has become a major challenge for BIOS engineers. Utility Model Content

[0003] In view of the above problems, the present invention mainly solves the technical problem that terminal devices cannot be turned on normally due to BIOS data corruption.

[0004] To solve the above-mentioned technical problems, the present invention provides a BIOS detection circuit, comprising: a central processing unit (CPU) module, a signal switching chip module, a signal switching button module, a first BIOS memory module, and a second BIOS memory module. The signal switching chip module is connected to the CPU module, the signal switching button module, the first BIOS memory module, and the second BIOS memory module, respectively. The CPU module is also connected to the first BIOS memory module and the second BIOS memory module. When the system does not detect BIOS data corruption, the signal switching chip module outputs a first chip select signal to the first BIOS memory module. When the system detects BIOS data corruption, the signal switching button module outputs a first control signal to the signal switching chip module. The signal switching chip module receives the first control signal and outputs a second chip select signal to the second BIOS memory module.

[0005] In some embodiments, the central processing unit module includes an SPI chip select signal pin and a data transmission signal pin. The SPI chip select signal pin is connected to the signal switching chip module, and the data transmission signal pin is connected to the first BIOS memory module and the second BIOS memory module, respectively.

[0006] In some embodiments, the signal switching button module includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is used to output the first control signal to the signal switching chip module, and the second pin, the third pin, and the fourth pin are respectively grounded.

[0007] In some embodiments, the signal switching chip module includes a first VCC power supply, a first chip U1, a first capacitor C1, a first resistor R7, and a second resistor R8. The first chip U1 includes an EN pin, a VCC pin, a SIN pin, a SOUT1 pin, a GND pin, and a SCOUT2 pin. The first end of the second resistor R8 is connected to the first VCC power supply, and the second end of the second resistor R8 is connected to the VCC pin. The first end of the first capacitor C1 is connected to the second end of the second resistor R8 and the VCC pin, respectively, and the second end of the first capacitor C1 is grounded. The first end of the first resistor R7 is connected to the signal switching button module, and the second end of the first resistor R7 is connected to the EN pin. The SIN pin is connected to the SPI chip select signal pin, the SCOUT1 pin is connected to the first BIOS memory module, the SCOUT2 pin is connected to the second BIOS memory module, and the GND pin is grounded.

[0008] In some embodiments, the data transmission signal pins include a first data transmission pin, a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a fifth data transmission pin. The first BIOS memory module includes a first BIOS chip, a second capacitor C2, and a second VCC power supply. The first BIOS chip includes a first VSS pin, a first VDD pin, a first chip select pin, a first serial output pin, a second serial output pin, a third serial output pin, a fourth serial output pin, and a first serial clock pin. The first chip select pin is connected to the SCOUT1 pin. The first serial output pin is connected to the first data transmission pin. The second serial output pin is connected to the second data transmission pin. The third serial output pin is connected to the third data transmission pin. The fourth serial output pin is connected to the fourth data transmission pin. The first serial clock pin is connected to the fifth data transmission pin. The first VSS pin is grounded. The first end of the second capacitor C2 is grounded. The second end of the second capacitor C2 is connected to the first VDD pin and the second VCC power supply, respectively.

[0009] In some embodiments, the second BIOS memory module includes a second BIOS chip, a third capacitor C3, and a third VCC power supply. The second BIOS chip includes a second VSS pin, a second VDD pin, a second chip select pin, a fifth serial output pin, a sixth serial output pin, a seventh serial output pin, an eighth serial output pin, and a second serial clock pin. The second chip select pin is connected to the SCOUT2 pin. The fifth serial output pin is connected to the first data transmission pin. The sixth serial output pin is connected to the second data transmission pin. The seventh serial output pin is connected to the third data transmission pin. The eighth serial output pin is connected to the fourth data transmission pin. The second serial clock pin is connected to the fifth data transmission pin. The second VSS pin is grounded. The first end of the third capacitor C3 is grounded. The second end of the third capacitor C3 is connected to the second VDD pin and the third VCC power supply, respectively.

[0010] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is to provide a terminal device, wherein the terminal device is provided with the BIOS detection circuit described above.

[0011] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this utility model embodiment provides a BIOS detection circuit and terminal device. The BIOS detection circuit includes: a central processing unit module, a signal switching chip module, a signal switching button module, a first BIOS memory module, and a second BIOS memory module. The signal switching chip module is connected to the central processing unit module, the signal switching button module, the first BIOS memory module, and the second BIOS memory module, respectively. The central processing unit module is also connected to the first BIOS memory module and the second BIOS memory module. When the system does not detect BIOS data corruption, the signal switching chip module outputs a first chip select signal to the first BIOS memory module. When the system detects BIOS data corruption, the signal switching button module outputs a first control signal to the signal switching chip module. The signal switching chip module receives the first control signal and outputs a second chip select signal to the second BIOS memory module. Based on this, a dual BIOS design (main BIOS and secondary BIOS) and a signal switching mechanism are used to enable the system to boot using the main BIOS under normal circumstances. When the main BIOS data is corrupted, manual intervention is performed through the signal switching button module to switch to the secondary BIOS, ensuring that the system can boot normally. This further enhances the maintainability of the system, effectively addresses issues such as BIOS data corruption, and improves system stability and security. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0013] Figure 1 This is a schematic block diagram of a BIOS detection circuit provided in an embodiment of the present invention;

[0014] Figure 2 This is a circuit structure diagram of the signal switching button module provided in this embodiment of the utility model;

[0015] Figure 3 This is a circuit structure diagram of the signal switching chip module provided in this embodiment of the utility model;

[0016] Figure 4 This is a circuit structure diagram of the first BIOS memory module provided in this embodiment of the present invention;

[0017] Figure 5This is a circuit diagram of the second BIOS memory module provided in an embodiment of the present invention. Detailed Implementation

[0018] To facilitate understanding of this utility model, a more detailed description will be provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements between them.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention.

[0020] Please see Figure 1 , Figure 1 This is a schematic block diagram of a BIOS detection circuit provided in an embodiment of the present invention. The BIOS detection circuit 100 includes a central processing unit module 10, a signal switching chip module 20, a signal switching button module 30, a first BIOS memory module 40, and a second BIOS memory module 50. The signal switching chip module 20 is connected to the central processing unit module 10, the signal switching button module 30, the first BIOS memory module 40, and the second BIOS memory module 50, respectively. The central processing unit module 10 is also connected to the first BIOS memory module 40 and the second BIOS memory module 50.

[0021] In this embodiment, the Central Processing Unit (CPU) module 10 is the core component of the system, often referred to as the brain of the computer. It is the core unit responsible for executing instructions, performing calculations, and controlling other hardware modules. It includes key components such as the Arithmetic Logic Unit (ALU), Control Unit (CU), and registers, which work together to complete data processing and program execution. In the BIOS detection circuit 100, the CPU communicates with the BIOS memory and controls the system's boot process, enabling switching between the primary and secondary BIOS and fault recovery functions.

[0022] In some embodiments, the central processing unit module 10 includes an SPI chip select signal pin and a data transmission signal pin. The SPI chip select signal pin is connected to the signal switching chip module 20, and the data transmission signal pin is connected to the first BIOS memory module 40 and the second BIOS memory module 50, respectively.

[0023] Specifically, the central processing unit (CPU) module 10 communicates with external devices via the SPI (Serial Peripheral Interface) protocol, particularly for data exchange and control with the first BIOS memory module 40 and the second BIOS memory module 50. SPI is a full-duplex serial communication protocol primarily used for short-distance communication between devices, commonly found in microcontrollers, sensors, and storage devices. In this embodiment, the SPI chip select signal pin is SPI CS (Chip Select), used to select the slave device for communication. The CPU module 10 is connected to the signal switching chip module 20 via the SPI CS pin to control the CS signal and determine which BIOS memory is active. Data transmission signal pins include, but are not limited to: SPI CLK, MOSI, and MISO. Among these, SPI CLK (clock signal) is used for synchronous data transmission; that is, the clock signal is provided by the master device (CPU), and all data transmission and reading are synchronized based on this clock. MOSI (Master Out Slave In) is used to send data from the master device (CPU) to the slave device (BIOS memory). That is, the CPU sends data (such as read commands or write commands) to the master BIOS (first BIOS memory) or the slave BIOS (second BIOS memory) via the MOSI pin. MISO (Master In Slave Out) is used to output data from the slave device (BIOS memory) to the master device (CPU). That is, the BIOS memory transfers data (such as BIOS firmware data) to the CPU via the MISO pin.

[0024] The working principle of the central processing unit module 10 is as follows: The CPU first outputs an SPI CS signal to select the master BIOS or the slave BIOS. It provides a clock synchronization signal via SPI CLK. It sends a read command to the BIOS memory module via the MOSI pin. The BIOS memory module (first or second BIOS memory) returns the corresponding firmware data via MISO. After the CPU reads the firmware data, it begins executing the initialization program.

[0025] In this embodiment, the signal switching chip module 20 is a circuit responsible for switching the chip select signal (CS). It switches the BIOS chip select signals (CS0 and CS1) according to the input control signal, thereby selecting either the main BIOS or the secondary BIOS for operation. When there is no BIOS data corruption, the signal switching chip module 20 outputs the first chip select signal (CS0) to the main BIOS memory (first BIOS memory module 40), enabling the CPU to read data from the main BIOS memory. When BIOS data corruption occurs, it receives the first control signal (used to switch the first chip select signal to the second chip select signal) output by the signal switching button module 30 and outputs the second chip select signal (CS1), switching to the secondary BIOS memory module (second BIOS memory module 50), thus enabling the system to boot from the secondary BIOS memory.

[0026] In this embodiment, the signal switching button module 30 is a manual control unit that provides the user with a signal to switch to a backup solution when a BIOS fault is detected. When the system detects that the BIOS data is corrupted, the user can manually send a control signal by pressing the button, that is, output a first control signal to the signal switching chip module 20 to force the chip select signal to the secondary BIOS memory module.

[0027] In this embodiment, the first BIOS memory module 40 is the main memory during normal system operation, storing the system firmware (BIOS). Its functions include storing the system initialization program, hardware detection code, and data related to booting the operating system. During normal system operation, the CPU communicates with the main BIOS to read its data and complete the system boot process.

[0028] In this embodiment, the second BIOS memory module 50 serves as a secondary memory during normal system operation and provides recovery functionality when the main BIOS malfunctions. Its function is to store system firmware data similar to that of the main BIOS, ensuring system redundancy. When the main BIOS data is corrupted or fails to boot, the signal switching chip module 20 switches to the secondary BIOS, enabling the system to boot normally.

[0029] The working principle of the BIOS detection circuit 100 provided in this embodiment is as follows: Under normal conditions, when the system starts, the signal switching chip module 20 outputs the first chip select signal to the first BIOS memory module 40 (main BIOS) by default. The central processing unit module 10 communicates with the first BIOS memory module 40 to read firmware data from the first BIOS memory module 40 for hardware initialization and operating system booting. At this time, the system is working normally and there is no need to switch to the secondary BIOS. During system operation, the central processing unit module 10 will detect the data integrity of the main BIOS to determine whether data corruption has occurred. If the main BIOS data is normal, the system continues to run through the main BIOS memory. When main BIOS data corruption is detected, a first control signal can be sent to the signal switching chip module 20 through the signal switching button module 30. After receiving the first control signal sent by the button module, the signal switching chip module 20 stops outputting the first chip select signal and instead outputs the second chip select signal. At this time, the central processing unit module 10 communicates with the second BIOS memory module 50. Subsequently, the central processing unit module 10 reads the firmware data in the second BIOS memory module 50, reinitializes the hardware devices, and boots the operating system. At this point, the system resumes normal startup via the secondary BIOS, ensuring system reliability. It is understandable that the BIOS detection circuit 100, through its dual BIOS design (primary BIOS and secondary BIOS) and signal switching mechanism, effectively improves system reliability and fault tolerance. Its core workflow is as follows: Under normal circumstances, the system boots using the primary BIOS. If the primary BIOS data is corrupted, manual intervention via the signal switching button module 30 switches the signal switching chip module 20 to the secondary BIOS, ensuring normal system startup, further enhancing system maintainability, effectively addressing issues such as BIOS data corruption, and improving system stability and security.

[0030] The following is combined Figures 2 to 5 The circuit structure diagrams of each functional module provided further illustrate the BIOS detection circuit provided in this embodiment of the invention.

[0031] In some embodiments, the signal switching button module 30 includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is used to output a first control signal to the signal switching chip module 20, and the second, third, and fourth pins are grounded respectively.

[0032] It is understood that in this embodiment, the signal switching button module 30 is a push-button switch (JSW1), model number TSVB-21L, which is typically used as a switch button in a circuit. The first pin outputs a first control signal (BIOS_CS_SEL), used to switch the BIOS ROM or related storage devices (such as the main BIOS or the secondary BIOS).

[0033] In some embodiments, the signal switching chip module 20 includes a first VCC power supply, a first chip U1, a first capacitor C1, a first resistor R7, and a second resistor R8. The first chip U1 includes an EN pin, a VCC pin, a SIN pin, a SOUT1 pin, a GND pin, and a SCOUT2 pin. The first end of the second resistor R8 is connected to the first VCC power supply, and the second end of the second resistor R8 is connected to the VCC pin. The first end of the first capacitor C1 is connected to the second end of the second resistor R8 and the VCC pin, respectively. The second end of the first capacitor C1 is grounded. The first end of the first resistor R7 is connected to the signal switching button module 30, and the second end of the first resistor R7 is connected to the EN pin. The SIN pin is connected to the SPI chip select signal pin. The SCOUT1 pin is connected to the first BIOS memory module 40, the SCOUT2 pin is connected to the second BIOS memory module 50, and the GND pin is grounded.

[0034] It is understood that in this embodiment, the signal switching chip module 20 is a CS switching chip circuit. Specifically, the first chip U1 is the first integrated circuit (IC) component on the circuit board, referring to an integrated circuit chip with the model number RS2057XC6, or a multiplexer or similar chip used to switch Chip Select signals. EN is the function pin that enables the chip. A high or low level (depending on the chip design) will activate the chip. Its connection is as follows: connected to the BIOS_CS_SEL signal via resistor R7. BIOS_CS_SEL: used to control whether the chip is activated. If the signal is pulled high (assuming the chip is in positive logic), the chip is enabled and begins to perform CS signal switching operations. Resistor R7 is a current-limiting resistor with an R0402 package, a resistance accuracy class of 1%, and a rated power of 1 / 16W, used to protect the EN pin or adjust the signal strength. The VCC pin provides power to the chip. Its connection is as follows: connected to the VCC power supply via resistor R8, forming a power decoupling circuit with capacitor C1, serving as a filter. Among them, capacitor C1 has a C0402 package, a capacitance of 1 microfarad, a rated voltage of 6.3V, and an X5R dielectric material. The SIN pin is the input pin for the CS signal. Its connection method is: connected to the FT_QSPI_CSN0 signal. FT_QSPI_CSN0 is the CS signal output by the central processing unit module 10 (CPU) through the SPI chip select signal pin, used to select the slave device. The SOUT1 pin is the output pin of the first CS signal, which selects the first BIOS memory module 40 by outputting the QSP1_CSN0 signal (first chip select signal CS0). The SOUT2 pin is the output pin of the second CS signal, which selects the second BIOS memory module 50 by outputting the QSP1_CSN1 signal (second chip select signal CS1).

[0035] The working principle of the signal switching chip module 20 is as follows: Chip initialization: The first VCC power supply powers the chip, and C1 ensures stable power supply. The BIOS_CS_SEL signal controls the EN pin; the chip is activated when the first VCC power supply is applied. Signal input and processing: The central processing unit module 10 sends the CS signal to the chip's SIN pin via FT_QSPI_CSN0. Internally, the chip routes the input signal from the SIN pin to either the SOUT1 or SOUT2 output pin according to its logic design. Signal output: When the chip's EN pin is high: the internal switching logic selects the primary BIOS memory and transmits the QSP1_CSN0 signal through the SOUT1 pin, thereby activating the primary BIOS memory. When the chip's EN pin is low: the internal switching logic selects the secondary BIOS memory and transmits the QSP1_CSN1 signal through the SOUT2 pin, thereby activating the secondary BIOS memory. Switching mechanism: The BIOS_CS_SEL signal controls the chip switching via EN. According to the control logic, the input CS signal (SIN) is switched to the two output terminals (SOUT1 or SOUT2), thereby achieving the switching between the primary BIOS and the backup BIOS. Understandably, the signal switching chip module 20 controls the selection between the main BIOS (QSP1_CSN0) and the secondary BIOS (QSP1_CSN1) based on the BIOS_CS_SEL signal. Through the control of the EN signal, combined with the transmission of the input signal (SIN), the chip achieves dynamic switching between the main BIOS and the secondary BIOS. Resistors and capacitors primarily serve to limit current and decouple the signal, ensuring stable operation of the chip during signal switching and preventing noise or current surges from interfering with normal function.

[0036] In some embodiments, the data transmission signal pins include a first data transmission pin, a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a fifth data transmission pin. The first BIOS memory module 40 includes a first BIOS chip, a second capacitor C2, and a second VCC power supply. The first BIOS chip includes a first VSS pin, a first VDD pin, a first chip select pin, a first serial output pin, a second serial output pin, a third serial output pin, a fourth serial output pin, and a first serial clock pin. The first chip select pin is connected to the SCOUT1 pin, the first serial output pin is connected to the first data transmission pin, the second serial output pin is connected to the second data transmission pin, the third serial output pin is connected to the third data transmission pin, the fourth serial output pin is connected to the fourth data transmission pin, the first serial clock pin is connected to the fifth data transmission pin, the first VSS pin is grounded, the first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is connected to the first VDD pin and the second VCC power supply, respectively.

[0037] It is understood that in this embodiment, the first BIOS chip of the first BIOS memory module 40 is an SPI flash memory chip used to store system firmware, typically used to store the system's BIOS or UEFI program. W25Q128JWSIQ is the model number. SMT is a modern electronic component mounting method. It refers to assembling the circuit by directly mounting electronic components onto the surface of the circuit board, rather than the traditional method of inserting pins into holes in the circuit board. The first chip select pin is the CS# (Chip Select) pin, which receives the QSPI_CSN0 signal transmitted by the SCOUT1 pin of the chip module 20 to activate the main BIOS memory, allowing the central processing unit module 10 to communicate with it. The first serial output pin is the SO / IO1 (Serial Output / Data I / O1) pin: in traditional SPI mode, as a serial output pin, the main BIOS memory sends data to the central processing unit module 10 through this pin. In QSPI mode, QSPI is an enhanced SPI communication protocol. Compared to the traditional SPI interface, it uses four data lines (IO0, IO1, IO2, and IO3) for data transmission, which can significantly improve data transmission speed. It is understandable that the first BIOS memory module 40 supports data transmission in both SPI and QSPI modes. Taking QSPI mode as an example, the first serial output pin is IO1, and the first data transmission pin is FT_QSPI_IO1. The second serial output pin is IO2, and the second data transmission pin is FT_QSPI_IO2. The third serial output pin is IO3, and the third data transmission pin is FT_QSPI_IO3. The fourth serial output pin is IO0, and the fourth data transmission pin is FT_QSPI_IO0. The first serial clock pin is SCK, and the fifth data transmission pin is FT_QSPI_SCK. In SPI mode, SO is used as a serial output pin, through which data is sent to the central processing unit module 10. WP is a write-protect pin, which disables write operations when low. RST# is a chip reset pin, which resets the BIOS memory when low. SI is used as a serial input pin, through which the central processing unit module 10 sends data to the main BIOS memory. The first VSS pin is the power supply reference ground, used to provide a stable voltage reference. The first terminal of the second capacitor C2 is grounded, and the second terminal of the second capacitor C2 is connected to the first VDD pin and the second VCC power supply, respectively, thereby supplying power to the first BIOS chip and ensuring stable power supply.

[0038] Understandably, the first BIOS memory module 40 is a crucial memory for motherboard startup, providing system boot code and hardware initialization configuration. It communicates with the central processing unit module 10 via SPI or QSPI interfaces, supporting fast read and write operations. Write protection (WP) and reset (RST#) functions enhance system reliability and anti-interference capabilities. Multiple data lines (QSPI mode) significantly improve data transfer rates, supporting complex systems. The eight pins of the main BIOS ROM provide rich functionality and flexibility to support SPI and QSPI communication modes, ensuring reliable firmware loading and execution. Its functions, such as CS control, data transfer, write protection, and reset mechanisms, constitute a vital part of the system startup process, while flexible configuration of I / O pins enables efficient communication and data protection.

[0039] In some embodiments, the second BIOS memory module 50 includes a second BIOS chip, a third capacitor C3, and a third VCC power supply. The second BIOS chip includes a second VSS pin, a second VDD pin, a second chip select pin, a fifth serial output pin, a sixth serial output pin, a seventh serial output pin, an eighth serial output pin, and a second serial clock pin. The second chip select pin is connected to the SCOUT2 pin, the fifth serial output pin is connected to the first data transmission pin, the sixth serial output pin is connected to the second data transmission pin, the seventh serial output pin is connected to the third data transmission pin, the eighth serial output pin is connected to the fourth data transmission pin, the second serial clock pin is connected to the fifth data transmission pin, the second VSS pin is grounded, the first end of the third capacitor C3 is grounded, and the second end of the third capacitor C3 is connected to the second VDD pin and the third VCC power supply, respectively.

[0040] It should be noted that the circuit structure of the second BIOS memory module 50 used in this embodiment is the same as that of the first BIOS memory module 40. The only difference is that the second chip select pin (CS#) of the second BIOS memory module 50 receives the QSPI_CSN1 signal. The other pins and their connection methods are the same as those of the first BIOS memory module 40. For details, please refer to the above description of the first BIOS memory module 40, which will not be repeated here.

[0041] In addition, in this embodiment, the first VCC power supply, the second VCC power supply and the third VCC power supply mentioned above all support two voltages (e.g., 3.3V and 1.8V), which can be selected according to the actual application.

[0042] It should be noted that the BIOS detection circuit 100 provided in this embodiment firstly sets up a main BIOS ROM (first BIOS memory module) and a secondary BIOS ROM (second BIOS memory module), and introduces an external button (signal switching button module) to switch the BIOS boot source. This circuit ensures that the system can still boot even if the main BIOS malfunctions. Whether the BIOS data corruption is caused by a network attack or abnormal operation, the system can restart from the secondary BIOS ROM, thus avoiding boot problems caused by BIOS corruption. Secondly, this circuit design solves the problem of abnormal BIOS data. Through the signal switching chip module, the BIOS source can be switched according to the detected BIOS data corruption, ensuring that the system always boots from normal BIOS data. The use of an external button to control the switching provides a simple and direct switching method when the system malfunctions, thereby enhancing the system's stability and reliability. Finally, this circuit design overcomes technical challenges such as circuit layout, signal interference, and frequency requirements. The correctness of the SPI data transmission signal is crucial. Through a reasonable circuit layout and the high-bandwidth design of the signal switching chip, distortion and interference of the SPI signal are avoided, ensuring stable system operation. Especially with increasingly higher SPI frequencies, selecting a suitable CS switching chip avoids CS signal distortion, ensuring accurate SPI data transmission. Understandably, the BIOS detection circuit 100 not only prevents system boot failure due to BIOS data corruption, but also addresses challenges such as circuit interference and frequency issues through its rational design, improving the reliability of host startup, making it particularly suitable for desktop and laptop systems requiring high stability.

[0043] This utility model embodiment also provides a terminal device, which includes the BIOS detection circuit 100 described above. For the specific structure and function of the BIOS detection circuit 100, please refer to the above embodiments, and will not be repeated here.

[0044] It should be noted that while the preferred embodiments of this utility model are provided in the specification and accompanying drawings, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are not intended to impose additional limitations on the content of this utility model; their purpose is to provide a more thorough and comprehensive understanding of the disclosure of this utility model. Furthermore, the above-described technical features can be combined with each other to form various embodiments not listed above, all of which are considered to be within the scope of this utility model specification. Moreover, those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A BIOS detection circuit, characterized in that, The BIOS detection circuit includes: a central processing unit module, a signal switching chip module, a signal switching button module, a first BIOS memory module, and a second BIOS memory module. The signal switching chip module is connected to the central processing unit module, the signal switching button module, the first BIOS memory module, and the second BIOS memory module, respectively. The central processing unit module is also connected to the first BIOS memory module and the second BIOS memory module. When the system does not detect any BIOS data corruption, the signal switching chip module outputs a first chip select signal to the first BIOS memory module; When the system detects BIOS data corruption, the signal switching button module outputs a first control signal to the signal switching chip module. The signal switching chip module receives the first control signal and outputs a second chip select signal to the second BIOS memory module.

2. The BIOS detection circuit according to claim 1, characterized in that, The central processing unit module includes an SPI chip select signal pin and a data transmission signal pin. The SPI chip select signal pin is connected to the signal switching chip module, and the data transmission signal pin is connected to the first BIOS memory module and the second BIOS memory module, respectively.

3. The BIOS detection circuit according to claim 1, characterized in that, The signal switching button module includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is used to output the first control signal to the signal switching chip module, and the second pin, the third pin, and the fourth pin are respectively grounded.

4. The BIOS detection circuit according to claim 2, characterized in that, The signal switching chip module includes a first VCC power supply, a first chip U1, a first capacitor C1, a first resistor R7, and a second resistor R8. The first chip U1 includes an EN pin, a VCC pin, a SIN pin, a SOUT1 pin, a GND pin, and a SCOUT2 pin. The first end of the second resistor R8 is connected to the first VCC power supply, and the second end of the second resistor R8 is connected to the VCC pin. The first end of the first capacitor C1 is connected to the second end of the second resistor R8 and the VCC pin, respectively, and the second end of the first capacitor C1 is grounded. The first end of the first resistor R7 is connected to the signal switching button module, and the second end of the first resistor R7 is connected to the EN pin. The SIN pin is connected to the SPI chip select signal pin. The SCOUT1 pin is connected to the first BIOS memory module, the SCOUT2 pin is connected to the second BIOS memory module, and the GND pin is grounded.

5. The BIOS detection circuit according to claim 4, characterized in that, The data transmission signal pins include a first data transmission pin, a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a fifth data transmission pin. The first BIOS memory module includes a first BIOS chip, a second capacitor C2, and a second VCC power supply. The first BIOS chip includes a first VSS pin, a first VDD pin, a first chip select pin, a first serial output pin, a second serial output pin, a third serial output pin, a fourth serial output pin, and a first serial clock pin. The first chip select pin is connected to the SCOUT1 pin. The first serial output pin is connected to the first data transmission pin. The second serial output pin is connected to the second data transmission pin. The third serial output pin is connected to the third data transmission pin. The fourth serial output pin is connected to the fourth data transmission pin. The first serial clock pin is connected to the fifth data transmission pin. The first VSS pin is grounded. The first end of the second capacitor C2 is grounded. The second end of the second capacitor C2 is connected to the first VDD pin and the second VCC power supply, respectively.

6. The BIOS detection circuit according to claim 5, characterized in that, The second BIOS memory module includes a second BIOS chip, a third capacitor C3, and a third VCC power supply. The second BIOS chip includes a second VSS pin, a second VDD pin, a second chip select pin, a fifth serial output pin, a sixth serial output pin, a seventh serial output pin, an eighth serial output pin, and a second serial clock pin. The second chip select pin is connected to the SCOUT2 pin. The fifth serial output pin is connected to the first data transmission pin. The sixth serial output pin is connected to the second data transmission pin. The seventh serial output pin is connected to the third data transmission pin. The eighth serial output pin is connected to the fourth data transmission pin. The second serial clock pin is connected to the fifth data transmission pin. The second VSS pin is grounded. The first end of the third capacitor C3 is grounded. The second end of the third capacitor C3 is connected to the second VDD pin and the third VCC power supply, respectively.

7. A terminal device, characterized in that, The terminal device is equipped with a BIOS detection circuit as described in any one of claims 1 to 6.

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