Power module packaging structure

Abstract

The utility model discloses a power module packaging structure, which comprises a signal terminal formed into an island-shaped signal terminal on a substrate, a first end of the signal terminal is connected with a power chip, a second end of the signal terminal forms an external interface, and the signal terminal is only used for signal transmission and does not pass through power current. According to the utility model, the layout of the signal terminals on the welding surface of the chip is optimized, and the island-shaped signal terminals and a power current path are separated to form a structure similar to a current island, so that the current of a power loop does not flow through a measurement loop, and the parasitic inductance of the layout is prevented from influencing the measurement of IGBT amp by a PCBA (Printed Circuit Board Assembly); and the result of the surface voltage stress of the SIC chip enables the chip welding surface which cannot be used as the Kelvin pin to obtain the effect of arranging the Kelvin pin. The signal terminal provided by the utility model can be used for actually measuring the electric stress on the surface of a chip; the SIC application design can optimize the design of the safety margin, exerts more capabilities of the device, reduces the cost for achieving the same capability, and reduces the failure probability caused by inaccurate measurement at the same time.

Description

Technical Field

[0001] This utility model relates to the semiconductor field, and in particular to a power module packaging structure. Background Technology

[0002] Power modules are key components in power electronics technology. They integrate multiple power semiconductor devices, drive circuits, protection circuits, and necessary electrical and thermal management components to achieve efficient power conversion and control. The packaging structure of power modules is a very important part of power electronic devices, as it not only relates to the electrical performance of the devices but also directly affects their heat dissipation efficiency and reliability.

[0003] Existing technology involves soldering pin headers from the AMB or DCB baseplate pattern to the AMB or DCB baseplate pattern, and then connecting the chip surface Kelvin structure leads to these pin headers via soldering pins or crimping pins. Voltage signals are then transmitted to the PCBA via signal pins, and the PCBA measures the electrical stress of the IGBT and SiC. However, because power module layout introduces parasitic inductance, the measurement data from conventional signal terminals includes voltage from this parasitic inductance (the measured voltage is not the voltage on the power device itself). This inductance voltage causes the actual voltage to be lower or higher (depending on the direction of current change and the inductor's position), making it impossible to determine the electrical stress of the power module. This necessitates a large margin in power module applications or prevents safe design.

[0004] The industry standard optimization approach is to use a Kelvin structure for the E / S terminals to avoid the impact of parasitic inductance on the test voltage. Current conventional designs cannot avoid the impact of collector parasitic inductance on the test voltage, and using Kelvin structures for both the upper and lower bridges increases layout area and affects layout integration. Utility Model Content

[0005] The utility model description section introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by this utility model is to provide a power module packaging structure that can avoid the influence of parasitic inductance on the test voltage and accurately measure the voltage of the power device itself.

[0007] To solve the above-mentioned technical problems, the power module packaging structure provided by this utility model includes:

[0008] Signal terminals are formed as island-shaped signal terminals on a substrate. Their first end connects to a power chip, and their second end forms an external interface. They are used only for signal transmission and do not carry power current. Island-shaped signal terminals refer to isolated copper foil areas in PCB (printed circuit board) design that are not connected to anywhere else. This structure is also known as isolated copper foil.

[0009] Preferably, the power module packaging structure is further improved, with the first end of the signal terminal connected to the power chip via an independent bonding wire.

[0010] Preferably, the power module packaging structure is further improved by using a Kelvin structure on the surface of the power chip bonding wires.

[0011] Preferably, the power module packaging structure is further improved such that when the power chip is an IGBT, the first terminal of the signal terminal is connected to the emitter (E) or collector (C) of the power chip.

[0012] Preferably, the power module packaging structure is further improved such that when the power chip is a MOSFET, the first terminal of the signal terminal is connected to the source (S) terminal of the power chip.

[0013] Preferably, the power module packaging structure is further improved, with signal terminals arranged at the four corners of the substrate.

[0014] Preferably, the power module packaging structure is further improved, with a first gap formed between the signal terminal and the adjacent power chip, and the first gap is greater than or equal to the minimum pattern rule.

[0015] Preferably, the power module packaging structure is further improved by forming a second gap between the signal terminal and the current path of the adjacent power chip, the second gap being equal to the maximum distance allowed on the substrate between the signal terminal and the current path of the adjacent power chip.

[0016] Preferably, the power module packaging structure is further improved by using a DCB or AMB substrate.

[0017] Preferably, the power module packaging structure is further improved, and the second end of the signal terminal is formed as a pin connector.

[0018] This invention optimizes the layout of signal terminals on the chip soldering surface. By separating the island-shaped signal terminals from the power current path, a structure similar to a current island is formed. This prevents the power circuit current from flowing through the measurement circuit, avoiding the parasitic inductance of the layout from affecting the PCBA measurement results of IGBT & SiC chip surface voltage stress. It also allows chip soldering surfaces that cannot be configured with Kelvin pins to achieve the effect of having Kelvin pins. The signal terminals of this invention can accurately measure the surface electrical stress of the chip. For IGBT & SiC application designs, it can optimize the design of safety margins, maximize the device's capabilities, reduce the cost of achieving the same capabilities, and decrease the probability of failure due to measurement inaccuracies.

[0019] The chip bonding wire surface uses a Kelvin structure to avoid the parasitic inductance of the bonding wire affecting the PCBA measurement results of IGBT & SiC chip surface voltage stress. Attached Figure Description

[0020] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the present invention, supplementing the description in the specification. However, these drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by the exemplary embodiments of the present invention. The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0021] Figure 1 This is a schematic diagram of the structure of this utility model.

[0022] Explanation of reference numerals in the attached figures

[0023] Signal terminal 1

[0024] Substrate 2

[0025] Power chip 3. Detailed Implementation

[0026] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can fully understand other advantages and technical effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the utility model. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of this utility model can be implemented in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of this utility model thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0027] First embodiment;

[0028] refer to Figure 1 As shown, this utility model provides a power module packaging structure. It should be noted that other structures of this power module packaging structure can adopt any of the existing technologies. The main improvement lies in:

[0029] Signal terminal 1 is formed as an island-shaped signal terminal on substrate 2. Its first end is connected to power chip 3, and its second end forms an external interface. It is only used for signal transmission and does not carry power current.

[0030] Preferably, the first end of the signal terminal is connected to the power chip via an independent bonding wire, the surface of the power chip bonding wire uses a Kelvin structure, and the substrate is a DCB or AMB substrate.

[0031] Preferably, the signal terminals are arranged at the four corners of the substrate. This design can make full use of the substrate area to separate the signal transmission and power current paths.

[0032] Second embodiment;

[0033] This utility model provides a power module packaging structure. It should be noted that other structures of this power module packaging structure can adopt any of the existing technologies. The main improvement lies in:

[0034] Signal terminal 1 is formed as an island-shaped signal terminal on substrate 2. Its first end is connected to power chip 3, and its second end forms an external interface. It is only used for signal transmission and does not carry power current.

[0035] The power chip is an IGBT, and the first signal terminal is connected to the emitter (E) or collector (C) of the power chip.

[0036] Preferably, the signal terminals are arranged at the four corners of the substrate. This design can make full use of the substrate area to separate the signal transmission and power current paths.

[0037] Preferably, a first gap is formed between the signal terminal and the adjacent power chip, and the first gap is greater than or equal to the minimum pattern rule.

[0038] Preferably, a second gap is formed between the signal terminal and the current path of the adjacent power chip, and the second gap is equal to the maximum distance allowed on the substrate between the signal terminal and the current path of the adjacent power chip.

[0039] In a further improvement to the second embodiment described above, the second end of the signal terminal is formed as a pin connector.

[0040] Third embodiment;

[0041] This utility model provides a power module packaging structure. It should be noted that other structures of this power module packaging structure can adopt any of the existing technologies. The main improvement lies in:

[0042] Signal terminal 1 is formed as an island-shaped signal terminal on substrate 2. Its first end is connected to power chip 3, and its second end forms an external interface. It is only used for signal transmission and does not carry power current.

[0043] The power chip is a MOSFET, and the first terminal of the signal terminal is connected to the source (S) of the power chip.

[0044] Preferably, the first end of the signal terminal is connected to the power chip via an independent bonding wire, the surface of the power chip bonding wire uses a Kelvin structure, the substrate is a DCB or AMB substrate, and the signal terminals are arranged at the four corners of the substrate.

[0045] Preferably, a first gap is formed between the signal terminal and the adjacent power chip, and the first gap is greater than or equal to the minimum pattern rule.

[0046] Preferably, a second gap is formed between the signal terminal and the current path of the adjacent power chip, and the second gap is equal to the maximum distance allowed on the substrate between the signal terminal and the current path of the adjacent power chip.

[0047] In a further improvement to the third embodiment described above, the second end of the signal terminal is formed as a pin connector.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0049] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the present invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A power module packaging structure, characterized in that, include: The signal terminal is formed as an island-shaped signal terminal on the substrate. Its first end is connected to the power chip, and its second end forms an external interface. It is only used for signal transmission and does not carry power current.

2. The power module packaging structure as described in claim 1, characterized in that: The first end of the signal terminal is connected to the power chip via an independent bonding wire.

3. The power module packaging structure as described in claim 1, characterized in that: The bonding wire surface of the power chip uses a Kelvin structure.

4. The power module packaging structure as described in claim 1, characterized in that: When the power chip is an IGBT, the first terminal of the signal terminal is connected to the emitter (E) or collector (C) of the power chip.

5. The power module packaging structure as described in claim 1, characterized in that: When the power chip is a MOSFET, the first terminal of the signal terminal is connected to the source (S) of the power chip.

6. The power module packaging structure as described in claim 1, characterized in that: Signal terminals are arranged at the four corners of the substrate.

7. The power module packaging structure as described in claim 1, characterized in that: A first gap is formed between the signal terminal and the adjacent power chip, and the first gap is greater than or equal to the minimum pattern rule.

8. The power module packaging structure as described in claim 1, characterized in that: A second gap is formed between the signal terminal and the current path of the adjacent power chip, and the second gap is equal to the maximum distance allowed on the substrate between the signal terminal and the current path of the adjacent power chip.

9. The power module packaging structure as described in claim 1, characterized in that: The substrate is a DCB or AMB substrate.

10. The power module packaging structure as described in claim 1, characterized in that: The second end of the signal terminal is formed as a pin connector.

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