Driving circuit of insulated gate bipolar transistor

Abstract

The utility model provides a driving circuit of an insulated gate bipolar transistor, and relates to the technical field of insulated gate bipolar transistors, a square wave signal is inverted and delayed through an inverted delay module, a processed signal is generated, then a first narrow pulse signal is generated through a first generation module according to the square wave signal and the processed signal, and a second narrow pulse signal is generated through a second generation module. A second narrow pulse signal is generated through a second generation module according to the square wave signal and the processed signal, the voltage of the first narrow pulse signal is boosted through an output module to generate a third narrow pulse signal, and the voltage of the second narrow pulse signal is boosted to generate a fourth narrow pulse signal; and generating a control signal for driving the insulated gate bipolar transistor according to the third narrow pulse signal and the fourth narrow pulse signal, and since the duty ratio of the narrow pulse signal is smaller than that of the square wave signal, compared with the voltage conversion realized through the square wave signal in the prior art, the voltage conversion realized through the narrow pulse signal has the advantage that the voltage conversion efficiency is improved. And heat loss generated by devices in the driving circuit is reduced.

Description

Technical Field

[0001] This application belongs to the field of insulated gate bipolar transistor (IGBT) technology, and specifically relates to a driving circuit for an IGBT. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) operates in a high-voltage domain and requires a high-voltage (e.g., 615 volts) control signal to drive it. In contrast, a microcontroller unit (MCU) operates in a low-voltage domain and provides a low-voltage (e.g., 3.3 volts) square wave signal using pulse width modulation (PWM).

[0003] In the prior art, a voltage conversion circuit directly converts the low-voltage square wave signal output by the microcontroller unit into a high-voltage control signal required to drive the insulated gate bipolar transistor.

[0004] However, in the process of directly converting a low-voltage square wave signal into a high-voltage control signal required to drive an insulated-gate bipolar transistor, the devices in the voltage conversion circuit generate significant heat loss. Utility Model Content

[0005] This application aims to provide a driving circuit for an insulated gate bipolar transistor (IGBT), which at least solves the problem of high heat loss in the voltage conversion circuit during the process of directly converting a low-voltage square wave signal into a high-voltage control signal required to drive the IGBT in the prior art.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] This application provides a driving circuit for an insulated gate bipolar transistor, including an inverting delay module, a first generation module, a second generation module, and an output module;

[0008] The inverting delay module is electrically connected to the first generation module and the second generation module respectively. The inverting delay module is used to receive the square wave signal, and to invert and delay the square wave signal to generate the processed signal.

[0009] The first generation module is electrically connected to the output module. The first generation module is used to receive the square wave signal and generate a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal.

[0010] The second generation module is electrically connected to the output module. The second generation module is used to receive the square wave signal and generate a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0011] The output module is used to increase the voltage of the first narrow pulse signal to generate a third narrow pulse signal, and increase the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal, and generate a control signal to drive the insulated gate bipolar transistor based on the third narrow pulse signal and the fourth narrow pulse signal.

[0012] In this embodiment, a square wave signal is received by an inverting delay module, and the square wave signal is inverted and delayed to generate a processed signal. Then, a first generation module receives the square wave signal and generates a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal. A second generation module receives the square wave signal and generates a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal. The voltage of the first narrow pulse signal is increased by an output module to generate a third narrow pulse signal, and the voltage of the second narrow pulse signal is increased to generate a fourth narrow pulse signal. A control signal for driving an insulated gate bipolar transistor is generated based on the third and fourth narrow pulse signals. In this process, since the duty cycle of the narrow pulse signal is smaller than that of the square wave signal, voltage conversion using a narrow pulse signal reduces the heat loss of the devices in the driving circuit compared to voltage conversion using a square wave signal in the prior art. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a driving circuit for an insulated gate bipolar transistor provided in an embodiment of this application;

[0015] Figure 2 This is a schematic diagram of a driving circuit for an insulated gate bipolar transistor provided in an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of another driving circuit for an insulated gate bipolar transistor provided in an embodiment of this application;

[0017] Figure 4This is a timing diagram of a driving circuit for an insulated gate bipolar transistor provided in an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of the driving process of the insulated gate bipolar transistor provided in the embodiments of this application.

[0019] Figure label:

[0020] 10-Inverting delay module; 11-First inverting delay submodule; 111-First delay unit; 12-Second inverting delay submodule; 121-Second delay unit; 13-Delay submodule; 20-First generation module; 30-Second generation module; 40-Output module; 41-Voltage conversion submodule; 42-Output submodule; F1-First inverter; F2-Second inverter; F3-Third inverter; R1-First resistor; R2-Second resistor; R3-Third resistor; C1-First capacitor; C2-Second capacitor; C3-Third capacitor; M1-AND gate; M2-NOR gate. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] Reference Figure 1This application provides a driving circuit for an insulated gate bipolar transistor (IGBT), including an inverting delay module 10, a first generation module 20, a second generation module 30, and an output module 40. The inverting delay module 10 is electrically connected to both the first generation module 20 and the second generation module 30. The inverting delay module 10 receives a square wave signal and inverts and delays the square wave signal to generate a processed signal. The first generation module 20 is electrically connected to the output module 40. The first generation module 20 receives the square wave signal and generates a signal representing the square wave signal and the processed signal. The square wave signal is a rising edge of a first narrow pulse signal; the second generation module 30 is electrically connected to the output module 40, the second generation module 30 is used to receive the square wave signal, and generate a second narrow pulse signal to characterize the falling edge of the square wave signal according to the square wave signal and the processed signal; the output module 40 is used to increase the voltage of the first narrow pulse signal to generate a third narrow pulse signal, and increase the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal, and generate a control signal to drive the insulated gate bipolar transistor according to the third narrow pulse signal and the fourth narrow pulse signal.

[0024] It should be noted that the control signal driving the insulated gate bipolar transistor is used as input to the gate of the insulated gate bipolar transistor.

[0025] The voltage of the square wave signal, the voltage of the processed signal, the voltage of the first narrow pulse signal, and the voltage of the second narrow pulse signal are all first voltages (e.g., 15 volts), while the voltage of the third narrow pulse signal, the voltage of the fourth narrow pulse signal, and the voltage of the control signal driving the insulated gate bipolar transistor are all second voltages (e.g., 615 volts).

[0026] The duty cycles of the first narrow pulse signal, the second narrow pulse signal, the third narrow pulse signal, and the fourth narrow pulse signal are all the first duty cycle, while the duty cycles of the square wave signal and the control signal driving the insulated gate bipolar transistor are all the second duty cycle. The first duty cycle is smaller than the second duty cycle.

[0027] The square wave signal is a pulse width modulation signal. Specifically, in some embodiments, the driving circuit of the insulated gate bipolar transistor further includes a filtering module and a voltage conversion module. The filtering module is electrically connected to the microcontroller unit and the voltage conversion module. The voltage conversion module is electrically connected to the inverting delay module 10, the first generation module 20, and the second generation module 30, respectively. The filtering module is used to filter the initial square wave signal output by the microcontroller unit to generate a filtered square wave signal. The initial square wave signal is a low-voltage (e.g., 3.3 volts) pulse width modulation signal. The voltage conversion module is used to increase the voltage of the filtered square wave signal to generate the square wave signal.

[0028] Because a larger duty cycle of a signal in a circuit results in a longer duration of current generation, the heat loss caused by the current passing through the components in the circuit is greater. Therefore, compared to a square wave signal, a narrow pulse signal has a smaller duty cycle. Consequently, during voltage conversion using a narrow pulse signal, the heat loss caused by the current passing through the components in the circuit is less than that caused by the current passing through the components in the circuit using a square wave signal.

[0029] In this embodiment, a square wave signal is received by an inverting delay module 10, and the square wave signal is inverted and delayed to generate a processed signal. Then, a first generation module 20 receives the square wave signal and generates a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal. A second generation module 30 receives the square wave signal and generates a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal. The output module 40 then increases the voltage of the first narrow pulse signal to generate a third narrow pulse signal and increases the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal. A control signal for driving an insulated gate bipolar transistor is generated based on the third and fourth narrow pulse signals. In this process, since the duty cycle of the narrow pulse signal is smaller than that of the square wave signal, voltage conversion using a narrow pulse signal reduces the heat loss of the devices in the driving circuit compared to voltage conversion using a square wave signal in the prior art.

[0030] Optionally, refer to Figure 2In some embodiments, the inverting delay module 10 includes a first inverting delay submodule 11 and a second inverting delay submodule 12; the first inverting delay submodule 11 is electrically connected to the first generation module 20, and is used to receive the square wave signal, and invert and delay the square wave signal to generate the processed signal; the second inverting delay submodule 12 is electrically connected to the second generation module 30, and is used to receive the square wave signal, and invert and delay the square wave signal to generate the processed signal.

[0031] It should be noted that the signal generated by the first inverting and delaying submodule 11 of the square wave signal is the same as the signal generated by the second inverting and delaying submodule 12 of the square wave signal; both are processed signals.

[0032] In this embodiment, a square wave signal is received by a first inverting delay submodule 11, and the square wave signal is inverted and delayed to generate a processed signal, which is then used by a first generation module 20 to generate a first narrow pulse signal representing the rising edge of the square wave signal based on the square wave signal and the processed signal; a square wave signal is received by a second inverting delay submodule 12, and the square wave signal is inverted and delayed to generate a processed signal, which is then used by a second generation module 30 to generate a second narrow pulse signal representing the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0033] In this process, since the process of the first inverting delay submodule 11 inverting and delaying the square wave signal to generate the processed signal is independent of the process of the second inverting delay submodule 12 inverting and delaying the square wave signal to generate the processed signal, the acquisition of the processed signal by the first generation module 20 is independent of the acquisition of the processed signal by the second generation module 30.

[0034] Optionally, in some embodiments, the first inverting delay submodule 11 includes a first inverter F1 and a first delay unit 111; the first inverter F1 is electrically connected to the first delay unit 111, and the first inverter F1 is used to receive the square wave signal and invert the square wave signal to generate a first inverted signal; the first delay unit 111 is electrically connected to the first generation module 20, and the first delay unit 111 is used to delay the first inverted signal to generate the processed signal.

[0035] In this embodiment, a square wave signal is received by a first inverter F1 and inverted to generate a first inverted signal. The first inverted signal is then delayed by a first delay unit 111 to generate a processed signal, which is then used by the first generation module 20 to generate a first narrow pulse signal that characterizes the rising edge of the square wave signal based on the square wave signal and the processed signal.

[0036] Optionally, in some embodiments, the first delay unit 111 includes a first resistor R1 and a first capacitor C1; the input terminal of the first inverter F1 is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the first inverter F1 is electrically connected to the first terminal of the first resistor R1; the square wave signal receiving terminal is used to receive the square wave signal; the second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1 and the first input terminal of the first generation module 20 respectively; the second terminal of the first capacitor C1 is grounded; and the second input terminal of the first generation module 20 is electrically connected to the square wave signal receiving terminal.

[0037] It should be noted that the first resistor R1 and the first capacitor C1 form a resistor-capacitor (RC) filter, which is used to delay the first inverted signal to generate the processed signal.

[0038] In this embodiment, a square wave signal is received by a square wave signal receiver so that the first inverter F1 inverts the square wave signal to generate a first inverted signal. Then, the first inverted signal is delayed by the first resistor R1 and the first capacitor C1 to generate a processed signal. The first generation module 20 generates a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal.

[0039] Optionally, in some embodiments, the second inverting delay submodule 12 includes a second inverter F2 and a second delay unit 121; the second inverter F2 is electrically connected to the second delay unit 121, and the second inverter F2 is used to receive the square wave signal and invert the square wave signal to generate a second inverted signal; the second delay unit 121 is electrically connected to the second generation module 30, and the second delay unit 121 is used to delay the second inverted signal to generate the processed signal.

[0040] In this embodiment, a square wave signal is received by a second inverter F2 and inverted to generate a second inverted signal. The second inverted signal is then delayed by a second delay unit 121 to generate a processed signal, which is then used by the second generation module 30 to generate a second narrow pulse signal that characterizes the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0041] Optionally, in some embodiments, the second delay unit 121 includes a second resistor R2 and a second capacitor C2; the input terminal of the second inverter F2 is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the second inverter F2 is electrically connected to the first terminal of the second resistor R2; the square wave signal receiving terminal is used to receive the square wave signal; the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first input terminal of the second generation module 30 respectively; the second terminal of the second capacitor C2 is grounded; and the second input terminal of the second generation module 30 is electrically connected to the square wave signal receiving terminal.

[0042] It should be noted that the second resistor R2 and the second capacitor C2 form a resistor-capacitor (RC) filter, which is used to delay the second inverted signal to generate the processed signal.

[0043] In this embodiment, a square wave signal is received by a square wave signal receiver so that the second inverter F2 inverts the square wave signal to generate a second inverted signal. Then, the second resistor R2 and the second capacitor C2 work together to delay the second inverted signal to generate a processed signal. The second generation module 30 then generates a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0044] Optionally, refer to Figure 3 In some embodiments, the inverting delay module 10 includes a third inverter F3 and a delay submodule 13; the third inverter F3 is electrically connected to the delay submodule 13, and the third inverter F3 is used to receive the square wave signal and invert the square wave signal to generate a third inverted signal; the delay submodule 13 is electrically connected to the first generation module 20 and the second generation module 30 respectively, and the delay submodule 13 is used to delay the third inverted signal to generate the processed signal.

[0045] In this embodiment, a square wave signal is received by a third inverter F3 and inverted to generate a third inverted signal. The third inverted signal is then delayed by a delay submodule 13 to generate a processed signal. This processed signal is then used by a first generation module 20 to generate a first narrow pulse signal representing the rising edge of the square wave signal based on the square wave signal and the processed signal, and by a second generation module 30 to generate a second narrow pulse signal representing the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0046] Optionally, in some embodiments, the delay submodule 13 includes a third resistor R3 and a third capacitor C3; the input terminal of the third inverter F3 is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the third inverter F3 is electrically connected to the first terminal of the third resistor R3; the square wave signal receiving terminal is used to receive the square wave signal; the second terminal of the third resistor R3 is electrically connected to the first terminal of the third capacitor C3, the first input terminal of the first generation module 20, and the first input terminal of the second generation module 30, respectively; the second terminal of the third capacitor C3 is grounded; the second input terminal of the first generation module 20 is electrically connected to the square wave signal receiving terminal; and the second input terminal of the second generation module 30 is electrically connected to the square wave signal receiving terminal.

[0047] It should be noted that the third resistor R3 and the third capacitor C3 form a resistor-capacitor (RC) filter, which is used to delay the third inverted signal to generate the processed signal.

[0048] In this embodiment, a square wave signal is received by a square wave signal receiver so that the third inverter F3 inverts the square wave signal to generate a third inverted signal. Then, the third resistor R3 and the third capacitor C3 work together to delay the third inverted signal to generate a processed signal. The first generation module 20 generates a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal, and the second generation module 30 generates a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal.

[0049] Optionally, in some embodiments, the first generation module 20 includes an AND gate device M1; the input terminal of the inverting delay module 10 is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the first output terminal of the inverting delay module 10 is electrically connected to the first input terminal of the AND gate device M1; the square wave signal receiving terminal is used to receive the square wave signal; the second input terminal of the AND gate device M1 is electrically connected to the square wave signal receiving terminal, and the output terminal of the AND gate device M1 is electrically connected to the first input terminal of the output module 40.

[0050] It should be noted that the AND gate device M1 has a high-level threshold and a low-level threshold. When the voltage of the input signal of the AND gate device M1 is greater than the high-level threshold of the AND gate device M1, the input signal level of the AND gate device M1 is high; when the voltage of the input signal of the AND gate device M1 is less than the low-level threshold of the AND gate device M1, the input signal level of the AND gate device M1 is low.

[0051] In this embodiment, an AND gate device M1 generates a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal. Specifically, the level of the first narrow pulse signal is high when both the level of the square wave signal and the level of the processed signal are high; the level of the first narrow pulse signal is low when both the level of the square wave signal and the level of the processed signal are low; the level of the first narrow pulse signal is low when both the level of the square wave signal and the level of the processed signal are low; and the level of the first narrow pulse signal is low when both the level of the square wave signal and the level of the processed signal are high.

[0052] Optionally, in some embodiments, the second generation module 30 includes a NOR gate device M2; the input terminal of the inverting delay module 10 is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the second output terminal of the inverting delay module 10 is electrically connected to the first input terminal of the NOR gate device M2; the square wave signal receiving terminal is used to receive the square wave signal; the second input terminal of the NOR gate device M2 is electrically connected to the square wave signal receiving terminal, and the output terminal of the NOR gate device M2 is electrically connected to the second input terminal of the output module 40.

[0053] It should be noted that the NOR gate M2 has a high-level threshold and a low-level threshold. When the voltage of the input signal of the NOR gate M2 is greater than the high-level threshold of the NOR gate M2, the level of the input signal of the NOR gate M2 is high; when the voltage of the input signal of the NOR gate M2 is less than the low-level threshold of the NOR gate M2, the level of the input signal of the NOR gate M2 is low.

[0054] In this embodiment, a second narrow pulse signal characterizing the falling edge of the square wave signal is generated by the NOR gate M2 based on the square wave signal and the processed signal. Specifically, when both the square wave signal and the processed signal are at a high level, the level of the second narrow pulse signal is low; when both the square wave signal and the processed signal are at a high level, the level of the first narrow pulse signal is low; when both the square wave signal and the processed signal are at a low level, the level of the first narrow pulse signal is high; and when both the square wave signal and the processed signal are at a low level, the level of the first narrow pulse signal is low.

[0055] Optionally, in some embodiments, the output module 40 includes a voltage conversion submodule 41 and an output submodule 42; the voltage conversion submodule 41 is electrically connected to the first generation module 20 and the second generation module 30 respectively, and is used to increase the voltage of the first narrow pulse signal to generate the third narrow pulse signal, and increase the voltage of the second narrow pulse signal to generate the fourth narrow pulse signal; the output submodule 42 is electrically connected to the voltage conversion submodule 41, and is used to generate the control signal according to the third narrow pulse signal and the fourth narrow pulse signal.

[0056] Specifically, in some embodiments, the output submodule 42 includes a generation unit and an output unit. The generation unit is electrically connected to the voltage conversion submodule 41 and the output unit, respectively. The generation unit is used to generate an initial control signal based on the third narrow pulse signal and the fourth narrow pulse signal, wherein the voltage of the initial control signal is the second voltage and the duty cycle of the initial control signal is the second duty cycle. The output unit is used to increase the current of the initial control signal to generate a control signal.

[0057] In this embodiment, the voltage of the first narrow pulse signal is increased by the voltage conversion submodule 41 to generate the third narrow pulse signal, and the voltage of the second narrow pulse signal is increased to generate the fourth narrow pulse signal. Then, the output submodule 42 generates a control signal based on the third and fourth narrow pulse signals to drive the insulated gate bipolar transistor.

[0058] Optionally, in some embodiments, the driving circuit of the insulated gate bipolar transistor further includes a filtering module; the filtering module is electrically connected to the inverting delay module 10, the first generation module 20 and the second generation module 30 respectively, and the filtering module is used to receive the initial square wave signal and filter the initial square wave signal to generate the square wave signal.

[0059] Specifically, in some embodiments, the input terminal of the filtering module is used to receive the initial square wave signal, and the output terminal of the filtering module is electrically connected to the square wave signal receiving terminal.

[0060] In this embodiment of the application, an initial square wave signal is received by a filtering module and filtered to generate a square wave signal, which is then input to the inverting delay module 10, the first generation module 20, and the second generation module 30.

[0061] In other embodiments, the driving circuit of the insulated gate bipolar transistor further includes a filtering module and a voltage conversion module. The input terminal of the filtering module is electrically connected to the output terminal of the microcontroller unit, the output terminal of the filtering module is electrically connected to the input terminal of the voltage conversion module, and the output terminal of the voltage conversion module is electrically connected to the square wave signal receiving terminal. The filtering module is used to filter the initial square wave signal output by the microcontroller unit to generate a filtered square wave signal, wherein the initial square wave signal is a low-voltage (e.g., 3.3 volts) pulse width modulation signal. The voltage conversion module is used to increase the voltage of the filtered square wave signal to generate a square wave signal.

[0062] Optionally, in some embodiments, the duty cycle of the control signal is the same as the duty cycle of the square wave signal, and the voltage of the control signal is greater than the voltage of the square wave signal.

[0063] In this embodiment, since the duty cycle of the control signal is the same as that of the square wave signal, the voltage of the control signal is greater than that of the square wave signal, so that the control signal can be used to drive the insulated gate bipolar transistor.

[0064] Specifically, in some embodiments, the driving circuit of the insulated gate bipolar transistor includes an inverting delay module 10, a first generation module 20, a second generation module 30, and an output module 40; the inverting delay module 10 includes a first inverting delay submodule 11 and a second inverting delay submodule 12; the first inverting delay submodule 11 includes a first inverter F1 and a first delay unit 111; the first delay unit 111 includes a first resistor R1 and a first capacitor C1; the second inverting delay submodule 12 includes a second inverter F2 and a second delay unit 121; the second delay unit 121 includes a second resistor R2 and a second capacitor C2; the first generation module 20 includes an AND gate device M1; the second generation module 30 includes a NOR gate device M2; the output module 40 includes a voltage conversion submodule 41 and an output submodule 42; the output submodule 42 includes a generation unit and an output unit; the driving circuit of the insulated gate bipolar transistor also includes a filtering module and a voltage conversion module;

[0065] The input terminal of the filtering module is electrically connected to the output terminal of the microcontroller unit; the output terminal of the filtering module is electrically connected to the input terminal of the voltage conversion module; the output terminal of the voltage conversion module is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor; the input terminal of the first inverter F1 is electrically connected to the square wave signal receiving terminal; the output terminal of the first inverter F1 is electrically connected to the first terminal of the first resistor R1; the square wave signal receiving terminal is used to receive square wave signals; the second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1 and the first input terminal of the AND gate device M1; the second terminal of the first capacitor C1 is grounded; the second input terminal of the AND gate device M1 is electrically connected to the square wave signal receiving terminal; the output terminal of the AND gate device M1 is electrically connected to the first input terminal of the voltage conversion submodule 41; the voltage conversion submodule... The first output terminal of block 41 is electrically connected to the first input terminal of the generation unit, the output terminal of the generation unit is electrically connected to the input terminal of the output unit, and the output terminal of the output unit is used to be electrically connected to the gate of the insulated gate bipolar transistor; the input terminal of the second inverter F2 is electrically connected to the square wave signal receiving terminal, and the output terminal of the second inverter F2 is electrically connected to the first terminal of the second resistor R2; the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first input terminal of the NOR gate device M2; the second terminal of the second capacitor C2 is grounded; the second input terminal of the NOR gate device M2 is electrically connected to the square wave signal receiving terminal, and the output terminal of the NOR gate device M2 is electrically connected to the second input terminal of the voltage conversion submodule 41, and the second output terminal of the voltage conversion submodule 41 is electrically connected to the second input terminal of the generation unit;

[0066] The initial square wave signal output from the microcontroller unit is filtered by a filtering module to generate a filtered square wave signal. The voltage conversion module then boosts the voltage of the filtered square wave signal to generate another square wave signal. A first inverter F1 receives the square wave signal and inverts it to generate a first inverted signal. A first resistor R1 and a first capacitor C1 then delay the inverted signal to generate a processed signal. An AND gate M1 then generates a first narrow pulse signal representing the rising edge of the square wave signal based on the square wave signal and the processed signal. The first inverter F1 receives the square wave signal and inverts it to generate the first inverted signal, which is then... The second resistor R2 and the second capacitor C2 work together to delay the second inverted signal, generating a processed signal. Then, the NOR gate M2 generates a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal. The voltage conversion submodule 41 increases the voltage of the first narrow pulse signal to generate a third narrow pulse signal, and increases the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal. The generation unit generates an initial control signal based on the third and fourth narrow pulse signals. Then, the output unit increases the current of the initial control signal to generate a control signal, which drives the insulated gate bipolar transistor.

[0067] Specifically, in some other embodiments, the driving circuit of the insulated gate bipolar transistor includes an inverting delay module 10, a first generation module 20, a second generation module 30, and an output module 40; the inverting delay module 10 includes a third inverter F3 and a delay submodule 13; the delay submodule 13 includes a third resistor R3 and a third capacitor C3; the first generation module 20 includes an AND gate device M1; the second generation module 30 includes a NOR gate device M2; the output module 40 includes a voltage conversion submodule 41 and an output submodule 42; the output submodule 42 includes a generation unit and an output unit; the driving circuit of the insulated gate bipolar transistor also includes a filtering module and a voltage conversion module;

[0068] The input terminal of the filter module is electrically connected to the output terminal of the microcontroller unit; the output terminal of the filter module is electrically connected to the input terminal of the voltage conversion module; the output terminal of the voltage conversion module is electrically connected to the square wave signal receiving terminal of the drive circuit of the insulated gate bipolar transistor; the input terminal of the third inverter F3 is electrically connected to the square wave signal receiving terminal; the output terminal of the third inverter F3 is electrically connected to the first terminal of the third resistor R3; the square wave signal receiving terminal is used to receive square wave signals; the second terminal of the third resistor R3 is electrically connected to the first terminal of the third capacitor C3, the first input terminal of the AND gate device M1, and the first input terminal of the NOR gate device M2; the second terminal of the third capacitor C3 is grounded; the AND gate... The second input terminal of device M1 is electrically connected to the square wave signal receiving terminal; the output terminal of AND gate device M1 is electrically connected to the first input terminal of voltage conversion submodule 41; the first output terminal of voltage conversion submodule 41 is electrically connected to the first input terminal of generation unit; the output terminal of generation unit is electrically connected to the input terminal of output unit; and the output terminal of output unit is used to be electrically connected to the gate of insulated gate bipolar transistor. The second input terminal of NOR gate device M2 is electrically connected to the square wave signal receiving terminal; the output terminal of NOR gate device M2 is electrically connected to the second input terminal of voltage conversion submodule 41; and the second output terminal of voltage conversion submodule 41 is electrically connected to the second input terminal of generation unit.

[0069] The initial square wave signal output from the microcontroller unit is filtered by the filtering module to generate a filtered square wave signal. The voltage conversion module increases the voltage of the filtered square wave signal to generate a square wave signal. The third inverter F3 receives the square wave signal and inverts it to generate a third inverted signal. The third resistor R3 and the third capacitor C3 work together to delay the third inverted signal to generate a processed signal. Then, the AND gate M1 generates a first narrow pulse signal to represent the rising edge of the square wave signal based on the square wave signal and the processed signal, and the NOR gate M2 generates a second narrow pulse signal to represent the falling edge of the square wave signal based on the square wave signal and the processed signal. The voltage conversion submodule 41 increases the voltage of the first narrow pulse signal to generate a third narrow pulse signal, and increases the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal. The generation unit generates an initial control signal based on the third and fourth narrow pulse signals. The output unit increases the current of the initial control signal to generate a control signal, which drives the insulated gate bipolar transistor.

[0070] Reference Figure 4 In some embodiments, Figure 4 (a1) shows the curve of the square wave signal in a coordinate system with voltage U on the vertical axis and time t on the horizontal axis. Figure 4 (a2) shows the curve of the third inverted signal in a coordinate system with voltage U on the vertical axis and time t on the horizontal axis (the curves of the first and second inverted signals are the same). Figure 4 (a3) shows the curve of the processed signal in a coordinate system with voltage U on the vertical axis and time t on the horizontal axis. Figure 4 (a4) is the curve of the first narrow pulse signal in a coordinate system with voltage U on the vertical axis and time t on the horizontal axis. Figure 4 (a5) is the curve of the second narrow pulse signal in a coordinate system with voltage U on the vertical axis and time t on the horizontal axis;

[0071] At time t1, the square wave signal curve changes from high level to low level, and the processed signal curve begins to rise; at time t2, the voltage of the processed signal reaches the low-level threshold u2 of the NOR gate device M2; at time t3, the square wave signal curve changes from low level to high level, and the processed signal curve begins to rise; at time t4, the voltage of the processed signal reaches the high-level threshold u1 of the AND gate device M1.

[0072] During the time interval from time t1 to time t2, since the square wave signal is at a low level and the processed signal is at a low level, the first narrow pulse signal is at a low level and the second narrow pulse signal is at a high level. During the time interval from time t2 to time t3, since the square wave signal is at a low level and the processed signal is at a high level, the first narrow pulse signal is at a low level and the second narrow pulse signal is at a low level. During the time interval from time t3 to time t4, since the square wave signal is at a high level and the processed signal is at a high level, the first narrow pulse signal is at a high level and the second narrow pulse signal is at a low level.

[0073] Optionally, refer to Figure 5 In some embodiments, the inverting delay module 10, the first generation module 20, and the second generation module 30 constitute a pulse generation circuit. The driving process of the insulated gate bipolar transistor includes: X1, start; X2, the microcontroller outputs an initial square wave signal; X3, the filtering module filters the initial square wave signal, that is, the filtering module removes noise from the initial square wave signal to generate a filtered square wave signal; X4, the voltage conversion module performs voltage conversion, that is, the voltage of the filtered square wave signal is increased by the voltage conversion module to generate a square wave signal; X5, the pulse generation circuit generates a first narrow pulse signal and a second narrow pulse signal, that is, the inverting delay module 10 receives the square wave signal, inverts and delays the square wave signal to generate a processed signal, and then the first generation module 20 receives the square wave signal and generates a signal to characterize the square wave based on the square wave signal and the processed signal. The rising edge of the signal is a first narrow pulse signal, and the square wave signal is received by the second generation module 30. Based on the square wave signal and the processed signal, a second narrow pulse signal is generated to characterize the falling edge of the square wave signal; X6, the voltage conversion submodule 41 performs voltage conversion, that is, the voltage of the first narrow pulse signal is increased by the voltage conversion submodule 41 to generate a third narrow pulse signal, and the voltage of the second narrow pulse signal is increased to generate a fourth narrow pulse signal; X7, the generation unit performs square wave conversion, that is, the generation unit generates an initial control signal based on the third narrow pulse signal and the fourth narrow pulse signal; X8, the output unit outputs the control signal, that is, the output unit increases the current of the initial control signal to generate a control signal; X9, the insulated gate bipolar transistor is driven to work, that is, the insulated gate bipolar transistor is driven to work by the control signal; X10, end.

[0074] In summary, in this embodiment, the square wave signal is received by the inverting delay module 10, and the square wave signal is inverted and delayed to generate a processed signal. Then, the square wave signal is received by the first generation module 20, and a first narrow pulse signal representing the rising edge of the square wave signal is generated based on the square wave signal and the processed signal. The square wave signal is received by the second generation module 30, and a second narrow pulse signal representing the falling edge of the square wave signal is generated based on the square wave signal and the processed signal. The voltage of the first narrow pulse signal is increased by the output module 40 to generate a third narrow pulse signal, and the voltage of the second narrow pulse signal is increased to generate a fourth narrow pulse signal. A control signal for driving the insulated gate bipolar transistor is generated based on the third and fourth narrow pulse signals. In this process, since the duty cycle of the narrow pulse signal is smaller than that of the square wave signal, the voltage conversion using the narrow pulse signal reduces the heat loss of the devices in the driving circuit compared to the prior art where voltage conversion is achieved using the square wave signal.

[0075] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0076] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A driving circuit for an insulated gate bipolar transistor, characterized in that, It includes an inverting delay module, a first generation module, a second generation module, and an output module; The inverting delay module is electrically connected to the first generation module and the second generation module respectively. The inverting delay module is used to receive the square wave signal, and to invert and delay the square wave signal to generate the processed signal. The first generation module is electrically connected to the output module. The first generation module is used to receive the square wave signal and generate a first narrow pulse signal to characterize the rising edge of the square wave signal based on the square wave signal and the processed signal. The second generation module is electrically connected to the output module. The second generation module is used to receive the square wave signal and generate a second narrow pulse signal to characterize the falling edge of the square wave signal based on the square wave signal and the processed signal. The output module is used to increase the voltage of the first narrow pulse signal to generate a third narrow pulse signal, and increase the voltage of the second narrow pulse signal to generate a fourth narrow pulse signal, and generate a control signal to drive the insulated gate bipolar transistor based on the third narrow pulse signal and the fourth narrow pulse signal.

2. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The inverting delay module includes a first inverting delay submodule and a second inverting delay submodule; The first inverting delay submodule is electrically connected to the first generation module. The first inverting delay submodule is used to receive the square wave signal, and to invert and delay the square wave signal to generate the processed signal. The second inverting delay submodule is electrically connected to the second generation module. The second inverting delay submodule is used to receive the square wave signal, invert and delay the square wave signal to generate the processed signal.

3. The driving circuit for the insulated gate bipolar transistor according to claim 2, characterized in that, The first inverting delay submodule includes a first inverter and a first delay unit; The first inverter is electrically connected to the first delay unit. The first inverter is used to receive the square wave signal and invert the square wave signal to generate a first inverted signal. The first delay unit is electrically connected to the first generation module. The first delay unit is used to delay the first inverted signal to generate the processed signal.

4. The driving circuit for the insulated gate bipolar transistor according to claim 3, characterized in that, The first delay unit includes a first resistor and a first capacitor; The input terminal of the first inverter is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the first inverter is electrically connected to the first terminal of the first resistor; the square wave signal receiving terminal is used to receive the square wave signal. The second end of the first resistor is electrically connected to the first end of the first capacitor and the first input end of the first generation module, respectively. The second terminal of the first capacitor is grounded; The second input terminal of the first generation module is electrically connected to the square wave signal receiving terminal.

5. The driving circuit for the insulated gate bipolar transistor according to claim 2, characterized in that, The second inverting delay submodule includes a second inverter and a second delay unit; The second inverter is electrically connected to the second delay unit. The second inverter is used to receive the square wave signal and invert the square wave signal to generate a second inverted signal. The second delay unit is electrically connected to the second generation module. The second delay unit is used to delay the second inverted signal to generate the processed signal.

6. The driving circuit for the insulated gate bipolar transistor according to claim 5, characterized in that, The second delay unit includes a second resistor and a second capacitor; The input terminal of the second inverter is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the second inverter is electrically connected to the first terminal of the second resistor; the square wave signal receiving terminal is used to receive the square wave signal. The second end of the second resistor is electrically connected to the first end of the second capacitor and the first input end of the second generation module, respectively. The second terminal of the second capacitor is grounded; The second input terminal of the second generation module is electrically connected to the square wave signal receiving terminal.

7. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The inverting delay module includes a third inverter and a delay submodule; The third inverter is electrically connected to the delay submodule. The third inverter is used to receive the square wave signal and invert the square wave signal to generate the third inverted signal. The delay submodule is electrically connected to the first generation module and the second generation module respectively. The delay submodule is used to delay the third inverted signal to generate the processed signal.

8. The driving circuit for the insulated gate bipolar transistor according to claim 7, characterized in that, The delay submodule includes a third resistor and a third capacitor; The input terminal of the third inverter is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the output terminal of the third inverter is electrically connected to the first terminal of the third resistor; the square wave signal receiving terminal is used to receive the square wave signal. The second end of the third resistor is electrically connected to the first end of the third capacitor, the first input end of the first generation module, and the first input end of the second generation module, respectively. The second terminal of the third capacitor is grounded; The second input terminal of the first generation module is electrically connected to the square wave signal receiving terminal; The second input terminal of the second generation module is electrically connected to the square wave signal receiving terminal.

9. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The first generation module includes an AND gate device; The input terminal of the inverting delay module is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the first output terminal of the inverting delay module is electrically connected to the first input terminal of the AND gate device; the square wave signal receiving terminal is used to receive the square wave signal. The second input terminal of the AND gate is electrically connected to the square wave signal receiving terminal, and the output terminal of the AND gate is electrically connected to the first input terminal of the output module.

10. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The second generation module includes NOR gate devices; The input terminal of the inverting delay module is electrically connected to the square wave signal receiving terminal of the driving circuit of the insulated gate bipolar transistor, and the second output terminal of the inverting delay module is electrically connected to the first input terminal of the NOR gate device; the square wave signal receiving terminal is used to receive the square wave signal. The second input terminal of the NOR gate is electrically connected to the square wave signal receiving terminal, and the output terminal of the NOR gate is electrically connected to the second input terminal of the output module.

11. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The output module includes a voltage conversion submodule and an output submodule; The voltage conversion submodule is electrically connected to the first generation module and the second generation module respectively. The voltage conversion submodule is used to increase the voltage of the first narrow pulse signal to generate the third narrow pulse signal, and increase the voltage of the second narrow pulse signal to generate the fourth narrow pulse signal. The output submodule is electrically connected to the voltage conversion submodule, and the output submodule is used to generate the control signal based on the third narrow pulse signal and the fourth narrow pulse signal.

12. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The driving circuit of the insulated gate bipolar transistor also includes a filtering module; The filtering module is electrically connected to the inverting delay module, the first generation module, and the second generation module, respectively. The filtering module is used to receive the initial square wave signal, filter the initial square wave signal, and generate the square wave signal.

13. The driving circuit for the insulated gate bipolar transistor according to claim 1, characterized in that, The duty cycle of the control signal is the same as that of the square wave signal, and the voltage of the control signal is greater than that of the square wave signal.

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