Timing adjustable high-low level alternate output circuit

Abstract

The utility model discloses a high-low level alternating output circuit with a timing adjustable function. The high-low level alternating output circuit comprises a multivibrator circuit, a counter group, a zero clearing signal circuit and a JK trigger group, wherein the multivibrator circuit is used for generating a pulse clock signal, and the output end of the multivibrator circuit is connected to the counter group; the counter group is used for timing output of high and low levels, the output end of the counter group is connected to the reset signal circuit, and the output end of the reset signal circuit is connected to the JK trigger group and used for driving the JK trigger group to trigger and output high and low level signals in a set time period. The utility model has the advantages that the timing output of multiple paths of high and low levels is realized through the digital circuit, and the circuit is simple and reliable. Multi-path timing output can be realized, the timing time is adjustable, and high and low levels can be circularly output.

Description

Technical Field

[0001] This utility model relates to the field of digital circuit design, and in particular to a high-low level alternating output circuit with adjustable timing. Background Technology

[0002] In the field of digital circuits, high and low level signals have a wide range of applications. They are commonly used for signal transmission, activation, and wake-up. The generation, output, and control of high and low level signals are crucial. For example, patent application number 201810591692.X discloses a logic circuit with three types of high and low level connection conditions. This circuit generates different high and low level signals from two transmitting terminals under three different connection conditions. By applying different high and low levels to Lin and Ri, Lut and Rou exhibit three different high and low level outputs. This can be used in basic computer addition calculations and in circuits requiring different paths under different connection conditions. High and low level control enables applications in specialized fields.

[0003] In the application and design of digital circuits, there is often a need for a circuit that can output high and low levels at specific pins at regular intervals. However, existing high and low level output control circuits cannot achieve the purpose of multiple outputs and timed interactive output of high and low levels, and cannot meet the output requirements of the digital circuit design field for high and low levels. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-low level alternating output circuit with adjustable timing. It realizes the timing output of multiple high and low levels through digital circuits, and the circuit is simple and reliable.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a high-low level alternating output circuit with adjustable timing, comprising a multivibrator circuit, a counter group, a clear signal circuit, and a JK flip-flop group; wherein the multivibrator circuit is used to generate a pulse clock signal, and its output terminal is connected to the counter group; the counter group is used to time the high and low level outputs, and its output terminal is connected to the clear signal circuit; the output terminal of the clear signal circuit is connected to the JK flip-flop group, and is used to drive the JK flip-flop group to trigger the output of high and low level signals within a set time period.

[0006] The multivibrator circuit includes a 555 timer A1. The RST and VCC pins of the 555 timer A1 are both connected to the power supply VCC. The power supply VCC is connected to the THR pin of the 555 timer A1 after passing through resistors R1 and R4 in series. A terminal is led out between resistors R1 and R4 and connected to the DIS pin of the 555 timer A1. The THR and TR1 pins of the 555 timer are both grounded through capacitor C1, and the CON pin is grounded through capacitor C2.

[0007] Alternatively, the VCC pin of the 555 timer can be connected to the power supply VCC, the RST pin can be connected to one end of the function generator, the other end of the function generator can be connected to the THR pin, the THR and TRI pins can be connected together and then connected to the DI S pin through resistor R4, the THR and TRI pins of the 555 timer can be grounded through capacitor C1, and the CON pin can be grounded through capacitor C2.

[0008] Alternatively, the VCC pin of the 555 timer can be connected to the power supply VCC, the RST pin can be connected to the THR pin via switch SA1, the THR and TRI pins can be connected together and then connected to the DIS pin via resistor R4, the THR and TRI pins of the 555 timer can be grounded through capacitor C1, and the CON pin can be grounded through capacitor C2.

[0009] The counter group includes three counter chips U1, U6, and U49. U1, U2, and U3 are all powered by VCC. The CLK pin of chip U1 is connected to the output OUT of 555 timer A1. The outputs QA and QD of chip U1 are connected to the input of NAND gate U2A. The outputs QB and QC of chip U1 are each connected to the input of NAND gate U2A via an NOT gate. The output of NAND gate U2A is connected to the CLK pin of chip U6. The outputs QA and QD of chip U6 are connected to the input of NAND gate U17A. The output QB of chip U6 is connected to the input of NAND gate U17A. QA and QC are each connected to the input of NAND gate U17A via an NOT gate. The output of NAND gate U17A is connected to the CLK pin of chip U49. The outputs QA and QD of chip U49 are connected to the input of NAND gate U50A. The outputs QB and QC of chip U49 are each connected to the input of NAND gate U50A via an NOT gate. The output of NAND gate U50A is connected to the ~LOAD pin of chip U49. The output of NAND gate U17A is connected to the ~LOAD pin of chip U6. The output of NAND gate U21 is connected to the ~LOAD pin of chip U1.

[0010] The reset signal circuit includes a first reset signal circuit, a second reset signal circuit, a third reset signal circuit, and a fourth reset signal circuit. The JK flip-flop group includes JK flip-flop chips U16, U68, U74, and U77. The first reset signal circuit has its SET pins grounded, and its J and K pins are connected to the power supply VCC.

[0011] The outputs of chips U1, U6, and U49 (QA, QB, QC, and QD) are respectively connected to the inputs of the first, second, third, and fourth reset signal circuits. The output of the first reset signal circuit is connected to the RESET pin of chip U16. The CLK pin of chip U16 is connected to the output of 555 timer A1. The output of the first reset signal circuit is connected to the CLK pin of chip U68 via NOT gate U85A. The RESET pin of chip U69 is connected to the output of the second reset signal circuit. The output of the second reset signal circuit is connected to the CLK pin of chip U74 via NOT gate U86A. The RESET pin of chip U74 is connected to the output of the third reset signal circuit. The output of the third reset signal circuit is connected to the CLK pin of chip U77 via NOT gate U87A. The RESET pin of chip U77 is connected to the fourth reset signal circuit.

[0012] The Q pins and ~Q pins of JK flip-flop chips U16, U68, U74, and U77 respectively lead out to level output terminals.

[0013] The first reset signal circuit includes NAND gates U3A, U12A, U88A, U10A, and NOT gate U7A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U3A after passing through a NOT gate. The outputs QA, QC, and QD of chip U6 are connected to the input of NAND gate U12A after passing through a NOT gate. The output QB of chip U6 is connected to the input of NAND gate U12A. The outputs QA, QB, QC, and QD of chip U49 are connected to the input of NAND gate U88A after passing through a NOT gate. The outputs of NAND gates U3A, U12A, and U88A are connected to the input of NAND gate U10A after passing through a NOT gate. The output of NAND gate U10A is led out to the output of the first reset signal circuit after passing through NOT gate U7A.

[0014] The second reset signal circuit includes NAND gates U29A, U30A, U79A, and U26A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U29A after passing through an NOT gate. The outputs QA, QB, and QC of chip U6 are connected to the input of NAND gate U30A after passing through an NOT gate, and the output QD of chip U6 is connected to the input of NAND gate U30A. The outputs QA, QB, QC, and QD of chip U49 are all connected to the input of NAND gate U79 after passing through an NOT gate. The outputs of NAND gates U29A, U30A, and U79A are connected to the input of NAND gate U26A after passing through an NOT gate, and the output of NAND gate U26A is led out to the output of the second reset signal circuit via NOT gate U73A.

[0015] The third reset signal circuit includes NAND gates U38A, U44A, U54A, and U76A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U38A after passing through an NAND gate. The outputs QB, QC, and QD of chip U6 are connected to the input of NAND gate U44A after passing through an NAND gate. The output QA of chip U6 is connected to the input of NAND gate U44A. The outputs QB, QC, and QD of chip U49 are connected to the input of NAND gate U54A after passing through an NAND gate. The output QA of chip U49 is connected to the input of NAND gate U54A. The outputs of NAND gates U38A, U44A, and U54A are connected to the input of NAND gate U76A after passing through an NAND gate. The output of NAND gate U76A is led out to the output of the third reset signal circuit after passing through NAND gate U75A.

[0016] The fourth reset signal circuit includes NAND gates U62A, U67A, U69A, and U42A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U62A after passing through an NOT gate. The outputs QA, QB, and QC of chip U6 are all connected to the input of NAND gate U67A. The output QD of chip U6 is connected to the input of NAND gate U67A after passing through an NOT gate U25A. The output QA of chip U49 is connected to one input of NAND gate U69. The outputs QB, QC, and QD of chip U49 are connected to the input of NAND gate U69A after passing through an NOT gate. NAND gates U62A, U67A, and U69A are connected to NAND gate U42A after passing through an NOT gate. The output of NAND gate U42A is led out to the output of the fourth reset signal circuit after passing through an NOT gate U78A.

[0017] The advantages of this invention are: it achieves multi-channel high and low level timing output through digital circuitry, and the circuitry is simple and reliable. It can achieve multi-channel timing output, with adjustable timing intervals and the ability to cycle through high and low levels. It can be used for tasks involving long-term repetitive tasks or fixed-time period settings. Attached Figure Description

[0018] The following is a brief explanation of the contents of each of the accompanying drawings and the markings in the drawings:

[0019] Figure 1 This is a schematic diagram illustrating the connection principle between the multivibrator circuit with a fixed unit timing length and the counter circuit in this utility model.

[0020] Figure 2 This is a schematic diagram of the multivibrator circuit of this utility model that uses an externally specified frequency signal;

[0021] Figure 3 This is a schematic diagram of the multivibrator circuit principle of this utility model, which uses a manually set unit timing length.

[0022] Figure 4 This is a schematic diagram of the first reset signal circuit in this utility model;

[0023] Figure 5 This is a schematic diagram of the second reset signal circuit in this utility model;

[0024] Figure 6 This is a schematic diagram of the third reset signal circuit in this utility model;

[0025] Figure 7 This is a schematic diagram of the fourth reset signal circuit in this utility model;

[0026] Figure 8 This is a schematic diagram showing the connection relationship between the reset circuit and the JK flip-flop circuit. Detailed Implementation

[0027] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and the description of the preferred embodiments.

[0028] This solution designs an integrated logic circuit based on a 555 timer and a JK flip-flop to achieve a timed output level for a specified pin during the timing period, thereby meeting the high and low level requirements of digital circuits. The specific solution is as follows: Figure 1-8 As shown, please note the following:

[0029] The circuit structure in this embodiment is described as follows: a timing-adjustable high / low level alternating output circuit includes a multivibrator circuit, a counter group, a clear signal circuit, and a JK flip-flop group. The multivibrator circuit generates a pulse clock signal, and its output is connected to the counter group and the first-stage JK flip-flop of the JK flip-flop group. The counter group times the high / low level output, and its output is connected to the clear signal circuit. The output of the clear signal circuit is connected to the JK flip-flop group, which drives the JK flip-flop group to trigger the output of high / low level signals within a set time period. The JK flip-flop group includes four stages of JK flip-flops, namely JK flip-flop chips U16, U68, U74, and U77. The counter group is essentially a state machine. It counts when a counting signal arrives, counts once more after reaching a transition state, and then returns to its initial state. It belongs to the state transition group of its own state machine and also serves as the inversion trigger signal for the next-level JK flip-flop. A clock signal is provided to the preset unit via a 555 timer, function generator, or key pulse signal. The preset unit operates in counting mode. The feedback preset logic combination at the preset unit's output is designed according to project requirements to set a fixed preset time for the required preset signal. Simultaneously, depending on whether it's a hundreds counter or a thousands counter, the preset unit's output feedback preset logic combination is cascaded again to match and set the output high-level duration. A JK flip-flop stores the level state until the terminal of the cascaded logic group outputs a high level, and then flips the level upon reaching the terminal high-level output.

[0030] like Figure 1 As shown, the multivibrator circuit includes a 555 timer A1. The RST and VCC pins of the 555 timer A1 are both connected to the power supply VCC. The power supply VCC is connected to the THR pin of the 555 timer A1 after passing through series resistors R1 and R4. A terminal is led out between resistors R1 and R4 and connected to the DIS pin of the 555 timer A1. The THR and TRI pins of the 555 timer are grounded through capacitor C1, and the CON pin is grounded through capacitor C2.

[0031] In a preferred embodiment, the multivibrator circuit is as follows: Figure 2 As shown, the VCC pin of the 555 timer is connected to the power supply VCC, the RST pin is connected to one end of the function generator, the other end of the function generator is connected to the THR pin, the THR and TR I pins are connected together and then connected to the DIS pin through resistor R4. The THR and TR I pins of the 555 timer are both grounded through capacitor C1, and the CON pin is grounded through capacitor C2.

[0032] In another alternative embodiment, the multivibrator circuit is as follows: Figure 3As shown, the VCC pin of the 555 timer is connected to the power supply VCC, the RST pin is connected to the THR pin via switch SA1, the THR and TR1 pins are connected together and then connected to the DI S pin via resistor R4, the THR and TR1 pins of the 555 timer are both grounded through capacitor C1, and the CON pin is grounded through capacitor C2.

[0033] like Figure 1 As shown, the counter group includes three counter chips U1, U6, and U49. U1, U2, and U3 are all powered by VCC. The CLK pin of chip U1 is connected to the output OUT of 555 timer A1. The outputs QA and QD of chip U1 are connected to the input of NAND gate U2A. The outputs QB and QC of chip U1 are each connected to the input of NAND gate U2A via an NOT gate. The output of NAND gate U2A is connected to the CLK pin of chip U6. The outputs QA and QD of chip U6 are connected to the input of NAND gate U17A. The output QB of chip U6 is connected to the input of NAND gate U17A. QA and QC are each connected to the input of NAND gate U17A via an NOT gate. The output of NAND gate U17A is connected to the CLK pin of chip U49. The outputs QA and QD of chip U49 are connected to the input of NAND gate U50A. The outputs QB and QC of chip U49 are each connected to the input of NAND gate U50A via an NOT gate. The output of NAND gate U50A is connected to the ~LOAD pin of chip U49. The output of NAND gate U17A is connected to the ~LOAD pin of chip U6. The output of NAND gate U21 is connected to the ~LOAD pin of chip U1.

[0034] like Figure 4-8 As shown, the reset signal circuit includes a first reset signal circuit, a second reset signal circuit, a third reset signal circuit, and a fourth reset signal circuit. The JK flip-flop group includes JK flip-flop chips U16, U68, U74, and U77. Figure 8As shown, the SET pins of JK flip-flop chips U16, U68, U74, and U77 are all grounded. The J and K pins of JK flip-flop chips U16, U68, U74, and U77 are all connected to the power supply VCC. The outputs of chips U1, U6, and U49 (QA, QB, QC, and QD) are respectively connected to the inputs of the first, second, third, and fourth reset signal circuits. The output of the first reset signal circuit is connected to the RESET pin of chip U16. The CLK pin of chip U16 is connected to... The output of the first reset signal circuit is connected to the output of the 555 timer A1; the output of the first reset signal circuit is connected to the CLK pin of the chip U68 via NOT gate U85A; the RESET pin of the chip U69 is connected to the output of the second reset signal circuit; the output of the second reset signal circuit is connected to the CLK pin of the chip U74 via NOT gate U86A; the RESET pin of the chip U74 is connected to the output of the third reset signal circuit; the output of the third reset signal circuit is connected to the CLK pin of the chip U77 via NOT gate U87A; and the RESET pin of the chip U77 is connected to the fourth reset signal circuit.

[0035] The Q pins and ~Q pins of JK flip-flop chips U16, U68, U74, and U77 respectively lead out to level output terminals.

[0036] like Figure 4 As shown, the first reset signal circuit includes NAND gates U3A, U12A, U88A, U10A, and NOT gate U7A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U3A after passing through a NOT gate. The outputs QA, QC, and QD of chip U6 are connected to the input of NAND gate U12A after passing through a NOT gate. The output QB of chip U6 is connected to the input of NAND gate U12A. The outputs QA, QB, QC, and QD of chip U49 are connected to the input of NAND gate U88A after passing through a NOT gate. The outputs of NAND gates U3A, U12A, and U88A are connected to the input of NAND gate U10A after passing through a NOT gate. The output of NAND gate U10A is led out to the output of the first reset signal circuit after passing through NOT gate U7A.

[0037] like Figure 5The second reset signal circuit shown includes NAND gates U29A, U30A, U79A, and U26A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U29A after passing through an NAND gate. The outputs QA, QB, and QC of chip U6 are connected to the input of NAND gate U30A after passing through an NAND gate, and the output QD of chip U6 is connected to the input of NAND gate U30A. The outputs QA, QB, QC, and QD of chip U49 are all connected to the input of NAND gate U79 after passing through an NAND gate. The outputs of NAND gates U29A, U30A, and U79A are connected to the input of NAND gate U26A after passing through an NAND gate, and the output of NAND gate U26A is led out to the output of the second reset signal circuit via NAND gate U73A.

[0038] like Figure 6 As shown, the third reset signal circuit includes NAND gates U38A, U44A, U54A, and U76A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U38A after passing through an NAND gate. The outputs QB, QC, and QD of chip U6 are connected to the input of NAND gate U44A after passing through an NAND gate. The output QA of chip U6 is connected to the input of NAND gate U44A. The outputs QB, QC, and QD of chip U49 are connected to the input of NAND gate U54A after passing through an NAND gate. The output QA of chip U49 is connected to the input of NAND gate U54A. The outputs of NAND gates U38A, U44A, and U54A are connected to the input of NAND gate U76A after passing through an NAND gate. The output of NAND gate U76A is led out to the output of the third reset signal circuit after passing through NAND gate U75A.

[0039] like Figure 7 As shown, the fourth reset signal circuit includes NAND gates U62A, U67A, U69A, and U42A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U62A after passing through an NOT gate. The outputs QA, QB, and QC of chip U6 are all connected to the input of NAND gate U67A. The output QD of chip U6 is connected to the input of NAND gate U67A after passing through an NOT gate U25A. The output QA of chip U49 is connected to one input of NAND gate U69. The outputs QB, QC, and QD of chip U49 are connected to the input of NAND gate U69A after passing through an NOT gate. NAND gates U62A, U67A, and U69A are connected to NAND gate U42A after passing through an NOT gate. The output of NAND gate U42A is led out to the output of the fourth reset signal circuit after passing through an NOT gate U78A.

[0040] This solution designs one main logic circuit integration scheme and two sub-logic circuit design schemes to achieve a timed output level of a specified pin within 1000 seconds, thus fulfilling the circuit design requirements of engineers.

[0041] The 555 timer is a versatile, medium-scale integrated circuit that combines digital and analog capabilities, with extremely wide applications. It is used not only for signal generation and transformation but also frequently in control and detection circuits. Due to its flexibility and ease of use, it has found widespread application in many fields, including waveform generation and exchange, measurement and control, home appliances, and electronic toys.

[0042] The JK flip-flop is a basic circuit unit in digital flip-flops. It has reset, set, hold, and toggle functions. Among various integrated flip-flops, the JK flip-flop has the most complete functionality. In practical applications, it not only has strong versatility but also can be flexibly converted into other types of flip-flops. D flip-flops and T flip-flops can be constructed from JK flip-flops.

[0043] In this embodiment, a 555 timer chip is used to construct a multivibrator circuit to generate pulses for use as a timing counting signal. An external signal source is used to set the unit timing length, and the occurrence and length of each unit timing are manually controlled. Three 74LS160 chips are used to construct a 1000-base counter for timing. In the third step, the required control time period is used as a reset signal to control the output state of the JK flip-flop. This circuit can be used to manufacture commonly used new chips for timing circuit design, and can be applied in waveform generation, shaping, and level driving.

[0044] This embodiment provides a circuit design and integration scheme based on a 555 timer, a JK flip-flop, a NAND gate, and a NAND gate, including: 1. a 555 timer; 2. a 170-ary adder counter; 3. a JK flip-flop; 4. a four-input NAND gate; 5. a three-input NAND gate; and 6. a NOT gate. The design of the clear signal input terminal of the JK flip-flop varies depending on different timing requirements. Figure 2 This is a NOT gate that short-circuits a specific branch within a specified time period. The short-circuit design concept is represented here by the on / off state of a switch connected in parallel with the NAND gate. When the switch connected in parallel with the NAND gate is closed, the NOT gate is short-circuited; when the switch connected in parallel with the NAND gate is open, the NOT gate operates normally and is not short-circuited.

[0045] The circuit in this scheme can achieve the following: QA pin outputs a high level within 0-20s, while other pins are low; QB pin outputs a high level within 20-80s, while other pins are low; QC pin outputs a high level within 80-110s, while other pins are low; QD pin outputs a high level within 110-170s, while other pins are low. The output states of QA', QB', QC', and QD' are the opposite of those of QA, QB, QC, and QD, respectively. The design based on the JK clear signal input can be modified according to the user's required high-level pin output time range.

[0046] like Figure 2 As shown, two additional external signal terminals, CLK1 and CLK2, are added for receiving external square wave signals, sine waves, or other signals with alternating zero and positive, zero and negative, or positive and negative potentials. Depending on the given frequency of the periodic signal, this circuit can operate within a specified unit timing length. For example... Figure 3 As shown, it provides a basis Figure 1 , Figure 1 In the absence of an external signal source, the RST terminal and the THR / TRI terminal can be switched on and off manually by connecting a toggle switch or button between the CLK1 and CLK2 terminals, thereby manually controlling the occurrence and length of each unit timing.

[0047] The circuit structure in this solution is simple and reliable. The specific circuit components involved are: 1. 555 timer; 2. 160 decimal adder counter; 3. JK flip-flop; 4. four-input NAND gate; 5. three-input NAND gate; 6. NOT gate. During integration and circuit construction, as long as the logic functions of the basic units are consistent, no specific model requirements are specified for the components.

[0048] Its working principle is as follows: all integrated chips in the overall circuit are powered by a 5V power supply. At the signal generation / input terminal of the circuit, such as... Figure 1 The A1 component uses a 555 timer chip to form a multivibrator circuit. In this circuit, the duty cycle of the generated clock signal can be changed by adjusting the values ​​of R1, R4, and C1, thus defining the duration of a single clock cycle: high-level time T1 = (R1 + R4)C1 ln2, low-level time T2 = R2C1 ln2. If a precise clock source is available but the 555 timer is not used, a more precise clock source can be used... Figure 2 The method of connecting an external function signal generator is used for clock timing calibration of the overall circuit. If neither of these hardware components is available, it can be done as follows: Figure 3As shown, a button is connected in series between CLK2 and CLK1. Based on the impedance divider principle of R4 and C1, pressing the button conducts, making the RST pin high, causing a falling edge at the A1 output. Releasing the button generates a rising edge at the A1 output. The clock period depends on the frequency of manually pressing and releasing the button. The clock signal generated by the pre-amplifier circuit provides a counting signal for U1 in counting mode. Transition states are designed at its four outputs QA, QB, QC, and QD. As shown in the diagram, when QA, QB, QC, and QD = 1001, U6 receives a counting signal from the CLK pin, and U1 restarts its counting cycle from QA, QB, QC, and QD = 0000 to QA, QB, QC, and QD = 1001, repeatedly resetting to zero. U49 starts counting once when U6 reaches the transition state QA, QB, QC, and QD = 1001, while U6 is reset to zero. Because U1, U6, and U49 are all counters with a total of 10 states (QA QB QC QD = 0000 to QA QB QC QD = 1001), cascading U1, U6, and U49 results in a 10 x 10 x 10 = 1000 base counter. Following the same logic, a logic group with state transitions is designed in the next stage of the circuit. As shown in the diagram, the JK flip-flop chip U16 is set to operate in counting mode, with the SET pin always active, and grounded in the diagram. The units digit is extracted from the four-bit output of U1, the tens digit from the four-bit output of U6, and the hundreds digit from the four-bit output of U49. When U10A reaches a non-desired state group (where 1C 1B 1A = 010 for U10A, 1D 1C 1B 1A = 0000 for U4A (units digit), 1D 1C 1B 1A = 0010 for U13A (tens digit), and 1D 1C 1B 1A = 0000 for U88A (hundreds digit), i.e., at the 20th state, its U7A terminal outputs a low level, setting the Q input of U16 to 0), the inverter outputs a high level to the REST terminal. At this time, SET = 0, REST = 1, causing the QA input of U16 to directly output a low level, causing it to flip from high to low at 20 seconds. Simultaneously, the inverter U85A provides a counting signal to U68. In the initial state, the JK flip-flop remains in its initial state, with the Q input outputting a low level, only flipping to a high level when the first clock signal arrives. Similarly, the logic group for the pre-stage state transition of the REEST pin of U68 is designed so that when 1C1 B1A = 010 in U26A (i.e., state 80), the pre-stage needs to go through 80 clock cycles. Within 20s-80s, the QB pin of U68 outputs a high level, and in state 80, it provides a clock signal to U74. This cyclical design sequentially causes the QC pin of U74 to output a high level within 80-110s, and the QD pin of U74 to output a high level within 110-170s.

[0049] Obviously, the specific implementation of this invention is not limited to the above-described methods. Any non-substantial improvements made using the inventive concept and technical solution of this invention are within the protection scope of this invention.

Claims

1. A timing-adjustable high / low level alternating output circuit, characterized in that: Includes a multivibrator circuit, a counter group, a reset signal circuit, and a JK flip-flop group; The multivibrator circuit is used to generate a pulse clock signal, and its output is connected to a counter group. The counter group is used to time the high and low level outputs, and its output is connected to a reset signal circuit. The output of the reset signal circuit is connected to a JK flip-flop group, which is used to drive the JK flip-flop group to trigger the output of high and low level signals within a set time period.

2. The high-low level alternating output circuit with adjustable timing as described in claim 1, characterized in that: The multivibrator circuit includes a 555 timer A1. The RST and VCC pins of the 555 timer A1 are both connected to the power supply VCC. The power supply VCC is connected to the THR pin of the 555 timer A1 after passing through series resistors R1 and R4. A terminal is led out between resistors R1 and R4 and connected to the DIS pin of the 555 timer A1. The THR and TRI pins of the 555 timer are both grounded through capacitor C1, and the CON pin is grounded through capacitor C2. Alternatively, the VCC pin of the 555 timer can be connected to the power supply VCC, the RST pin can be connected to one end of the function generator, the other end of the function generator can be connected to the THR pin, the THR and TRI pins can be connected together and then connected to the DIS pin through resistor R4, the THR and TRI pins of the 555 timer can be grounded through capacitor C1, and the CON pin can be grounded through capacitor C2. Alternatively, the VCC pin of the 555 timer can be connected to the power supply VCC, the RST pin can be connected to the THR pin via switch SA1, the THR and TRI pins can be connected together and then connected to the DIS pin via resistor R4, the THR and TRI pins of the 555 timer can be grounded through capacitor C1, and the CON pin can be grounded through capacitor C2.

3. A timing-adjustable high / low level alternating output circuit as described in claim 1 or 2, characterized in that: The counter group includes three counter chips U1, U6, and U49. These three chips combine and count the pulse signals output from the pulse clock signal circuit, forming a drive signal to the clear signal circuit. U1, U2, and U3 are all powered by VCC. The CLK pin of chip U1 is connected to the output OUT of the 555 timer A1. The outputs QA and QD of chip U1 are connected to the input of NAND gate U2A. The outputs QB and QC of chip U1 are each connected to the input of NAND gate U2A via an NOT gate. The output of NAND gate U2A is connected to the CLK pin of chip U6. The outputs QA and QD of chip U6... The outputs QB and QC of chip U6 are connected to the input of NAND gate U17A via an NOT gate. The output of NOT gate U17A is connected to the CLK pin of chip U49. The outputs QA and QD of chip U49 are connected to the input of NAND gate U50A. The outputs QB and QC of chip U49 are connected to the input of NAND gate U50A via an NOT gate. The output of NAND gate U50A is connected to the ~LOAD pin of chip U49. The output of NAND gate U17A is connected to the ~LOAD pin of chip U6. The output of NAND gate U21 is connected to the ~LOAD pin of chip U1.

4. The high-low level alternating output circuit with adjustable timing as described in claim 3, characterized in that: The reset signal circuit has four branches, namely the first reset signal circuit, the second reset signal circuit, the third reset signal circuit, and the fourth reset signal circuit. Each reset signal circuit corresponds to the action of one JK flip-flop in a JK flip-flop group and is used to drive the JK flip-flop group to trigger the output of high and low level signals within a set time period.

5. A timing-adjustable high / low level alternating output circuit as described in claim 4, characterized in that: The JK flip-flop group includes JK flip-flop chips U16, U68, U74, and U77. The SET pins of JK flip-flop chips U16, U68, U74, and U77 are all grounded, and the J pins and K pins of JK flip-flop chips U16, U68, U74, and U77 are all connected to the power supply VCC. The outputs of chips U1, U6, and U49 (QA, QB, QC, and QD) are respectively connected to the inputs of the first, second, third, and fourth reset signal circuits. The output of the first reset signal circuit is connected to the RESET pin of chip U16. The CLK pin of chip U16 is connected to the output of 555 timer A1. The output of the first reset signal circuit is connected to the CLK pin of chip U68 via NOT gate U85A. The RESET pin of chip U69 is connected to the output of the second reset signal circuit. The output of the second reset signal circuit is connected to the CLK pin of chip U74 via NOT gate U86A. The RESET pin of chip U74 is connected to the output of the third reset signal circuit. The output of the third reset signal circuit is connected to the CLK pin of chip U77 via NOT gate U87A. The RESET pin of chip U77 is connected to the fourth reset signal circuit. The Q pins and ~Q pins of JK flip-flop chips U16, U68, U74, and U77 respectively lead out to level output terminals.

6. The high-low level alternating output circuit with adjustable timing as described in claim 4, characterized in that: The first reset signal circuit includes NAND gates U3A, U12A, U88A, U10A, and NOT gate U7A. The outputs QA, QB, QC, and QD of chip U1 are connected to the input of NAND gate U3A after passing through a NOT gate. The outputs QA, QC, and QD of chip U6 are connected to the input of NAND gate U12A after passing through a NOT gate. The output QB of chip U6 is connected to the input of NAND gate U12A. The outputs QA, QB, QC, and QD of chip U49 are connected to the input of NAND gate U88A after passing through a NOT gate. The outputs of NAND gates U3A, U12A, and U88A are connected to the input of NAND gate U10A after passing through a NOT gate. The output of NAND gate U10A is led out to the output of the first reset signal circuit after passing through NOT gate U7A.

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