Surface assembly and component high-density interconnection packaging structure

Abstract

The utility model is suitable for the technical field of semiconductor packaging, and provides a surface assembly and component high-density interconnection packaging structure, which comprises a first substrate and two groups of second substrates connected with the first substrate, and filling layers are arranged between the first substrate and the second substrates and between the second substrates. The second substrate comprises a plane part and connecting parts arranged at the two ends of the plane part, a third mounting surface and a fourth mounting surface are arranged on the two sides of the plane part respectively, chips can be mounted on the third mounting surface and the fourth mounting surface, and heat dissipation pieces are arranged between the chips and the third mounting surface. According to the device, the problem that the assembly density of plane assembly is difficult to improve is solved, and the effect of ensuring the heat dissipation capability of the components of the packaging structure on the basis of realizing multi-layer stacking of the components and improving the assembly density is achieved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and more specifically, to surface mount and high-density interconnection packaging structures for components. Background Technology

[0002] Semiconductor packaging technology is a key step in the semiconductor manufacturing process. It not only protects the chip from physical and chemical damage, but also ensures the effective connection between the chip and other electronic components.

[0003] Conventional semiconductor packaging uses MCM technology, which is a two-dimensional planar technology. It encapsulates multiple bare IC chips, plastic-encapsulated devices, or chip devices by tightly arranging them on a planar substrate.

[0004] While this packaging technology has already approached its theoretical maximum packaging density, the assembly density of conventional MCM (Mechanical Controlled Molding) packaging structures is relatively low, leaving room for further improvement. To further increase assembly density and reduce volume, dense stacking along the Z-axis can be achieved to create multi-layer structures. However, this high-density assembly method places higher demands on heat dissipation between components. Therefore, during assembly, it is necessary not only to increase the component assembly density but also to ensure good heat dissipation performance of the components within the packaging structure. Utility Model Content

[0005] To address the shortcomings of existing technologies, the purpose of this utility model is to provide a surface assembly and high-density interconnection packaging structure that achieves multi-layer stacking of components, increases assembly density, and ensures heat dissipation capability of the packaged components.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A surface mount and high density interconnect package structure for components includes a first substrate and two sets of second substrates connected to the first substrate. A filler layer is provided between the first substrate and the second substrate, and between the second substrate and the second substrate. The second substrate includes a planar portion and connecting portions provided at both ends of the planar portion. The two sides of the planar portion are respectively provided as a third mounting surface and a fourth mounting surface. Chips can be mounted on both the third mounting surface and the fourth mounting surface. A heat sink is provided between the chip and the third mounting surface.

[0008] The present invention is further configured such that the side of the first substrate away from the second substrate is configured as the second mounting surface, and the side closer to the second substrate is configured as the first mounting surface.

[0009] The present invention is further configured such that: multiple sets of first connection points are symmetrically arranged at both ends of the second mounting surface, and multiple sets of second connection points are arranged in the middle of the second mounting surface; the first connection points are connected to the second substrate, and the second connection points are connected to the chip.

[0010] The present invention is further configured such that: multiple sets of leads are equidistantly arranged on the first mounting surface.

[0011] The present invention is further configured such that: the third mounting surface is disposed on the side of the planar portion close to the connecting portion, the fourth mounting surface is disposed on the side of the planar portion away from the connecting portion, and a filling layer is disposed inside the cavity formed by the third mounting surface.

[0012] The present invention is further configured such that: multiple sets of third connection points are equidistantly arranged at both ends of the connecting portion, and multiple sets of fourth connection points are arranged in the middle of the planar portion.

[0013] By adopting the above technical solution, when the second substrate needs to be connected to another group of second substrates, each group of third connection points is connected to the second substrate, thereby realizing the electrical connection between the two groups of second substrates through the connection of the third connection points to the planar portion of the other group of second substrates.

[0014] The present invention is further configured such that the chip includes a first chip installed inside a first substrate and a second substrate, and a second chip and a third chip installed inside two sets of second substrates.

[0015] The present invention is further configured such that: the second chip is mounted on the fourth mounting surface, the third chip is mounted on the third mounting surface, and a filling layer is provided between the second chip and the third chip.

[0016] The present invention is further configured such that: the heat sink includes a first heat sink strip disposed on the top of the first chip and a second heat sink strip disposed on the top of the second chip; the first heat sink strip is connected to a third mounting surface on a set of planar portions; and the second heat sink strip is connected to a third mounting surface on another set of planar portions.

[0017] The present invention is further configured such that: the first heat sink and the second heat sink are each provided with multiple sets at equal intervals along the length direction of the planar portion, and the first heat sink and the second heat sink are each provided with a bent portion along their length direction.

[0018] By adopting the above technical solution, the cross-sectional area of ​​the first and second heat sinks can be further increased by setting the bending portion, thereby increasing the area for heat conduction by the first and second heat sinks and achieving the purpose of increasing heat dissipation. By setting a heat sink between the chip and the filler layer that can be directly connected to the second substrate, the heat generated by the chip is directly conducted to the second substrate using the heat sink. Its conduction efficiency is much higher than that of conduction through the filler layer, thereby ensuring that heat dissipation can be carried out normally after the chip assembly density is increased.

[0019] The beneficial effects of this utility model are:

[0020] 1. By mounting chips in different positions and quantities between the first substrate and the second substrate, and between the second substrate and the second substrate, the mounting positions and quantities of the chips are changed, thereby increasing the chip mounting density based on increasing the number of mounting layers.

[0021] 2. By mounting a second substrate on top of the first substrate and continuing to mount other second substrates on top of the second substrate, spatial stacking between different substrates can be achieved, thereby realizing the mounting connection of multiple substrates, thereby increasing the chip mounting space in three dimensions and achieving the purpose of increasing chip mounting density. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This is a schematic diagram of the surface mount and high-density interconnect packaging structure of the present invention.

[0024] Figure 2 for Figure 1 The diagram shows the structure of the first substrate and the second substrate connected together.

[0025] Figure 3 for Figure 1 The diagram shows a structural schematic of the connection between the first substrate and the first substrate.

[0026] Figure 4 for Figure 2 The diagram shows a structural schematic of the connection between the first substrate and the second substrate from another perspective.

[0027] Explanation of reference numerals in the attached drawings: 1. First substrate; 11. Lead wire; 12. First mounting surface; 13. Second mounting surface; 14. First connection point; 15. Second connection point;

[0028] 2. Second substrate; 21. Planar portion; 22. Connecting portion; 23. Third mounting surface; 24. Fourth mounting surface; 25. Third connection point; 26. Fourth connection point;

[0029] 3. Chip; 31. First chip; 32. Second chip; 33. Third chip;

[0030] 4. Heat sink; 41. First heat sink strip; 42. Second heat sink strip; 43. Bending section;

[0031] 5. Filler layer. Detailed Implementation

[0032] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will now be described in detail with reference to the accompanying drawings. This drawing is a simplified schematic diagram, illustrating only the basic aspects of the present utility model, and therefore only shows the components relevant to the present utility model. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0033] Please refer to Figure 1-4 The system includes a first substrate 1 and two sets of second substrates 2 connected to the first substrate 1. The first substrate 1 and the second substrate 2 are electrically connected to each other. A mounting chip 3 and a heat sink 4 are disposed between the first substrate 1 and the second substrate 2, and between the second substrate 2 and the second substrate 2, thereby increasing the assembly density of the mounting chip 3 while dissipating heat from the mounting chip 3. A filler layer 5 is disposed between the first substrate 1 and the second substrate 2, and between the second substrate 2 and the second substrate 2, providing protection and buffering for the mounting chip 3 and the heat sink 4 inside the first substrate 1 and the second substrate 2, ensuring that the mounting chip 3 and the heat sink 4 are not damaged.

[0034] Please refer to Figure 1-2 The first substrate 1 has a second mounting surface 13 on the side away from the second substrate 2 and a first mounting surface 12 on the side closer to the second substrate 2. Multiple sets of first connection points 14 are symmetrically arranged at both ends of the second mounting surface 13, extending along the width of the second mounting surface 13. Each set of first connection points 14 is connected to the second substrate 2, achieving electrical connection between the first substrate 1 and the second substrate 2 through multiple sets of first connection points 14. Multiple sets of second connection points 15 are arranged in the middle of the second mounting surface 13, arranged in multiple rows along the width of the second mounting surface 13. Each set of second connection points 15 is connected to the chip 3, achieving electrical connection between the first substrate 1 and the chip 3 through multiple sets of second connection points 15. Multiple sets of leads 11 are equidistantly arranged on the first mounting surface 12. The leads 11 are connected to the first mounting surface 12 on the first substrate 1 by soldering, thereby achieving interlayer signal interconnection after the assembly of each substrate layer.

[0035] Please refer to Figure 1-4 The second substrate 2 includes a planar portion 21 and connecting portions 22 disposed at both ends of the planar portion 21. The connecting portions 22 are formed by bending downwards from all sides of the planar portion 21, thus giving the second substrate 2 an approximate U-shaped structure. A third mounting surface 23 and a fourth mounting surface 24 are respectively provided on both sides of the planar portion 21. The third mounting surface 23 is disposed on the side of the planar portion 21 closer to the connecting portion 22, and the fourth mounting surface 24 is disposed on the side of the planar portion 21 away from the connecting portion 22. Chips 3 can be mounted on both the third mounting surface 23 and the fourth mounting surface 24, thereby increasing the mounting positions and assembly methods of the chips 3, ultimately improving the assembly density of the chips 3. A filling layer 5 is disposed inside the cavity formed by the third mounting surface 23. After the chips 3 are installed inside the second substrate 2, the filling layer 5 can fully enclose and protect the chips 3.

[0036] Please refer to Figure 1-4 Multiple sets of third connection points 25 are equidistantly arranged at both ends of the connecting portion 22. These third connection points 25 are arranged along the width direction of the second substrate 2. When the second substrate 2 needs to be connected to another set of second substrates 2, each set of third connection points 25 connects to the second substrate 2, thereby achieving an electrical connection between the two sets of second substrates 2 through the connection between the third connection points 25 and the planar portion 21 of the other set of second substrates 2. It should be noted that in this embodiment, the number of interconnected second substrates 2 is two layers; this number is merely an example illustrating the connection method of the two sets of second substrates 2. In other embodiments, the number of interconnected second substrates 2 may be three, four, or more layers. Multiple sets of fourth connection points 26 are arranged in the middle of the planar portion 21, arranged in multiple columns along the width direction of the second substrate 2. When the second substrate 2 needs to be connected to another set of second substrates 2, each set of fourth connection points 26 connects to the chip 3 inside the other set of second substrates 2, thereby achieving an electrical connection between the second substrate 2 and the internal chip 3 through the connection between the fourth connection points 26 and the internal chip 3 of the other set of second substrates 2.

[0037] Please refer to Figure 1-4Chip 3 includes a first chip 31 installed inside a first substrate 1 and a second substrate 2, and a second chip 32 and a third chip 33 installed inside two sets of second substrates 2. When the first substrate 1 and the second substrate 2 are connected, the first chip 31 can be connected to the first mounting surface 12 via multiple sets of second connection points 15, thereby achieving an electrical connection between the first substrate 1 and the first chip 31. When the two sets of second substrates 2 are connected, the second chip 32 and the third chip 33 can be selectively installed inside the cavity formed between the two sets of second substrates 2. In this embodiment, the second chip 32 is installed on the fourth mounting surface 24, and is connected to the plane portion 21 via multiple sets of third connection points 25 on the plane portion 21, thereby achieving an electrical connection between the second chip 32 and the second substrate 2. In this embodiment, the third chip 33 is installed on the third mounting surface 23, and the third chips 33 are symmetrically arranged in two sets about the axis of the second substrate 2. The electrical connection between the third chip 33 and the second substrate 2 is achieved through a three-dimensional connection between the third chip 33 and the third mounting surface 23. It should be noted that in this embodiment, the mounting positions and quantities of the first chip 31, the second chip 32, and the third chip 33 are merely examples of different mounting positions and quantities of the chips 3. In other embodiments, the mounting positions and quantities of the first chip 31, the second chip 32, and the third chip 33 can be changed, thereby achieving changes in the mounting positions and quantities of the different chips 3. A filling layer 5 is provided between the second chip 32 and the third chip 33. When the two sets of second substrates 2 are connected, the filling layer 5 can fully enclose and protect the second chip 32 and the third chip 33 mounted inside the two sets of second substrates 2.

[0038] Specifically, by mounting a second substrate 2 on top of the first substrate 1 and continuing to mount other second substrates 2 on top of the second substrate 2, spatial stacking between different substrates can be achieved, thereby realizing the mounting connection of multiple substrates, thereby increasing the mounting space of the chip 3 in three dimensions and achieving the purpose of increasing the mounting density of the chip 3.

[0039] Furthermore, by mounting chips 3 in different positions and in different numbers between the first substrate 1 and the second substrate 2, and between the second substrate 2 and the second substrate 2, the mounting position and number of chips 3 can be changed, thereby increasing the mounting density of chips 3 on the basis of increasing the number of mounting layers.

[0040] Please refer to Figure 1-4A heat sink 4 is provided between chip 3 and the third mounting surface 23. The heat sink 4 enables the connection between chip 3 and the second substrate 2, facilitating heat dissipation of chip 3. The heat sink 4 includes a first heat sink 41 disposed on the top of the first chip 31 and a second heat sink 42 disposed on the top of the second chip 32. The first heat sink 41 is connected to the third mounting surface 23 on a set of planar portions 21. Multiple sets of first heat sink 41 are equidistantly arranged along the length of the planar portions 21. The first heat sink 41 enables the connection between the first chip 31 and the second substrate 2, allowing the heat generated by the first chip 31 to be directly conducted to the second substrate 2 through the first heat sink 41. Its conduction efficiency is much higher than that of conduction through the filler layer 5. The second heat sink 42 is connected to the third mounting surface 23 on another set of planar portions 21. Multiple sets of the second heat sink 42 are equidistantly arranged along the length of the planar portion 21. The second heat sink 42 enables the connection between the second chip 32 and the second substrate 2, allowing the heat generated by the second chip 32 to be directly conducted to the second substrate 2. This conduction efficiency is far higher than that achieved through the filling layer 5. Both the first heat sink 41 and the second heat sink 42 have bending portions 43 along their length. These bending portions 43 further increase the cross-sectional area of ​​the first and second heat sinks 41 and 42, thereby increasing the area for heat conduction and achieving increased heat dissipation. It should be noted that the connection positions and installation relationships between the first and second heat sinks 41 and 42 and different chips 3 in this embodiment are merely examples illustrating different arrangements of the heat sink 4 on different chips 3. In other embodiments, the connection positions and installation relationships of the heat sink 4 on different chips 3 can also be changed, thereby changing the arrangement of the heat sink 4.

[0041] Specifically, by setting a heat sink 4 that can be directly connected to the second substrate 2 between the chip 3 and the filling layer 5, the heat generated by the chip 3 is directly conducted to the second substrate 2 using the heat sink 4. Its conduction efficiency is much higher than that of conduction through the filling layer 5, thereby ensuring that the chip 3 can dissipate heat normally after the assembly density is increased.

[0042] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0043] It should be understood that the terms "length", "width", "up", "down", "front and back", "left and right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0044] Based on the preferred embodiments of this utility model described above, those skilled in the art can make various changes and modifications without departing from the scope of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A surface mount and high-density interconnect package structure for components, characterized in that: The system includes a first substrate (1) and two sets of second substrates (2) connected to the first substrate (1). A filling layer (5) is provided between the first substrate (1) and the second substrate (2) and between the second substrate (2) and the second substrate (2). The second substrate (2) includes a planar portion (21) and a connecting portion (22) provided at both ends of the planar portion (21). The two sides of the planar portion (21) are respectively provided as a third mounting surface (23) and a fourth mounting surface (24). Chips (3) can be mounted on both the third mounting surface (23) and the fourth mounting surface (24). A heat sink (4) is provided between the chip (3) and the third mounting surface (23).

2. The surface mount and high-density interconnect packaging structure for components according to claim 1, characterized in that: The side of the first substrate (1) away from the second substrate (2) is configured as the second mounting surface (13), and the side closer to the second substrate (2) is configured as the first mounting surface (12).

3. The surface mount and high-density interconnect packaging structure for components according to claim 2, characterized in that: The second mounting surface (13) has multiple sets of first connection points (14) symmetrically arranged at both ends, and multiple sets of second connection points (15) arranged in the middle of the second mounting surface (13). The first connection points (14) are connected to the second substrate (2), and the second connection points (15) are connected to the chip (3).

4. The surface mount and high-density interconnect packaging structure for components according to claim 3, characterized in that: Multiple sets of leads (11) are equidistantly arranged on the first mounting surface (12).

5. The surface mount and high-density interconnect packaging structure for components according to claim 1, characterized in that: The third mounting surface (23) is disposed on the side of the planar portion (21) near the connecting portion (22), and the fourth mounting surface (24) is disposed on the side of the planar portion (21) away from the connecting portion (22). The cavity formed by the third mounting surface (23) is provided with a filling layer (5).

6. The surface mount and high-density interconnect packaging structure for components according to claim 5, characterized in that: Multiple sets of third connection points (25) are equidistantly arranged at both ends of the connecting part (22), and multiple sets of fourth connection points (26) are arranged in the middle of the planar part (21).

7. The surface mount and high-density interconnect packaging structure for components according to claim 1, characterized in that: The chip (3) includes a first chip (31) installed inside the first substrate (1) and the second substrate (2), and a second chip (32) and a third chip (33) installed inside the two sets of second substrates (2).

8. The surface mount and high-density interconnect packaging structure for components according to claim 7, characterized in that: The second chip (32) is mounted on the fourth mounting surface (24), and the third chip (33) is mounted on the third mounting surface (23). A filler layer (5) is provided between the second chip (32) and the third chip (33).

9. The surface mount and high-density interconnect packaging structure for components according to claim 8, characterized in that: The heat sink (4) includes a first heat sink (41) disposed on the top of the first chip (31) and a second heat sink (42) disposed on the top of the second chip (32). The first heat sink (41) is connected to a third mounting surface (23) on a set of planar portions (21), and the second heat sink (42) is connected to a third mounting surface (23) on another set of planar portions (21).

10. The surface mount and high-density interconnect packaging structure for components according to claim 9, characterized in that: The first heat sink (41) and the second heat sink (42) are provided in multiple sets at equal intervals along the length direction of the planar portion (21), and the first heat sink (41) and the second heat sink (42) are provided with bent portions (43) along their length direction.

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