Sonar receiver and transmit-receive isolation circuit testing device

Abstract

A sonar receiver and transmit-receive isolation circuit testing device mainly comprises two pairs of connectors, a plurality of voltage-stabilized power supply chips, an FPGA chip, a storage chip, double-row in-line pins and a plurality of jumper caps which are all arranged on a printed circuit board (PCB). The device can carry out single-board testing on the transceiving isolation board and the receiver board, and is beneficial to positioning of problems during testing; a test wire does not need to be welded on the tested board, so that the damage such as short circuit possibly caused by an external lead to the board is avoided; test channels can be flexibly selected, and single-channel or multi-channel test can be realized; the whole test can be carried out on the PCB, the operation is simple, and the reliability is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sonar, in particular to a sonar receiver and transceiver isolation circuit testing device. BACKGROUND

[0002] The acoustic self-homing head is installed on the underwater vehicle carrier, and is used for detecting, identifying and positioning tracking of underwater dynamic targets. The acoustic self-homing head is mainly composed of an acoustic array, a mechanical structure, a transceiver isolation plate, a receiver plate, a system plate and a transmitting plate. The acoustic array is usually composed of dozens of array elements. Taking a 32-array element array as an example, the array elements are independent of each other. Each circuit board has 32 array element data processing modules. When the circuit board is welded and single board testing is performed, 32 test lines need to be led out on the board. When the single board testing is completed, the leads need to be removed. This repeated welding and removal of the circuit board may cause damage to the board, increase the workload and reduce the work efficiency. In addition, the test lines are easy to cause short circuit of the board, which brings uncertainty to the testing. SUMMARY

[0003] In view of the above problems, the utility model provides a kind of sonar receiver and transceiver isolation circuit testing device, mainly for the testing of transceiver isolation plate and receiver plate, it is simple to operate, and it is practical, and safety factor is high, can effectively carry out single board testing.

[0004] The sonar receiver and transceiver isolation circuit testing device provided by the present application mainly comprises: two pairs of connectors, a plurality of voltage stabilizing power supply chips, an FPGA chip, a storage chip, a double-row in-line pin, and a plurality of jumper caps, all of which are arranged on a PCB (Printed Circuit Board or Printed Wiring Board). Wherein:

[0005] The double-row in-line pin is provided with a signal input pad for connection with an external signal generator. One column of the double-row in-line pin is connected with the signal input pad. The other column is connected with the external receiver plate or transceiver isolation plate through the connector. The jumper cap is used for insertion with the double-row in-line pin to select which signal to test.

[0006] One pair of connectors is used to connect with the transceiver isolation plate and transmit test signals and PWM wave signals to the transceiver isolation plate.

[0007] The other pair of connectors is used to connect with the sonar receiver plate and transmit test input signals of different frequencies and amplitudes to the receiver plate.

[0008] The voltage stabilizing power supply chip is used to supply power to the FPGA chip and the receiver plate.

[0009] The FPGA chip and the storage chip are used to send PWM wave signals to the transceiver isolation plate.

[0010] Further, the double-row inline pins adopt two 2*16 double-row inline pins, and the jumper cap is provided with 32 jumper caps.

[0011] The left sides of the two pins respectively lead out 16 signals as a network signal signal_in, a signal_in signal line is led out in the test board and connected with the signal output positive terminal of a signal generator, a ground wire is led out in the test board and connected with the ground of the signal generator, and the signal generator outputs a sine wave signal signal_in with different frequencies and different amplitudes according to requirements;

[0012] The right sides of the two pins respectively lead out 32 signals as test input signals of a receiver board and a transceiver isolation board.

[0013] The jumper cap is plugged with the two pins as required, and is used for selecting one or multiple signal_in signals to enter the transceiver isolation board or the receiver board for signal testing.

[0014] Further, the double-row inline pins are welded on the back of the PCB board.

[0015] Among the two pairs of connectors, one pair of connectors is placed on the front of the PCB board and distributed on the left and right sides of the front, and the other pair of connectors is placed on the back of the PCB board and distributed on the left and right sides of the back.

[0016] The voltage stabilizing chip is arranged on the front of the PCB board.

[0017] The FPGA chip and the storage chip are arranged on the back of the PCB board.

[0018] Further, the test board is provided with four voltage stabilizing power supply chips, which respectively output 12V, 5V, 3.3V and 1.2V voltages, an external power supply supplies power to the test board at 12V, the 12V voltage output by the voltage stabilizing chip is used for power supply of the receiver board, and the 3.3V and 1.2V voltages output by the voltage stabilizing chip are used for power supply of the FPGA chip.

[0019] Further, the test board PCB is provided with reserved 12V and GND pads for external power supply.

[0020] Compared with the prior art, the beneficial effects of the present disclosure are: 1) the transceiver isolation board and the receiver board can be tested singly, which is beneficial for positioning problems during testing; 2) no test line needs to be welded on the tested board, which avoids damage such as short circuit caused by external lead wires; 3) the test channel can be flexibly selected, and single or multiple channel testing can be realized; 4) the whole test can be performed on the PCB board, which is simple to operate and has high reliability. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout the figures, and wherein exemplary embodiments of the present disclosure are shown.

[0022] Figure 1 Structure schematic diagram of an exemplary transceiver isolation and sonar receiver testing device according to the present disclosure;

[0023] Figure 2 An exemplary double-row in-line pin diagram. DETAILED DESCRIPTION

[0024] Preferred embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure is thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] The utility model provides a kind of sonar receiver and transceiver isolation circuit testing device, in a exemplary implementation way:

[0026] The equipment connection relationship related to transceiver isolation and receiver board testing device is as shown in the accompanying Figure 1 As shown, mainly includes: signal generator, external power supply, receiver board, transceiver isolation board and test board.

[0027] Among them, test board includes: two pairs of connectors, 4 voltage stabilizing chips, an FPGA chip, a memory chip, 2 2x16 double-row in-line pins, 32 jumper caps. These devices are all placed on PCB printed board, wherein:

[0028] One pair of connectors is placed on the front of PCB board and is distributed on the left and right sides of the front, for being connected with transceiver isolation board, test signal and PWM wave signal are provided to transceiver isolation board;Another pair of connectors is placed on the back of PCB board and is distributed on the left and right sides of the back, for being connected with receiver board, different frequency and amplitude test input signals are transmitted to receiver board;

[0029] 4 voltage stabilizing chips are arranged on the front of PCB board respectively, for power supply to FPGA chip and power supply to receiver board,

[0030] FPGA chip and memory chip are arranged on the back of PCB board, for transmitting PWM wave signal to transceiver isolation board;

[0031] 2 double-row straight-line insertion pins are welded on the back of the PCB board, a signal input pad is placed beside the double-row straight-line insertion pins, which is used to connect with the signal generator, one column of the double-row straight-line insertion pins is connected with the signal input pad, and the other column is connected with 32 channels respectively;

[0032] The jumper cap is used for insertion with the double-row straight-line insertion pins, and the signal to be tested is selected.

[0033] The 12V and GND pads in the test board PCB are reserved for external power supply.

[0034] Specifically,

[0035] The voltage regulator power supply chip on the test board is 4, which outputs 12V, 5V, 3.3V and 1.2V respectively, the external power supply provides 12V for the test board, the 12V voltage output by the voltage regulator chip is used to power the receiver board, and the 3.3V and 1.2V voltage output by the voltage regulator chip is used to power the FPGA chip.

[0036] Figure 2 It is a 2x16 double-row straight-line insertion pin diagram, where the left side of J5 and J6 respectively leads out 16 signals as a network signal signal_in, a signal_in signal line is led out in the test board and connected with the signal output positive terminal of the signal generator, a ground line is led out in the test board and connected with the ground of the signal generator, the signal generator outputs different frequency and different amplitude sine wave signals signal_in according to the demand, the right side of J5 and J6 respectively leads out 16 signals as a total of 32 signals as the test input signal of the receiver board and the transceiver isolation board, the jumper cap is used for insertion with J5 and J6 according to the need, and 1 or multiple signal_in signals can be selected to enter the transceiver isolation board or the receiver board for signal test.

[0037] After the test signal enters the receiver board, it can cooperate with the system board and the upper computer to test the receiver board performance such as amplitude consistency, phase consistency and amplification multiple.

[0038] For the test of the transceiver isolation board, the PWM wave signal emitted by the FPGA is needed for testing, when the PWM wave is high, the transceiver isolation board signal is turned on, and the test signal signal_in enters the transceiver isolation board and can be tested to have signal_in output on the transceiver isolation board; when the PWM wave is low, the transceiver isolation board signal is cut off, and the test signal signal_in enters the transceiver isolation board but cannot be detected to have signal_in output on the transceiver isolation board.

[0039] The technical scheme is only an exemplary embodiment of the present application, and for those skilled in the art, on the basis of the application method and principle disclosed in the present application, various types of improvements or deformations can be easily made, and are not limited to the method described in the above specific embodiments of the present application, therefore, the above-described mode is only preferred, and does not have a limiting meaning.

Claims

1. A sonar receiver and transceiver isolation circuit test apparatus, characterized by, It comprises: two pairs of connectors, several voltage stabilizing power supply chips, an FPGA chip, a storage chip, double-row in-line pins, several jumper caps, and all these devices are arranged on a PCB printed board, wherein: a signal input pad is arranged beside the double-row in-line pins, which is used to be connected with an external signal generator, one column of the double-row in-line pins is connected with the signal input pad, and the other column is connected with an external receiver board or transceiver isolation board through the connector, and the jumper cap is used to be inserted into the double-row in-line pins to select which path signal to test; one pair of connectors is used to be connected with the transceiver isolation board to transmit test signals and PWM wave signals to the transceiver isolation board; the other pair of connectors is used to be connected with the sonar receiver board to transmit test input signals with different frequencies and amplitudes to the receiver board; the voltage stabilizing power supply chip is used to supply power to the FPGA chip and the receiver board; the FPGA chip and the storage chip are used to send PWM wave signals to the transceiver isolation board.

2. The apparatus of claim 1, wherein, The double-row in-line pins adopt two 2x16 double-row in-line pins, and the jumper cap has 32; wherein: 16 signals are led out from the left side of the two pins as a network signal signal_in, a signal_in signal line is led out in the test board and connected with the signal output positive terminal of the signal generator, a ground line is led out in the test board and connected with the ground of the signal generator, and the signal generator outputs sine wave signals signal_in with different frequencies and amplitudes according to the demand; 32 signals are led out from the right side of the two pins as test input signals of the receiver board and the transceiver isolation board; the jumper cap is inserted into the two pins as needed to select one or multiple signal_in signals to enter the transceiver isolation board or the receiver board for signal testing.

3. The apparatus of claim 1 or 2, wherein, The double-row in-line pins are welded on the back of the PCB board; one pair of connectors is placed on the front of the PCB printed board and distributed on the left and right sides of the front, and the other pair of connectors is placed on the back of the PCB board and distributed on the left and right sides of the back; the voltage stabilizing chip is arranged on the front of the PCB board; the FPGA chip and the storage chip are arranged on the back of the PCB board.

4. The apparatus of claim 1, wherein, There are four voltage stabilizing power supply chips on the test board, which output 12V, 5V, 3.3V and 1.2V voltages, the external power supply supplies power to the test board at 12V, the 12V voltage output by the voltage stabilizing chip is used to supply power to the receiver board, and the 3.3V and 1.2V voltages output by the voltage stabilizing chip are used to supply power to the FPGA chip.

5. The apparatus of claim 4, wherein, 12V and GND pads are reserved in the test board PCB for external power supply.

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