Semiconductor test structure

Abstract

The utility model relates to a semiconductor test structure, and relates to the technical field of semiconductors, in the semiconductor test structure, a substrate comprises a plurality of active regions; the plurality of word line structures extend along the first direction and intersect with the active region; the plurality of insulating columns are positioned on the word line structure and are in direct contact with the word line structure; the first plugs and the second plugs are alternately clamped between the insulating columns in the second direction and electrically connected with the active region, and the first plugs further extend to the side walls of the word line structures and are electrically connected with the word line structures; at least whether the short-circuit defect of the adjacent conductive plugs exists in the chip can be detected timely, simply and conveniently.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor test structure. BACKGROUND

[0002] With the rapid development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in the process production can affect the performance of the devices.

[0003] For a semiconductor chip, with the miniaturization of devices and the continuous increase of storage capacity and storage density, the probability of generating a leakage channel between adjacent conductive plugs is continuously increased, which increases the challenge of electrical defect detection of the semiconductor chip. CONTENT OF THE UTILITY MODEL

[0004] Therefore, the present application provides a semiconductor test structure, which can at least timely and simply detect whether there is a short circuit defect between adjacent conductive plugs in a chip.

[0005] In order to solve the above technical problems and other problems, according to some embodiments, a first aspect of the present application provides a semiconductor test structure, comprising a substrate, a plurality of word line structures, a plurality of insulating columns, a plurality of first plugs, and a plurality of second plugs, the substrate comprising a plurality of active regions; the plurality of word line structures extend along a first direction and intersect with the active regions; the plurality of insulating columns are located on the word line structures and directly contact with the word line structures; the plurality of first plugs and the plurality of second plugs are alternately arranged between the insulating columns along a second direction and electrically connected with the active regions, wherein the first plug further extends to the sidewall of the word line structure and is electrically connected with the word line structure.

[0006] The semiconductor test structure in the above embodiment, by arranging a plurality of word line structures extending along the first direction and intersecting the active region, and arranging a plurality of insulating columns on the word line structures and directly contacting the word line structures, so as to facilitate the arrangement of a plurality of first plugs and a plurality of second plugs, which are alternately sandwiched between the insulating columns along the second direction and electrically connected with the active region; since the first plug also extends to the sidewall of the word line structure and is electrically connected with the word line structure, so that the first plug and the second plug adjacent along the second direction present the same voltage contrast pattern on the electron beam detection voltage contrast graph, and the first plug and the second plug adjacent along the first direction present different voltage contrast patterns on the electron beam detection voltage contrast graph. For example, under normal circumstances, the first plug and the second plug adjacent along the second direction present bright voltage contrast pattern or dark voltage contrast pattern on the electron beam detection voltage contrast graph; the first plug and the second plug adjacent along the first direction present bright voltage contrast pattern and dark voltage contrast pattern which appear alternately on the electron beam detection voltage contrast graph. If at least three same voltage contrast patterns adjacent along the first direction appear on the electron beam detection voltage contrast graph of the semiconductor structure to be tested, or two different voltage contrast patterns adjacent along the second direction appear, it is determined that the semiconductor structure to be tested has adjacent conductive plug short circuit defect; otherwise, it is determined that the semiconductor structure to be tested does not have adjacent conductive plug short circuit defect. Thus, the embodiment of the present application can at least timely and simply detect whether there is adjacent conductive plug short circuit defect in the chip, avoid the chip with adjacent conductive plug short circuit defect from flowing into the later process to affect the production efficiency of the machine, and can adjust the defective process in time according to the detected defect to avoid the defective process from continuously reducing the product yield.

[0007] In some embodiments, the first plug is in electrical contact with the sidewalls of the two word line structures adjacent along the second direction, so as to maximize the size of the first plug in the second direction to reduce the impedance of the first plug; and when any one of the word line structures adjacent to the first plug is selected to be powered, the first plug can also be selected to be powered, so that the first plug and the second plug adjacent along the second direction present bright voltage contrast pattern or dark voltage contrast pattern on the electron beam detection voltage contrast graph, thereby improving the efficiency of detecting adjacent conductive plug short circuit defect.

[0008] In some embodiments, the insulating column includes a cover layer and a separation portion, the cover layer is located on the top surface of the word line structure and directly contacts the top surface of the word line structure; the bottom surface of the second plug is located between the cover layers adjacent along the second direction and is higher than the top surface of the word line structure; the separation portion is located on the cover layer, and the insulating column insulates the first plug and the second plug adjacent along the second direction from each other; and the cover layer insulates the first plug adjacent along the second direction from each other.

[0009] In some embodiments, the bottom surface of the first plug is lower than the bottom surface of the second plug, so that the first plug extends to the sidewall of the word line structure and is electrically connected to the word line structure, while the bottom surface of the second plug is located between adjacent cover layers along the second direction.

[0010] In some embodiments, the substrate includes an array region and a dicing region. The dicing region is located on the periphery of the array region, and the semiconductor test structure is located within the dicing region, thus avoiding an increase in the area of ​​the array region due to the introduction of the semiconductor test structure. By placing the semiconductor test structure within the dicing region, the semiconductor structure under test in the array region and the semiconductor test structure in the dicing region can be fabricated simultaneously in the same process step, thus avoiding an increase in the complexity and cost of the process due to the introduction of the semiconductor test structure.

[0011] According to some embodiments, a second aspect of this application provides a semiconductor test structure, including a substrate, a plurality of word line structures, a plurality of bit line structures, a plurality of first plugs, and a plurality of second plugs. The substrate includes a plurality of active regions. The plurality of word line structures extend along a first direction and intersect with the active regions. The plurality of bit line structures extend along a second direction and are electrically connected to the active regions, wherein the first direction and the second direction are perpendicular to each other. The plurality of first plugs and the plurality of second plugs are alternately arranged along the first direction on one side of the bit line structures and are electrically connected to the active regions. The first plugs also extend to the sidewalls of the word line structures and are electrically connected to the word line structures.

[0012] The semiconductor test structure in the above embodiments includes multiple word line structures extending along a first direction and intersecting with the active region, multiple bit line structures extending along a second direction and electrically connected to the active region, and multiple first plugs and multiple second plugs arranged alternately along the first direction on one side of the bit line structures and electrically connected to the active region. The first plugs also extend to the sidewall of the word line structure and are electrically connected to it. This results in adjacent first and second plugs along the first direction exhibiting different voltage contrast patterns on the electron beam detection voltage comparison chart, and adjacent first and second plugs along the second direction exhibiting the same voltage contrast pattern. For example, under normal circumstances, adjacent first and second plugs along the second direction both exhibit either a bright voltage contrast pattern or a dark voltage contrast pattern on the electron beam detection voltage comparison chart; adjacent first and second plugs along the first direction exhibit alternating bright and dark voltage contrast patterns on the electron beam detection voltage comparison chart. If at least three identical voltage comparison patterns appear adjacent to each other along the first direction on the electron beam detection voltage comparison map of the semiconductor structure under test, or two different voltage comparison patterns appear adjacent to each other in the second direction, it is determined that the semiconductor structure under test has an adjacent conductive plug short-circuit defect; otherwise, it is determined that the semiconductor structure under test does not have an adjacent conductive plug short-circuit defect. Therefore, the embodiments of this application can at least detect whether there is an adjacent conductive plug short-circuit defect in the chip in a timely and convenient manner, preventing chips with adjacent conductive plug short-circuit defects from flowing into the subsequent process and affecting the production efficiency of the equipment, and can adjust the defective process in a timely manner according to the detected defect, so as to prevent the defective process from further reducing the product yield.

[0013] In some embodiments, the first plug is electrically contacted with the sidewalls of the two adjacent word line structures along the second direction, thereby maximizing the size of the first plug in the second direction to reduce the impedance of the first plug; and when any word line structure adjacent to the first plug is selected for energization, the first plug can also be selected for energization, so that the first plug and the second plug adjacent along the second direction both show a bright voltage comparison pattern or a dark voltage comparison pattern on the electron beam detection voltage comparison diagram, thereby improving the efficiency of short-circuit defect detection of adjacent conductive plugs.

[0014] In some embodiments, the semiconductor test structure further includes a plurality of insulating pillars located on and in direct contact with the word line structure; each insulating pillar includes a capping layer and an isolation portion, the capping layer being located on the top surface of the word line structure and in direct contact with the top surface of the word line structure; the bottom surface of the second plug is located between adjacent capping layers along the second direction and is higher than the top surface of the word line structure; the isolation portion is located on the capping layer, and the insulating pillars insulate the first plug and the second plug adjacent along the second direction from each other; the capping layer insulates the first plugs adjacent along the second direction from each other.

[0015] In some embodiments, the bottom surface of the first plug is lower than the bottom surface of the second plug, so that the first plug extends to the sidewall of the word line structure and is electrically connected to the word line structure, while the bottom surface of the second plug is located between adjacent cover layers along the second direction.

[0016] In some embodiments, the substrate includes an array region and a dicing region. The dicing region is located on the periphery of the array region, and the semiconductor test structure is located within the dicing region, thus avoiding an increase in the area of ​​the array region due to the introduction of the semiconductor test structure. By placing the semiconductor test structure within the dicing region, the semiconductor structure under test in the array region and the semiconductor test structure in the dicing region can be fabricated simultaneously in the same process step, thus avoiding an increase in the complexity and cost of the process due to the introduction of the semiconductor test structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view schematic diagram including a semiconductor test structure in one embodiment of this application;

[0019] Figure 2 This is a top view schematic diagram of a semiconductor test structure in one embodiment of this application;

[0020] Figure 3 This is a schematic cross-sectional view of a semiconductor test structure according to an embodiment of this application, wherein, Figure 3 The direction of BB' in the middle is along Figure 2 A schematic diagram of the longitudinal section structure obtained in the BB' direction shown in the figure;

[0021] Figure 4 This is a standard testing schematic diagram of a semiconductor test structure in one embodiment of this application;

[0022] Figure 5 This is a schematic diagram of defect detection in a semiconductor test structure according to another embodiment of this application.

[0023] Explanation of reference numerals in the attached figures:

[0024] 100, Substrate; 1000, Semiconductor test structure; 10, Cutting area; 20, Array area; 211, First plug; 212, Second plug; 22, Word line structure; 23, Bit line structure; 25, Insulating pillar; 251, Capping layer; 252, Isolation section; 101, Isolation structure; 102, Active region. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description of the application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the application. However, the application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] Please note that the mutual insulation between the two entities described in this application embodiment includes, but is not limited to, the presence of one or more of the following: insulating material, insulating fumes, or gaps.

[0032] This application aims to provide a semiconductor testing structure that can at least detect the presence of short-circuit defects between adjacent conductive plugs in a chip in a timely and convenient manner, thereby effectively improving the chip yield.

[0033] Please refer to Figure 1A semiconductor test structure 1000 is disposed on a substrate 100, the substrate 100 including an array region 20 and a dicing region 10 located around the array region 20. The semiconductor test structure 1000 can be located in the dicing region 10. This avoids increasing the area of ​​the array region 20 due to the introduction of the semiconductor test structure 1000; by disposing of the semiconductor test structure 1000 within the dicing region 10, the semiconductor structure under test in the array region 20 and the semiconductor test structure 1000 in the dicing region 10 can be fabricated simultaneously in the same process steps, avoiding increasing the complexity and cost of the process due to the introduction of the semiconductor test structure 1000.

[0034] Please refer to Figures 2-3 In some embodiments, a semiconductor test structure is provided, including a substrate 100, a plurality of word line structures 22, a plurality of insulating pillars 25, a plurality of first plugs 211, and a plurality of second plugs 212. The substrate 100 includes a plurality of active regions 102; the plurality of word line structures 22 extend along a first direction (e.g., the oy direction) and intersect with the active regions 102; the plurality of insulating pillars 25 are located on the word line structures 22 and are in direct contact with the word line structures 22; the plurality of first plugs 211 and the plurality of second plugs... 212, alternately sandwiched between insulating posts 25 along a second direction (e.g., the ox direction), such that the first plug 211 and the second plug 212 are alternately arranged along the ox direction, and the first plug 211 and the second plug 212 adjacent along the ox direction are insulated from each other by the insulating posts 25. The plurality of first plugs 211 and the plurality of second plugs 212 are electrically connected to the active area 102 below them. The first plug 211 also extends to the side wall of the word line structure 22 and is electrically connected to the word line structure 22.

[0035] For example, please continue to refer to Figure 2 , Figure 3 By setting multiple word line structures 22 extending along a first direction (e.g., the oy direction) and intersecting with the active region 102, adjacent active regions 102 are isolated by an isolation structure 101, and multiple insulating pillars 25 are set on the word line structures 22 and in direct contact with them, it is convenient to set multiple first plugs 211 and multiple second plugs 212, which are alternately sandwiched between the insulating pillars 25 along a second direction (e.g., the ox direction) and electrically connected to the active region 102. Since the first plugs 211 also extend to the side wall of the word line structure 22 and are electrically connected to it, adjacent first plugs 211 and second plugs 212 along the second direction show the same voltage comparison pattern on the electron beam detection voltage comparison diagram, and adjacent first plugs 211 and second plugs 212 along the first direction show different voltage comparison patterns on the electron beam detection voltage comparison diagram. For example, under normal circumstances, please refer to Figure 4On the electron beam detection voltage comparison chart, the first plug 211 and the second plug 212 adjacent along the second direction both show bright voltage comparison patterns or dark voltage comparison patterns; on the electron beam detection voltage comparison chart, the first plug 211 and the second plug 212 adjacent along the first direction show alternating bright voltage comparison patterns and dark voltage comparison patterns.

[0036] For example, the material of the first plug 211 or the second plug 212 is selected from titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper or metal silicides and combinations thereof.

[0037] For example, please refer to Figure 5 If at least three identical voltage comparison patterns appear adjacent along a first direction (e.g., the oy direction) on the electron beam detection voltage comparison map of the semiconductor structure under test, for example... Figure 5 The presence of three identical voltage comparison patterns arranged continuously along the oy direction as shown in box D indicates that the conductive plugs corresponding to the voltage comparison patterns in box D are abnormal or defective. For example, there may be a current leakage path between the conductive plugs corresponding to the voltage comparison patterns in box D.

[0038] For example, please continue to refer to Figure 5 If, on the electron beam detection voltage comparison map of the semiconductor structure under test, two adjacent different voltage comparison patterns appear in the second direction (e.g., the ox direction), for example... Figure 5 If two different voltage comparison patterns appear alternately in the ox direction within box L, it can be determined that the conductive plug corresponding to the voltage comparison pattern in box L is abnormal or defective.

[0039] Therefore, in some embodiments of this application, if at least three identical voltage comparison patterns appear adjacent to each other along the first direction on the electron beam detection voltage comparison map of the semiconductor structure under test, or if two different voltage comparison patterns appear adjacent to each other in the second direction, it is determined that there is a conductive plug abnormality or defect in the semiconductor structure under test; otherwise, it is determined that there is no conductive plug defect in the semiconductor structure under test. Thus, the embodiments of this application can at least promptly and easily detect whether there is a conductive plug abnormality or defect in the chip, preventing chips with adjacent conductive plug defects from flowing into subsequent processes and affecting the production efficiency of the equipment, and can promptly adjust defective processes based on detected defects to prevent defective processes from further reducing product yield.

[0040] In some embodiments, please refer to Figure 2 , Figure 3The first plug 211 is electrically contacted with the sidewalls of the two adjacent word line structures 22 along the second direction (e.g., the ox direction), thereby maximizing the size of the first plug 211 in the second direction to reduce its impedance. This also ensures that when any word line structure 22 adjacent to the first plug 211 is selected for energization, the first plug 211 can also be selected for energization. This results in the first plug 211 and the second plug 212 adjacent along the second direction both exhibiting bright or dark voltage comparison patterns on the electron beam detection voltage comparison diagram, thereby improving the efficiency of detecting short-circuit defects in adjacent conductive plugs.

[0041] In some embodiments, please refer to Figure 2 , Figure 3 The insulating post 25 includes a cover layer 251 and an insulating portion 252. The cover layer 251 is located on the top surface of the word line structure 22 and is in direct contact with the top surface of the word line structure 22. The bottom surface of the second plug 212 is located between adjacent cover layers 251 along the second direction (e.g., the ox direction) and is higher than the top surface of the word line structure 22. The insulating portion 252 is located on the cover layer 251 and the insulating post 255 insulates the first plug 211 and the second plug 212 adjacent along the second direction from each other. The cover layer 251 insulates the first plug 211 adjacent along the second direction from each other.

[0042] In some embodiments, please refer to Figure 2 , Figure 3 The bottom surface of the first plug 211 is lower than the bottom surface of the second plug 212, so that the first plug 211 extends to the side wall of the word line structure 22 and is electrically connected to the word line structure 22, while the bottom surface of the second plug 212 is located between adjacent cover layers 251 along the second direction (e.g., the ox direction).

[0043] Please refer to Figure 2In some embodiments, a semiconductor test structure is provided, including a substrate 100, a plurality of word line structures 22, a plurality of bit line structures 23, a plurality of first plugs 211, and a plurality of second plugs 212. The substrate 100 includes a plurality of active regions 102. The plurality of word line structures 22 extend along a first direction (e.g., the oy direction) and intersect with the active regions 102. The plurality of bit line structures 23 extend along a second direction (e.g., the ox direction) and are electrically connected to the active regions 102, wherein the first direction and the second direction are perpendicular to each other. Multiple first plugs 211 and multiple second plugs 212 are alternately arranged on one side of the bit line structure 23 along a first direction, such that the first plugs 211 and the second plugs 212 are alternately arranged along the oy direction, and a bit line structure 23 is included between adjacent first plugs 211 and second plugs 212 along the oy direction. The multiple first plugs 211 and multiple second plugs 212 are all electrically connected to the active region 102 below them. The first plugs 211 also extend to the side wall of the word line structure 22 and are electrically connected to the word line structure 22.

[0044] For example, please continue to refer to Figures 2-3 By setting multiple word line structures 22 extending along a first direction (e.g., the oy direction) and intersecting with the active region 102, and multiple bit line structures 23 extending along a second direction (e.g., the ox direction) and electrically connected to the active region 102, and by setting multiple first plugs 211 and multiple second plugs 212 alternately arranged along the first direction on one side of the bit line structure 23 and electrically connected to the active region 102, and by isolating adjacent active regions 102 through an isolation structure 101, wherein the first plugs 211 also extend to the sidewall of the word line structure 22 and are electrically connected to the word line structure 22, thereby causing adjacent first plugs 211 and second plugs 212 along the first direction to present different voltage comparison patterns on the electron beam detection voltage comparison diagram, and causing adjacent first plugs 211 and second plugs 212 along the second direction to present the same voltage comparison pattern on the electron beam detection voltage comparison diagram. For example, under normal circumstances, please refer to Figure 4 On the electron beam detection voltage comparison chart, the first plug 211 and the second plug 212 adjacent along the second direction both show bright voltage comparison patterns or dark voltage comparison patterns; on the electron beam detection voltage comparison chart, the first plug 211 and the second plug 212 adjacent along the first direction show alternating bright voltage comparison patterns and dark voltage comparison patterns.

[0045] For example, please refer to Figure 5 If at least three identical voltage comparison patterns appear adjacent along a first direction (e.g., the oy direction) on the electron beam detection voltage comparison map of the semiconductor structure under test, for example... Figure 5The presence of three identical voltage comparison patterns arranged continuously along the oy direction as shown in box D indicates that the conductive plugs corresponding to the voltage comparison patterns in box D are abnormal or defective. For example, there may be a current leakage path between the conductive plugs corresponding to the voltage comparison patterns in box D.

[0046] For example, please continue to refer to Figure 5 If, on the electron beam detection voltage comparison map of the semiconductor structure under test, two adjacent different voltage comparison patterns appear in the second direction (e.g., the ox direction), such as... Figure 5 If two different voltage comparison patterns appear alternately in the ox direction within box L, it can be determined that the conductive plug corresponding to the voltage comparison pattern in box L is abnormal or defective.

[0047] In some embodiments, please refer to Figure 2 , Figure 3 The first plug 211 is electrically contacted with the sidewalls of the two adjacent word line structures 22 along the second direction (e.g., the ox direction), thereby maximizing the size of the first plug 211 in the second direction to reduce its impedance. This also ensures that when any word line structure 22 adjacent to the first plug 211 is selected for energization, the first plug 211 can also be selected for energization. This results in the first plug 211 and the second plug 212 adjacent along the second direction both exhibiting bright or dark voltage comparison patterns on the electron beam detection voltage comparison diagram, thereby improving the efficiency of detecting short-circuit defects in adjacent conductive plugs.

[0048] In some embodiments, please refer to Figure 2 , Figure 3 The semiconductor test structure also includes a plurality of insulating pillars 25, which are located on and in direct contact with the word line structure 22. Each insulating pillar 25 includes a capping layer 251 and an isolation portion 252. The capping layer 251 is located on the top surface of the word line structure 22 and is in direct contact with the top surface of the word line structure 22. The bottom surface of the second plug 212 is located between adjacent capping layers 251 along the second direction (e.g., the ox direction) and is higher than the top surface of the word line structure 22. The isolation portion 252 is located on the capping layer 251, and the insulating pillars 25 insulate the first plug 211 and the second plug 212 adjacent along the second direction from each other. The capping layer 251 is used to insulate the first plug 211 adjacent along the second direction from each other.

[0049] In some embodiments, please refer to Figure 2 , Figure 3 The bottom surface of the first plug 211 is lower than the bottom surface of the second plug 212, so that the first plug 211 extends to the side wall of the word line structure 22 and is electrically connected to the word line structure 22, while the bottom surface of the second plug 212 is located between adjacent cover layers 251 along the second direction (e.g., the ox direction).

[0050] In some embodiments, please refer to Figure 1 The substrate 100 includes an array region 20 and a dicing region 10. The dicing region 10 is located on the periphery of the array region 20, and the semiconductor test structure 1000 is located within the dicing region 10. This avoids increasing the area of ​​the array region 20 due to the introduction of the semiconductor test structure 1000. By placing the semiconductor test structure 1000 within the dicing region 10, the semiconductor structure under test in the array region 20 and the semiconductor test structure 1000 in the dicing region 10 can be fabricated simultaneously in the same process steps, avoiding increasing the complexity and cost of the process due to the introduction of the semiconductor test structure 1000.

[0051] In some embodiments, a defect detection method includes:

[0052] Step S300: Provide a semiconductor test structure according to any embodiment of this application;

[0053] Step S400: Use an electron beam defect detection device to inspect the aforementioned semiconductor test structure and obtain inspection information;

[0054] Step S500: Determine whether there is a short circuit defect between adjacent conductive plugs in the array area within the chip based on the detection information.

[0055] In some embodiments, the detection information includes an electron beam detection voltage comparison graph; step 500, determining whether there is a short-circuit defect between adjacent conductive plugs in the array region within the chip based on the detection information, includes:

[0056] Step S501: Compare the electron beam detection voltage comparison image with a preset standard image;

[0057] Step S502: Determine whether there is a short circuit defect between adjacent conductive plugs in the array area based on the comparison results.

[0058] It should be understood that electron beam defect detection equipment uses a low-energy electron beam as the incident source during the detection process. When the electron beam strikes the surface of the semiconductor test structure, it excites secondary electrons, back-electrons, and penetrating electrons. The collected image is then presented by an image processing system, which is the electron beam detection voltage contrast map. In the electron beam detection voltage contrast map, areas with a higher amount of secondary electrons can be observed as a bright field or bright voltage contrast pattern, while areas with a lower amount of secondary electrons can be observed as a dark field or dark voltage contrast pattern. Therefore, the distribution of bright field / dark field can be used as a basis for defect detection judgment.

[0059] It should be understood that the device structure in the substrate of the semiconductor test structure can be equivalent to a MOS transistor. The first and second plugs located above the active region are in a floating state. When the electron beam defect detection equipment emits an electron beam onto the floating first or second plug, more charge accumulates, and the amount of secondary electrons also accumulates, resulting in a bright field or bright voltage contrast pattern at the corresponding position of the preset standard image. Conversely, when the first and second plugs above the active region are grounded, and the electron beam defect detection equipment emits an electron beam onto the grounded first or second plug, charge transfer occurs, resulting in less charge accumulation and less secondary electron accumulation, resulting in a dark field or dark voltage contrast pattern at the corresponding position of the preset standard image.

[0060] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0061] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are quite specific and detailed, but they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A semiconductor test structure, wherein, include: The substrate includes multiple active regions; Multiple word line structures extend along a first direction and intersect with the active region; Multiple insulating posts are located on the word line structure and are in direct contact with the word line structure; Multiple first plugs and multiple second plugs are alternately sandwiched between the insulating posts along a second direction and electrically connected to the active area, wherein the first plugs also extend to the sidewall of the word line structure and are electrically connected to the word line structure.

2. The semiconductor test structure according to claim 1, wherein, The first plug is in electrical contact with the sidewalls of the two adjacent letter lines along the second direction.

3. The semiconductor test structure according to claim 1, wherein, The insulating post includes: The cover layer is located on the top surface of the character line structure and is in direct contact with the top surface of the character line structure. The bottom surface of the second plug is located between adjacent cover layers along the second direction and is higher than the top surface of the letter line structure; An isolation section is located on the cover layer.

4. The semiconductor test structure according to claim 1, wherein, The bottom surface of the first plug is lower than the bottom surface of the second plug.

5. The semiconductor test structure according to claim 1, wherein, The substrate includes: Array area; The dicing region is located on the periphery of the array region, and the semiconductor test structure is located within the dicing region.

6. A semiconductor test structure, wherein, include: The substrate includes multiple active regions; Multiple word line structures extend along a first direction and intersect with the active region; Multiple bit line structures extend along a second direction and are electrically connected to the active region, wherein the first direction and the second direction are perpendicular to each other; and A plurality of first plugs and a plurality of second plugs are alternately arranged along the first direction on one side of the bit line structure and electrically connected to the active area, wherein the first plugs also extend to the sidewall of the word line structure and are electrically connected to the word line structure.

7. The semiconductor test structure according to claim 6, wherein, The first plug is in electrical contact with the sidewalls of the two adjacent letter lines along the second direction.

8. The semiconductor test structure according to claim 6, wherein, Also includes: Multiple insulating posts are located on the word line structure and are in direct contact with the word line structure; The insulating post includes: The cover layer is located on the top surface of the character line structure and is in direct contact with the top surface of the character line structure. The bottom surface of the second plug is located between adjacent cover layers along the second direction and is higher than the top surface of the letter line structure; An isolation section is located on the cover layer.

9. The semiconductor test structure according to claim 6, wherein, The bottom surface of the first plug is lower than the bottom surface of the second plug.

10. The semiconductor test structure according to claim 6, wherein, The substrate includes: Array area; The dicing region is located on the periphery of the array region, and the semiconductor test structure is located within the dicing region.

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