Chip packaging structure

Abstract

The utility model belongs to the technical field of chip packaging, and discloses a chip packaging structure. The chip packaging structure comprises a substrate, a first wiring layer is arranged on the upper surface of the substrate, and second wiring layers are symmetrically arranged on the lower surface of the substrate; a chip module, wherein the chip module is embedded in the substrate; a first dielectric layer, a third wiring layer, a second dielectric layer and a fourth wiring layer are laminated on the surface of the first wiring layer; a first connecting piece is arranged between the first dielectric layer and the third wiring layer, and a second connecting piece is arranged between the second dielectric layer and the fourth wiring layer; a third dielectric layer, a fifth wiring layer, a fourth dielectric layer, a fifth dielectric layer and a sixth wiring layer are arranged on the second wiring layer in a stacked mode in the direction away from the substrate. A third connecting piece is arranged between the third dielectric layer and the fifth wiring layer; the heat conductivity coefficient of the fourth dielectric layer is lower than that of the fifth dielectric layer. According to the structure, the problem that glue filling holes exist in the line spacing in the chip packaging process can be reduced, and the reliability of products is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure. BACKGROUND

[0002] With the progress of artificial intelligence, Internet of Things and other technologies, the performance of electronic products is increasingly tending to be highly intelligent, which has promoted the demand for advanced packaging processes to grow continuously. The existing chip packaging process mainly includes installing a chip module on a substrate, bonding a conductive layer on the substrate through a semi-cured sheet, and processing a circuit diagram on the conductive layer. However, the existing high-power chip packaging structure has a relatively thick conductive copper layer, and a large amount of glue is needed to fill the space between the lines. However, the semi-cured sheet used at present has poor fluidity, and the chip structure prepared thereby has serious glue filling voids, resulting in low product reliability. SUMMARY

[0003] Therefore, embodiments of the present application provide a chip packaging structure to reduce the problem of glue filling voids between lines in the chip packaging process and improve the reliability of products.

[0004] In a first aspect, the present application provides a chip packaging structure.

[0005] The present application is achieved by the following technical solutions:

[0006] A chip packaging structure, the packaging structure comprising:

[0007] a substrate, the upper surface of the substrate being provided with a first wiring layer, and the lower surface of the substrate being symmetrically provided with a second wiring layer;

[0008] a chip module, the chip module being embedded in the substrate;

[0009] a first dielectric layer, a third wiring layer, a second dielectric layer and a fourth wiring layer are stacked on the surface of the first wiring layer; the third wiring layer and the chip module are electrically connected through a first connecting piece, and the fourth wiring layer and the third wiring layer are electrically connected through a second connecting piece;

[0010] a third dielectric layer, a fifth wiring layer, a fourth dielectric layer, a fifth dielectric layer and a sixth wiring layer are stacked on the surface of the second wiring layer; the fifth wiring layer and the chip module are electrically connected through a third connecting piece; the thermal conductivity of the fourth dielectric layer is lower than that of the fifth dielectric layer.

[0011] In a preferred example of the present application, it can be further provided to comprise:

[0012] a through-hole connecting piece, the through-hole connecting piece penetrating through the third wiring layer, the first dielectric layer, the substrate, the third dielectric layer and the fifth wiring layer.

[0013] In a preferred example of the present application, the fourth dielectric layer can be further configured as a dielectric layer formed by curing of a bonding material, the bonding material being composed of 80% filler particles and 20% epoxy resin.

[0014] In a preferred example of the present application, the fourth dielectric layer can be further configured as a dielectric layer formed by curing of a bonding material, the bonding material being composed of 80% filler particles and 20% epoxy resin.

[0015] In a preferred example of the present application, the fifth dielectric layer can be further configured as a dielectric layer formed by curing of a bonding material, the bonding material being composed of 95% filler particles and 5% epoxy resin.

[0016] In a preferred example of the present application, the fifth dielectric layer can be further configured as a dielectric layer formed by curing of a bonding material, the bonding material being composed of 95% filler particles and 5% epoxy resin.

[0017] In a preferred example of the present application, the third wiring layer and the chip module can be electrically connected through a plurality of first connecting members, the plurality of first connecting members being uniformly distributed in the area of the chip module.

[0018] In a preferred example of the present application, the fifth wiring layer can have a thickness of 100-120 μm.

[0019] In a preferred example of the present application, the sixth wiring layer can be made of copper plate.

[0020] In a preferred example of the present application, the substrate can be a double-sided copper-clad substrate.

[0021] In summary, compared with the prior art, the technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0022] The chip structure comprises a substrate, a first wiring layer is arranged on the upper surface of the substrate, and a second wiring layer is symmetrically arranged on the lower surface of the substrate; a chip module is embedded in the substrate; a first dielectric layer, a third wiring layer, a second dielectric layer and a fourth wiring layer are stacked on the surface of the first wiring layer; the third wiring layer and the chip module are electrically connected through a first connecting piece, and the fourth wiring layer and the third wiring layer are electrically connected through a second connecting piece; a third dielectric layer, a fifth wiring layer, a fourth dielectric layer, a fifth dielectric layer and a sixth wiring layer are stacked on the surface of the second wiring layer; the fifth wiring layer and the chip module are electrically connected through a third connecting piece; and the thermal conductivity of the fourth dielectric layer is lower than that of the fifth dielectric layer. By changing the structure of the dielectric layer between the fifth wiring layer and the sixth wiring layer, the dielectric layer can be effectively converted into a molten state and completely fill the surface circuit spacing of the fifth wiring layer, solving the problem of glue filling voids in the circuit spacing in the original product structure and improving the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structural schematic diagram of a chip packaging structure is provided for an exemplary embodiment of the present application.

[0024] Figure 2 A structural schematic diagram of a chip packaging structure is provided for another exemplary embodiment of the present application.

[0025] Reference signs:

[0026] 1 - substrate, 101 - first wiring layer, 102 - second wiring layer, 2 - chip module, 3 - first dielectric layer, 4 - third wiring layer, 5 - second dielectric layer, 6 - fourth wiring layer, 7 - third dielectric layer, 8 - fifth wiring layer, 9 - fourth dielectric layer, 10 - fifth dielectric layer, 11 - sixth wiring layer, 12 - second connecting piece, 13 - first connecting piece, 14 - third connecting piece, 15 - through-hole connecting piece. DETAILED DESCRIPTION

[0027] This specific embodiment is only an explanation of the present application, and is not a limitation of the present application. Those skilled in the art can make modifications to the present embodiment without creative contribution after reading the present specification, but as long as the modifications are within the scope of the claims of the present application, they are protected by the patent law.

[0028] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0029] In addition, the term "and / or" in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the associated objects unless otherwise specified.

[0030] The terms "first", "second", and the like in the present application are used to distinguish the same items or similar items with basically the same function, and it should be understood that there is no logical or time sequence relationship between "first", "second", and "n", and the quantity and execution order are not limited.

[0031] The embodiments of the present application will be described in further detail below with reference to the drawings of the specification.

[0032] In an embodiment of the present application, a chip packaging structure is provided, as shown in Figure 1 The chip packaging structure comprises:

[0033] a substrate 1, a first wiring layer 101, a second wiring layer 102, a chip module 2, a first dielectric layer 3, a third wiring layer 4, a second dielectric layer 5, a fourth wiring layer 6, a third dielectric layer 7, a fifth wiring layer 8, a fourth dielectric layer 9, a fifth dielectric layer 10, a sixth wiring layer 11, a second connecting piece 12, a first connecting piece 13, and a third connecting piece 14.

[0034] The upper surface of the substrate 1 is the first wiring layer 101, which is used for network wiring of the PCB (printed circuit board) of the chip module and provides a conductive circuit. The lower surface of the substrate 1 is symmetrically provided with the second wiring layer 102, which is used for network wiring of the PCB (printed circuit board) of the chip module and provides a conductive circuit. Specifically, the substrate 1 is a double-sided copper-clad substrate, that is, a substrate material with copper layers on the upper and lower surfaces. For example, the substrate 1 can be a double-sided copper-clad epoxy resin substrate or a double-sided copper-clad ceramic substrate. In this application, the thickness of the substrate 1 is 1.3 mm, and the thickness of the copper layer on the upper surface and the copper layer on the lower surface is 40 μm to 50 μm, that is, the thickness of the first wiring layer 101 and the second wiring layer 102 is 40 μm to 50 μm. The first wiring layer 101 and the second wiring layer 102 can provide the same wiring function or different wiring functions. By providing wiring layers on the upper and lower surfaces of the substrate 1, more wiring paths can be provided in a limited space.

[0035] The chip module 2 is embedded in the substrate 1. Specifically, a through slot is formed in the substrate 1, which extends through the upper end and the lower end of the substrate 1. The chip module 2 is embedded in the through slot of the substrate 1, and the lower surface of the chip module 2 is flush with the lower surface of the second wiring layer 102, and the upper surface of the chip module 2 is flush with the upper surface of the first wiring layer 101. At the same time, the gap between the chip module 2 and the substrate 1 is filled with a resin material to stably fix the chip module 2 inside the substrate 1 and improve the mechanical stability of the product.

[0036] The first wiring layer 101 is provided with a first dielectric layer 3, a third wiring layer 4, a second dielectric layer 5, and a fourth wiring layer 6 in sequence from top to bottom. The third wiring layer 4 and the chip module 2 are provided with a first connecting piece 13, and the third wiring layer 4 and the chip module 2 are electrically connected through the first connecting piece 13. The fourth wiring layer 6 and the third wiring layer 4 are provided with a second connecting piece 12, and the fourth wiring layer 6 and the third wiring layer 4 are electrically connected.

[0037] Specifically, the packaging structure includes a first dielectric layer 3 and a third wiring layer 4, wherein the third wiring layer 4 is used for network wiring of a PCB (printed circuit board), and the third wiring layer 4 can be made of a metal material with good electrical conductivity. The third wiring layer 4 is connected to the first wiring layer 101 of the substrate 1 through the first dielectric layer 3, and the first dielectric layer 3 fills the line gaps of the third wiring layer 4 during packaging. The first dielectric layer 3 is made of an insulating material to prevent electrical interference between different lines. By filling the line gaps, parasitic capacitance and inductance caused by the gaps can be reduced, thereby reducing loss and delay in signal transmission and improving the stability and reliability of signal transmission. Meanwhile, a first connecting piece 13 is arranged between the third wiring layer 4 and the chip module 2, the first connecting piece 13 penetrates the first dielectric layer 3, one end of the first connecting piece 13 is connected to the third wiring layer 4, and the other end is connected to the chip module 2, so as to electrically connect the third wiring layer 4 and the chip module 2. The first connecting piece 13 is made of a conductive metal material, such as gold, silver, copper, aluminum, etc. with good electrical conductivity, and preferably the first connecting piece 13 is a copper pillar.

[0038] The packaging structure includes a second dielectric layer 5 and a fourth wiring layer 6, wherein the fourth wiring layer 6 is used for network wiring of a PCB (printed circuit board), and the fourth wiring layer 6 can be made of a metal material with good electrical conductivity. The fourth wiring layer 6 is connected to the third wiring layer 4 through the second dielectric layer 5, and the second dielectric layer 5 fills the line gaps of the third wiring layer 4 during packaging. The second dielectric layer 5 is made of an insulating material to prevent electrical interference between different lines. A second connecting piece 12 is arranged between the fourth wiring layer 6 and the third wiring layer 4, the second connecting piece 12 penetrates the second dielectric layer 5, one end of the second connecting piece 12 is connected to the fourth wiring layer 6, and the other end is connected to the third wiring layer 4, so as to electrically connect the fourth wiring layer 6 and the third wiring layer 4. The second connecting piece 12 is made of a conductive metal material, such as gold, silver, copper, aluminum, etc. with good electrical conductivity, and preferably a copper pillar.

[0039] The second wiring layer 102 is stacked with a third dielectric layer 7, a fifth wiring layer 8, a fourth dielectric layer 9, a fifth dielectric layer 10, and a sixth wiring layer 11; the fifth wiring layer 8 and the chip module 2 are electrically connected through a third connecting piece 14, one end of the third connecting piece 14 is connected to the fifth wiring layer 8, and the other end penetrates the third dielectric layer 7 and is connected to the chip module 2. The thermal conductivity of the fourth dielectric layer 9 is lower than that of the fifth dielectric layer 10.

[0040] Specifically, a third dielectric layer 7 is disposed on the surface of the second wiring layer 102. The third dielectric layer 7 is made of insulating material to prevent electrical interference between different lines. A fifth wiring layer 8 is bonded to the surface of the third dielectric layer 7. The fifth wiring layer 8 is made of a highly conductive metal and is used for network routing on the PCB (Printed Circuit Board). A fourth dielectric layer 9 is bonded to the surface of the fifth wiring layer 8, and a fifth dielectric layer 10 is then bonded to the surface of the fourth dielectric layer 9. The thermal conductivity of the fourth dielectric layer 9 is lower than that of the fifth dielectric layer 10.

[0041] In some preferred embodiments, such as Figure 2 As shown, the chip packaging structure also includes a through-hole connector 15, which penetrates the third wiring layer 4, the first dielectric layer 3, the substrate 1 (including the first wiring layer 101 and the second wiring layer 102), the third dielectric layer 7, and the fifth wiring layer 8. The through-hole connector 15 is a highly conductive metal connector, preferably a copper pillar. Electrical connections between the third wiring layer 4, the first wiring layer 101, the second wiring layer 102, and the fifth wiring layer 8 are achieved through this through-hole connector 15.

[0042] In some preferred embodiments, a plurality of first connectors 13 are provided between the third wiring layer 4 and the chip module 2, and the plurality of connectors 13 are evenly distributed within the area of ​​the chip module 2. The even distribution of the plurality of first connectors 13 helps to more effectively conduct and disperse the heat generated by the chip module, thereby reducing the operating temperature of the chip and improving long-term stability and performance.

[0043] In some preferred embodiments, the fourth dielectric layer 9 is made of an adhesive sheet material composed of 80% filler particles and 20% epoxy resin. The filler particles include aluminum oxide and boron nitride. The fourth dielectric layer 9 has an average thermal conductivity of 2.0 W / mK and a thickness of 60 μm.

[0044] In some preferred embodiments, the fifth dielectric layer 10 is made of an adhesive sheet material composed of 95% filler particles and 5% epoxy resin. The filler particles include aluminum oxide and boron nitride. The average thermal conductivity of the fifth dielectric layer 10 is 3.82 W / mK, and the thickness of the fifth dielectric layer 10 is 60 μm.

[0045] In some preferred embodiments, the first wiring layer 101, the second wiring layer 102, the third wiring layer 4, the fourth wiring layer 6, the fifth wiring layer 8, and the sixth wiring layer 11 are all made of copper plates.

[0046] The thickness of the fifth wiring layer 8 is between 100μm and 120μm.

[0047] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the system described in the present application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A chip package structure, characterized by, The application relates to a substrate, a chip module embedded in the substrate, a first wiring layer arranged on the upper surface of the substrate, a second wiring layer symmetrically arranged on the lower surface of the substrate, a first dielectric layer, a third wiring layer, a second dielectric layer and a fourth wiring layer stacked on the surface of the first wiring layer, a third dielectric layer, a fifth wiring layer, a fourth dielectric layer, a fifth dielectric layer and a sixth wiring layer stacked on the surface of the second wiring layer, a first connecting piece electrically connecting the third wiring layer and the chip module, a second connecting piece electrically connecting the fourth wiring layer and the third wiring layer, the fifth wiring layer and the chip module being electrically connected through a third connecting piece, and the thermal conductivity of the fourth dielectric layer being lower than that of the fifth dielectric layer. The application further comprises a through-hole connecting piece penetrating through the third wiring layer, the first dielectric layer, the substrate, the third dielectric layer and the fifth wiring layer. The fourth dielectric layer is formed by curing adhesive material. The thermal conductivity of the fourth dielectric layer is 2.0 W / mK. The fifth dielectric layer is formed by curing adhesive material.

2. The chip package structure of claim 1, wherein, The thermal conductivity of the fifth dielectric layer is 3.8 W / mK. The third wiring layer and the chip module are electrically connected through a plurality of first connecting pieces which are uniformly distributed in the area of the chip module.

3. The chip package structure of claim 1, wherein, The thickness of the fifth wiring layer is 100-120 mu m.

4. The chip package structure of claim 3, wherein, The sixth wiring layer is made of copper plate.

5. The chip package structure of claim 4, wherein, The substrate is a double-sided copper-clad substrate.

6. The chip package structure of claim 5, wherein, ​ 7. The chip package structure of claim 1, wherein, ​ 8. The chip package structure of claim 1, wherein, ​ 9. The chip package structure of claim 1, wherein, ​ 10. The chip package structure of any one of claims 1 to 9, wherein, ​

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