Radio frequency inductor device

Abstract

A radio frequency inductor device includes an insulator layer and a copper inductor coil having a plurality of turns disposed on the insulator. The copper inductor coil comprises textured copper having an orientation of at least 90% (111).

Description

Technical Field

[0001] This disclosure relates to a radio frequency inductor device. Background Technology

[0002] The following content concerns semiconductor devices and manufacturing technologies, back-end-of-line (BEOL) processing technologies, radio frequency (RF) inductor technologies, BEOL inductor technologies, and related technologies. Utility Model Content

[0003] In some embodiments disclosed herein, the radio frequency inductor device includes an insulating layer and a copper inductor coil having a plurality of turns disposed on the insulating layer. The copper inductor coil comprises textured copper having at least 90% (111) orientation.

[0004] In some embodiments disclosed herein, the radio frequency inductor device includes an insulating layer and a copper inductor coil having a plurality of turns disposed on the insulating layer. The turns of the copper inductor coil have an upper dome away from the insulating layer.

[0005] In some embodiments disclosed herein, the radio frequency inductor device includes an insulating layer, a copper inductor coil having a plurality of turns disposed on the insulating layer, and an interconnect structure. The interconnect structure includes a plurality of patterned metallization layers. The patterned metallization layers are separated by a dielectric material and electrically interconnected by a plurality of conductive vias through the dielectric material, wherein the copper inductor coil is disposed in or on the interconnect structure. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 The diagram illustrates a top view of a radio frequency (RF) inductor coil.

[0008] Figure 2 The diagram illustrates a portion of an RF inductor device along the lines indicated by... Figure 1 A cross-sectional view taken from section SS in the diagram;

[0009] Figure 3 The diagram illustrates a non-restrictive back end-of-line (BEOL) scenario, such as the one shown in the diagram. Figure 1 and Figure 2 RF inductors in the middle;

[0010] Figure 4 and Figure 5 The illustrated diagram can be suitably used as a top view of the additional RF inductor layout as disclosed in this article;

[0011] Figure 6 A flowchart is used to illustrate a non-limiting illustrative example of a manufacturing process used to manufacture RF inductors.

[0012] [Symbol Explanation]

[0013] 6: Radio Frequency (RF) Inductor Devices

[0014] 8: Insulating layer

[0015] 10 HD High-texture (111) copper inductor coil

[0016] 10 oct :Illustrative high-texture (111) copper inductor coil

[0017] 10: High-texture (111) copper inductor coil

[0018] 12: Insulating coating

[0019] 14: Optional encapsulation with polyimide

[0020] 16: Base

[0021] 18: Upper dome

[0022] 30: Semiconductor wafers

[0023] 32: Device Layer

[0024] 34: Underlying patterned metallization layer

[0025] 34 T Topmost patterned metallized layer

[0026] 36: Dielectric materials

[0027] 38: Conductive via

[0028] 40: Interconnection Structure

[0029] 42: Joint gasket

[0030] 44: Through hole

[0031] 50: Operation

[0032] 52: Operation

[0033] 54: Operation

[0034] 56: Operation

[0035] 60: Operation

[0036] 62: Operation

[0037] H1: Coil height

[0038] H2: Height

[0039] H3: Height

[0040] S1: Spacing

[0041] W1: Width

[0042] W2: Distance / Width

[0043] W3: Width Detailed Implementation

[0044] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0045] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0046] Radio frequency (RF) inductors are incorporated into the back-end-of-line (BEOL) processing of integrated circuit (IC) chips for various purposes, such as achieving an improved quality factor (Q-factor) for RF signals. Placing RF inductors in the BEOL process offers certain advantages over forming RF inductors on the semiconductor wafer during the front-end-of-line (FEOL) process. RF inductors are relatively large-area devices, thus occupying valuable wafer space when placed on the semiconductor wafer. BEOL RF inductors can also be positioned close to the RF signal input / output (I / O) ports to / from the IC chip.

[0047] Various factors affect inductor performance, including proximity effect, skin effect, and others. The skin effect refers to the lack of RF penetration into the material, causing the electric field at the RF frequency to be limited to the surface of the inductor material. The skin depth δ of the RF signal in the conductive material is given by the following formula:

[0048]

[0049] Where f is the RF frequency, ρ is the resistivity of the inductor, μ is the permeability of the inductor, and π represents the mathematical constant "pi". A reduced skin depth δ means that a smaller portion of the inductor (specifically, the thin surface portion of the inductor's turns) carries the entire RF load. This can reduce RF coupling efficiency because most of the inductor material is shielded from RF coupling by the skin effect, and due to the potential damage to the inductor itself caused by excessive Joule heating concentrated on the surface of the inductor's conductors. One way to counteract this effect is to use a physically larger inductor to increase the total surface area of ​​the inductor, but this makes miniaturizing the IC chip more difficult.

[0050] As can be seen from equation (1), the skin depth δ decreases with increasing RF frequency f (and therefore the harmful skin effect increases), and decreases with decreasing resistivity ρ. The RF frequency f is usually fixed for a given IC chip design, and therefore what is desired is to reduce the resistivity ρ, which is due to the reduced skin effect caused by the lower resistance of the inductor material.

[0051] The embodiments disclosed herein advantageously provide inductors made of low-resistance copper for BEOL processing. However, manufacturing BEOL inductors from copper has its own advantages. Notably, due to the skin effect, RF current flows on the outer skin of the copper inductor. This causes Joule heating to concentrate on the surface, which can lead to high operating temperatures approaching the melting point of copper (approximately 1084°C for pure copper), resulting in thermal instability.

[0052] To overcome these difficulties, some embodiments of the copper inductors disclosed herein use textured copper with at least 90% (111) orientation and, in some embodiments, at least 97% (111) orientation. In this highly textured (111) copper material, the grain size is predominantly oriented with respect to (111). This has several advantages. It primarily results in low-angle grain boundaries, as most grains have an orientation close to (111). Low-angle grain boundaries reduce the contribution of grain boundaries to the resistance of the highly textured (111) copper material, thus resulting in a lower resistivity ρ of the highly textured (111) copper material compared to other types of copper. Compared to other oriented highly textured copper materials (e.g., highly textured (101) copper), the highly textured (111) copper material also exhibits improved hardness, electromigration, and oxidation resistance.

[0053] In some embodiments, copper inductor coils are advantageously formed on an insulating layer by plating, which can produce high-texture (111) copper material with at least 90% (111) orientation and, in some embodiments, at least 97% (111) orientation. Characterization techniques such as X-ray diffraction (XRD), electron backscatter diffraction (EBSD), and scanning electron microscopy (SEM) can be used to quantitatively measure the percentage of copper with the desired (111) orientation, thus enabling empirical determination of the percentage (111) orientation of the high-texture (111) copper material. Plating parameters such as pulse current magnitude and frequency, as well as plating temperature, can be empirically optimized using test passes characterized by XRD and / or EBSD to optimize the plating and obtain high-texture (111) copper material with the desired at least 90% (111) or at least 97% (111) orientation. In some embodiments, both forward and backward pulses can be used during the plating process. The choice of seed layer can also affect the texture and can be similarly optimized empirically.

[0054] In some embodiments, the copper inductor coil is advantageously modified to include an upper dome on the turns of the copper inductor coil. The upper dome increases the total surface area of ​​the turns of the copper inductor coil, thus providing improved RF coupling by means of the increased total surface area without the accompanying increase in the layout area occupied by the RF inductor.

[0055] In some embodiments, two of these features are combined: the copper inductor coil comprises textured copper having at least 90% (111) orientation and, in some embodiments, at least 97% (111) orientation; and also includes an upper dome on the turns of the copper inductor coil. The resulting inductor advantageously has improved electrical performance (e.g., lower resistance and higher Q factor) as well as improved stiffness and thermal stability.

[0056] See now Figure 1 and Figure 2 The radio frequency (RF) inductor device 6 is shown in the top view ( Figure 1 ) and along the instructions Figure 1 The section SS line in the drawing is shown in Figure 2 A cross-section is shown in the diagram. The RF inductor device 6 includes an insulating layer 8 and a copper inductor coil 10 (i.e., inductor 10) disposed on the insulating layer 8. The copper inductor coil 10 has a plurality of turns (illustrated four turns), but the number of turns can be one, two, three, illustrated four, five, six, or more. Typically, the inductance increases with increasing number of turns (ideally, the inductance increases with the square of the number of turns, although this assumes that perfect coupling between the turns is not usually the case). In some IC chip designs, it is preferable to limit the number of turns, because increasing the number of turns increases the layout area of ​​the inductor 12, which may be undesirable when minimizing the IC chip size is required. Although Figure 1 A top view of an RF inductor device 6 including a copper inductor coil 10 is shown, but... Figure 2 The cross section SS is illustrated, which includes additional components that may be included, such as the aforementioned insulating layer 8 and one or more dielectric overlays such as an insulating coating 12 disposed on the copper inductor coil 10 (and, if necessary, above the portion of the insulating layer 8 not covered by the copper inductor coil 10), and polyimide 14 (and its insulating coating 12) encapsulating the copper inductor coil 10.

[0057] The copper inductor coil 10 is made of textured copper having at least 90% (111) orientation and more preferably at least 97% (111) orientation. As discussed, this highly textured (111) copper offers advantages over other forms of copper because it provides benefits such as reduced resistance (for a given inductor coil layout / number of turns) and improved hardness, electromigration, and oxidation resistance compared to other coils made of other types of copper. Using highly textured (111) copper can provide improvements in the RF performance and reliability of the inductor 10, including improved electrical performance (e.g., lower resistance and higher Q factor) and improved hardness and thermal stability. Generally, these benefits increase with increasing percentage of (111) orientation. In some embodiments, at least 97% (111) orientation is preferred to achieve the desired low resistance and high thermal stability of the highly textured (111) copper inductor coil 10.

[0058] Without losing generality, Figure 2 The diagram illustrates the dimensions of a high-texture (111) copper inductor coil 10, including the height H1 transverse to the height of the insulating layer 8, the width W1 of the turns of the high-texture (111) copper inductor coil 10, and the spacing S1 between adjacent turns of the copper inductor coil 10. Figure 2 As can be seen, the spacing S1 is measured from one edge of a turn to the nearest edge of the next turn. Dimensions H1, W1, and S1 are selected for ease of handling / manufacturing of the copper inductor coil 10 and for the reliability of the copper inductor coil 10. Based on these considerations, in some non-limiting illustrative embodiments, the coil height H1 is in the range of 1 micrometer to 7 micrometers (i.e., 1 μm ≤ H1 ≤ 7 μm), the turn width W2 is in the range of 1 micrometer to 50 micrometers (i.e., 1 μm ≤ W1 ≤ 50 μm), and the spacing S1 is in the range of 1 micrometer to 50 micrometers (i.e., 1 μm ≤ W1 ≤ 50 μm).

[0059] In the illustrative embodiment, the turns of inductor 10 include bases 16 disposed on insulating layer 8 and extending away from the opposite side of each turn by a distance W2 (indicated by...). Figure 2 (in the middle). In some non-limiting illustrative embodiments, the distance W2 is between 0.1 μm and 1 μm (i.e., 0.1 μm ≤ W2 ≤ 1 μm). The base 16 is optional (or in other words, expected until W2 = 0). The insulating coating 12 has indicators indicating... Figure 2 The width W3 is specified in the figure. In some non-limiting illustrative embodiments, the thickness W3 is in the range of 0.5 μm to 2 μm (i.e., 0.5 μm ≤ W3 ≤ 2 μm). Furthermore, these ranges of W2 and W3 are selected for ease of handling / manufacturing of the copper inductor coil 10 and for the reliability of the copper inductor coil 10, and should be considered as non-limiting illustrative examples.

[0060] like Figure 2 As can be seen, the turns of the copper inductor coil 10 have upper domes 18 on the turns of the copper inductor coil. The upper dome 18 of each turn is located away from the insulating layer 8. As previously discussed, the upper dome 18 increases to the total surface area of ​​the inductor 10 compared to the turns having a planar top surface, thus advantageously increasing the total surface area of ​​RF coupling to improve the overall RF coupling of the inductor 10. In some non-limiting illustrative examples, the upper dome 18 may have a height H2 in the range of 0.2 μm to 1 μm (i.e., 0.2 μm ≤ H2 ≤ 1 μm). The height H2 is measured along the total height H1 of the coil 10 along the same height direction transverse to the insulating layer 8, and as... Figure 2 As can be seen, the total height H1 of coil 10 includes the height H2 of dome 18. For example... Figure 2 As can be further seen, the polyimide 14 of the encapsulated inductor 10 extends to a height H3 above the top of the dome 18 (again in the height direction). In some non-limiting illustrative embodiments, the height H3 is in the range of 1 micrometer to 7 micrometers (i.e., 1 μm ≤ H3 ≤ 7 μm). Furthermore, these ranges of H2 and H3 are selected for ease of handling / manufacturing of the copper inductor coil 10 and for the reliability of the copper inductor coil 10, and should be considered as non-limiting illustrative examples.

[0061] Insulating layer 8 and optional insulating coating 12 may comprise any suitable electrical insulating material, such as (by means of non-limiting illustrative examples) oxides (e.g., stoichiometric SiO2 or non-stoichiometric Si). x O y (where 0 < (x, y) < 1), nitrides (e.g., stoichiometric Si3N4 or non-stoichiometric Si) x N y , where 0<(x,y)<1), silicon oxynitride, multilayers of two or more insulating materials, etc.

[0062] See Figure 3 , Figure 1 and Figure 2The RF inductor device 6 is shown in cross-section during BEOL processing. A typical manufacturing process for integrated circuits (ICs) includes front-end-of-line (FEOL) and back-end-of-line (BEOL) processing stages. During FEOL processing, various electronic, optoelectronic, photonic, or other devices, such as transistors, photodetectors, etc., are fabricated on and / or in semiconductor wafers 30, such as silicon, silicon-on-insulator (SOI), germanium, gallium arsenide (GaAs), or other semiconductor wafers. This creates layers or regions of semiconductor devices 32 on the surface of the semiconductor wafer 30. For example, as a non-limiting illustrative example, these devices could be RF signal processing devices.

[0063] The BEOL process follows the FEOL process and includes the formation of a stack of patterned metallization layers 34 separated by a dielectric material 36, sometimes referred to as an intermetallic dielectric (IMD) material 36. The patterned metallization layers 34 may, by means of non-limiting illustrative examples, comprise conductive materials such as copper, aluminum, copper alloys, or aluminum alloys. The patterned metallization layers 34 are typically not high-texture (111) copper, although high-texture (111) copper is expected from the patterned metallization layers 34. The IMD material 36 is typically an oxide, such as silicon dioxide (SiO2), formed by plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or another deposition technique. Conductive vias 38 interconnect the patterned metallization layers 34 through the IMD material 36. The vias 38 may, for example, comprise tungsten, copper, or another conductive material. A typical BEOL process sequence involves a series of repetitive stacks necessary to establish the patterned metallization layers 34. Each iteration may include, for example, depositing an IMD material on a previous patterned metallization layer (or on a layer or region of the semiconductor device 32 in the case of an initial MO metallization layer); photolithographically processing the IMD material to form a via opening through the IMD material for accessing the previous patterned metallization layer (or a layer or region of the semiconductor device 32 in the case of an initial MO metallization layer); subsequently metallizing to fill the via opening to form a via 38; and depositing and photolithographically patterning a next metallization layer. This process can be repeated to build a stack of patterned metallization layers 34. The stack of patterned metallization layers 34 and the interconnect vias 38 formed during the BEOL process provide conductive circuitry for interconnecting transistors, photodetectors, and / or other devices formed on the surface of the semiconductor device 32 on the semiconductor wafer 10 during the FEOL process.

[0064] The stacked structure including the patterned metallization layer 34 and the IMD material 36 can, for example, constitute the interconnect structure 40. In some embodiments, the topmost patterned metallization layer 34 T These act as contact surfaces to bond the overall device (e.g., device layer 32 and interconnect structure 40) to a printed circuit board, another IC chip, or the like (not shown). Bonding pads 42 (only one representative example is shown in...) Figure 3 (The middle) can be formed on the top surface of the interconnect structure 40 (e.g., the topmost patterned metallization layer 34). TThe above (not shown) serves as under-bump metallization (UBM) for bonding bumps used to bond IC chips to printed circuit boards, other IC chips, or the like. Bonding bumps can be solder bumps, copper balls, solder-coated copper balls, or the like.

[0065] Typically, the bonding bump 42 is formed of copper or a copper alloy. However, in some embodiments, it is anticipated that the bonding pad 42 may also be made of high-texture (111) copper, and in such embodiments, the formation of the high-texture (111) copper bonding bump 42 may be performed simultaneously with the formation of the high-texture (111) copper inductor coil 10 in a single plating process that forms both the high-texture (111) copper bonding bump 42 and the high-texture (111) copper inductor coil 10.

[0066] Continue reading Figure 3 And look back further Figure 1 and Figure 2 The high-texture (111) copper inductor coil 10 is electrically connected to the interconnect structure 40, for example, through the via 44 of the insulating layer 8, and to the topmost patterned metallization layer 34. T Electrical connection to contact the topmost patterned metallization layer 34 T The via 44 can be formed from the same high-texture (111) copper material used to form the high-texture (111) copper inductor coil 10, and can be formed, for example, by the same process (e.g., plating) used to form the copper inductor coil 10. That is, the plating process can be operated to fill the via opening formed in the insulating layer 8 in the form of optical lithography with high-texture (111) copper to form the via 44, and the plating process continues to form the high-texture (111) copper inductor coil 10. Note that the high-texture (111) copper inductor coil 10 is electrically connected to the patterned metallization layer 34 by the via 44. T Typically not formed from high-texture (111) copper (i.e., interconnect metallization layer 34) T It is not typically formed from high-texture (111) copper. However, it is instead expected to be formed via the interconnected metallization layer 34. T It is also made of high-texture (111) copper.

[0067] Figure 1 The diagram illustrates the possible orientation of the through-hole 44 at the opposite ends of the spiral coil 10. (Note that the through-hole 44 is below the high-texture (111) copper inductor coil 10, and therefore the through-hole 44 is...) Figure 1 In a top view, it is usually not visible, therefore through hole 44 is... Figure 1 The directions indicated in the diagram should be considered as a graphical representation. However, please note that the directions shown in the diagram are not graphical representations. Figure 1 The orientation of the through hole 44 is merely a non-limiting illustrative example.

[0068] The RF inductor device 6, and more specifically the high-texture (111) copper inductor coil 10, can serve various functions within an IC chip. For example, the high-texture (111) copper inductor coil 10 can act as an inductor in an LC (inductor-capacitor), RL (resistor-inductor), or RLC (resistor-inductor-capacitor) sub-circuit of the IC chip's RF circuitry. For example, the LC or RLC circuit can form a resonant circuit that performs RF filtering, improves the Q factor in RF signal processing, and so on. These are merely some non-limiting illustrative examples.

[0069] exist Figure 3 In one example, an RF inductor device 6 comprising a high-texture (111) inductor coil 10 is formed on the top surface of the interconnect structure 40 (and thus disposed thereon); that is, formed on / disposed on the surface of the interconnect structure 40 opposite to the layer or region of the semiconductor device 32. However, it is contemplated alternatively to have an RF inductor device 6 embedded within the interconnect structure. For example, if the interconnect structure comprises 10 patterned metallization layers 34 (enumerated as layers M0 to M9 without loss of versatility), then as a non-limiting example, the first 5 patterned metallization layers 34 (i.e., layers M0 to M4) may be formed, followed by the formation of the RF inductor device 6 and contact with the M4 patterned metallization layer via via 44, and then the formation of the next 5 patterned metallization layers (i.e., layers M5 to M9).

[0070] Looking back Figure 1 The illustrative high-texture (111) copper inductor coil 10 is rectangular and includes four turns. However, the above is merely a non-limiting illustrative example. Both the number of turns and the geometry of the turns can be selected based on various factors, such as the desired inductance, the acceptable layout area occupied by the high-texture (111) copper inductor coil, etc. Generally, the inductance increases with the number of turns; ideally, the inductance increases with the square of the number of turns. On the other hand, more turns can increase the layout area of ​​the inductor, which may not be desirable when minimizing the IC chip is the goal.

[0071] See Figure 4 and Figure 5 Two additional non-limiting illustrative examples are shown illustrating suitable layouts of high-texture (111) copper inductor coils. Figure 4 In one example, a high-texture (111) copper inductor coil 10 oct It is an octagon, meaning it has eight sides. In other words, Figure 4 High-textured (111) copper inductor coil 10 oct The shape of the turn is octagonal. Figure 4 Illustrative high-texture (111) copper inductor coil 10 octIt has nine (9) octagonal turns; however, the number of turns can be selected for the application (e.g., the desired inductance and layout area).

[0072] exist Figure 5 In one example, a high-texture (111) copper inductor coil 10 HD It is rectangular, that is, it has rectangular turns, such as in Figure 1 In general, this is the case in the embodiments. However, the high-texture (111) copper inductor coil 10 HD Compared to Figure 1 The high-texture (111) copper inductor coil 10 has more turns. Figure 5 Illustrative high-texture (111) copper inductor coil 10 HD It has eleven (11) rectangular turns. Furthermore, Figure 5 High-textured (111) copper inductor coil 10 HD These 11 turns are packaged at a higher density by reducing the spacing S1 between adjacent turns (where S1 is previously referred to). Figure 2 (Definition). Trade-offs can exist in such designs – for example, reducing the spacing S1 can provide a more compact inductor, but if the inductor operates at high voltage, a smaller spacing S1 can increase the likelihood of voltage arcs across adjacent turns.

[0073] Figure 4 and Figure 5 The diagram also shows the connection between the inductor and the underlying patterned metallization layer 34. T Different options for the orientation of through hole 44. Figure 4 In the embodiment, the high-texture (111) copper inductor coil 10 oct It has connecting through holes 44 distributed along the length of the octagonal coil. Figure 5 In this example, the connecting through-holes 44 are divided into four groups connecting the outermost fourth to tenth turns, along with five through-holes 44 contacting the end of the innermost turn and ten through-holes 44 contacting the end of the outermost turn. Furthermore, it should be understood that the orientation of the through-holes 44 is graphically indicated on... Figure 4 and Figure 5 In fact, through-hole 44 is positioned for individual high-texture (111) copper inductor coils 10 oct and 10 HD Below, and therefore from Figure 4 and Figure 5 The view in the top view is obscured.

[0074] Despite Figure 4 and Figure 5 These are not visible in the top view, but it should be understood that these embodiments may be visible as needed for individual high-texture (111) copper inductor coils 10 oct and 10 HDThe turns include an upper dome 18. In some embodiments, each high-texture (111) copper inductor coil 10 oct and 10 HD The high-texture (111) copper material has at least 90% (111) orientation, and in some embodiments at least 97% (111) orientation.

[0075] Furthermore, it should be understood that Figure 1 , Figure 4 and Figure 5 The coil layout examples are merely non-limiting illustrative examples. More generally, high-texture (111) copper inductor coils may have turns with various geometries (e.g., rectangular, hexagonal, octagonal, etc.) and may generally have any number of turns (e.g., one turn, two turns, three turns, five turns, ten turns, fifteen turns, etc.).

[0076] See now Figure 6 This describes a suitable method for manufacturing an RF inductor device 6, which includes a high-texture (111) copper inductor coil 10. Figure 6 Method assumptions Figure 3 The interconnection structure 40 has been formed. That is, Figure 6 The method begins after the interconnect structure 40 is formed. (However, if the RF inductor device 6 is embedded in the interconnect structure 40, then...) Figure 6 The method can be performed after some, but not all, of the patterned metallization layers 34 have been formed, after which the following will be executed. Figure 6 The method is followed by the formation of a residual patterned metallization layer 34 for the interconnect structure.

[0077] Figure 6The method begins with operation 50, in which an insulating layer 8 is deposited on the interconnect structure 40, and openings for vias 44, designated to be filled, are opened in the insulating layer 8 by optical lithography. Operation 50 may make it necessary to form an insulating layer 8 of a suitable electrical insulating material, such as oxides, nitrides, silicon oxide, silicon nitride or silicon oxynitride, multilayers of two or more insulating materials, etc. The insulating layer 8 may be formed by any suitable deposition technique for depositing insulating materials, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The opening for the via 44 is suitably formed by optical lithography, that is, a photoresist layer (not shown) is placed on the blanket-covered insulating layer 8 and exposed by a photomask, and the exposed photoresist is developed to form an opening in the photoresist that is aligned with the opening to be formed in the insulating layer 8, followed by suitable chemical etching, followed by photoresist stripping, the chemical etching etching the opening in the insulating layer 8 through the opening in the photoresist.

[0078] In operation 52, a patterned seed layer for subsequent plating of the high-texture (111) copper inductor coil 10 is deposited by PVD, CVD, or another suitable technique. The seed layer may be copper, but may be another conductive material suitable for seed plating of high-texture (111) copper. The patterned seed layer is typically thin, for example, substantially thinner than the height H1 of the plated high-texture (111) copper inductor coil 10 (see [link to relevant documentation]). Figure 2 (as defined in H1). Operation 52 may, for example, include depositing a seed material blanket and then optically lithographically patterning the blanket to form a patterned seed layer of copper or another suitable seed material.

[0079] In operation 54, the high-texture (111) copper inductor coil 10 is formed by plating. The parameters of the plating (also referred to in this art as electrochemical deposition or electrode deposition) are selected to form a high-texture (111) copper material with the desired high texture (e.g., at least 90% (111) orientation and, in some embodiments, at least 97% (111) orientation). As previously mentioned, plating parameters such as pulse current magnitude and frequency, and plating temperature, are appropriately optimized empirically using test passes, in which the desired thickness (e.g., corresponding to...) is determined. Figure 2The high-texture (111) copper layers of the desired coil height H1 indicated in the figure are formed with different plating parameters; and the texture of each high-texture (111) copper layer is characterized by XRD, EBSD and / or SEM to determine the percentage (111) orientation in each test layer. The selection of the patterned seed layer formed in operation 52 can be similarly (commonly) optimized. In some embodiments, the plating performed in operation 54 may use both forward pulses and backward pulses during the plating process, which may increase the (111) texture.

[0080] It is noteworthy that the plated area is limited to the patterned seed layer formed in the previous operation 52. This is because the electrically insulating layer 8 is not a suitable conductor for the plated process. Therefore, the high-texture (111) copper inductor coil 10 (or alternatively, Figure 4 The embodiment of the high-texture (111) copper inductor coil 10 oct or Figure 5 The embodiment of the high-texture (111) copper inductor coil 10 HD The layout of the crystal layer is determined by the optical lithography patterning of the seed layer.

[0081] The bonding pad 42 may be made of a material such as aluminum or an aluminum alloy. However, in some intended embodiments, some or all of the bonding pads 42 (see [link to original text]) Figure 3 (and related discussions) can be performed using high-texture (111) copper in operations 52 and 54. In doing so, the patterning of the seed layer in operation 52 includes forming a seed layer portion corresponding to both the high-texture (111) copper inductor coil 10 and the bonding pad 42. In this manner, subsequent plating operation 54 plating high-texture (111) copper material onto the patterned seed layer portion corresponding to the coil, thus forming the high-texture (111) copper inductor coil 10, and also plating high-texture (111) copper material onto the portion of the patterned seed layer corresponding to the bonding pad 42 (thus forming the same high-texture (111) copper plated bonding pad 42 along with the formation of the coil 10). It should be understood that the bonding pad 42 can similarly benefit from being formed of high-texture (111) copper material, thus granting the bonding pad 42 benefits such as reduced resistance and improved thermal stability.

[0082] In embodiments where the turns of the high-texture (111) copper inductor coil 10 include an upper dome 18, the above can be achieved subsequently in operation 56 by a suitable etching process. In a non-limiting illustrative approach, isotropic etching can be applied, which is due to the presence of two exposed surfaces (i.e., a top surface and a side surface) at the upper corner, which will preferably be etched at that corner of the turn. This preferred etching of the corner forms the upper surface of the turn into the desired shape of the upper dome 18. Furthermore, empirical optimization can be performed, for example, using cross-sectional SEM to directly image the shape of the dome 18 achieved for different etching parameters. It should be understood that etching can also help form optional feet 16 of the turns of the high-texture (111) copper inductor coil 10.

[0083] In operation 60, an optional insulating coating 12 may be applied to the high-texture (111) copper inductor coil 10 (and, if necessary, to the portion of the copper inductor coil 10 between the turns of the surface of the insulating layer 8). The insulating coating 12 may be formed by any suitable deposition technique (e.g., PVD, CVD, etc.) and may contain any suitable electrical insulating material, such as oxides, nitrides, silicon oxide, silicon nitride or silicon oxynitride, multilayers of two or more insulating materials, etc.

[0084] In operation 62, optional encapsulated polyimide 14 is formed. In one method, polyimide material is deposited up to at least H1+H3 (wherein H1 and H3 are as follows). Figure 2 The thickness (defined in the diagram) is then subjected to chemical mechanical polishing to planarize the upper surface of the polyimide, resulting in a surface with... Figure 2 The final thickness shown in the figure (e.g., the thickness H3 above the top force of the upper dome 18 of coil 10).

[0085] exist Figure 6 In the illustrative method, the high-texture (111) copper inductor coil 10 is formed in operation 54 by plating, wherein the high-texture (111) copper is plated on a patterned seed layer formed in operation 52. However, other methods for forming the high-texture (111) copper inductor coil 10 are contemplated, such as sputtering as another non-limiting illustrative example. In this illustrative alternative embodiment (not shown), operations 52 and 54 are replaced by sputtering operations to form a blanket layer of high-texture (111) copper, followed by suitable optical lithography patterning of the blanketed high-texture (111) copper to form the high-texture (111) copper inductor coil 10.

[0086] Some other embodiments are described below.

[0087] In a non-limiting illustrative embodiment, a method for forming a radio frequency (RF) inductor device is disclosed. The method includes forming an insulating layer and forming a copper inductor coil by plating onto the insulating layer. The copper inductor coil comprises textured copper having at least 90% (111) orientation.

[0088] In some embodiments, the copper inductor coil comprises textured copper with at least 97% (111) orientation. In some embodiments, an insulating coating is deposited over the copper inductor coil. In some embodiments, after depositing the insulating coating, the copper inductor coil is encapsulated in polyimide. In some embodiments, an upper dome is formed on a plurality of turns of the copper inductor coil. In some embodiments, the plurality of turns of the copper inductor coil are rectangular or octagonal. In some embodiments, a back-end processing is performed to form a plurality of patterned metallization layers, the plurality of patterned metallization layers being separated by a dielectric material and electrically interconnected by a plurality of conductive vias through the dielectric material; wherein the copper inductor coil is formed as part of the BEOL processing and is electrically connected to at least one of the plurality of patterned metallization layers.

[0089] In a non-limiting illustrative embodiment, a method for forming an RF inductor device is disclosed. The method includes: forming a semiconductor device on a semiconductor wafer; after forming the semiconductor device, forming an interconnect structure comprising a plurality of patterned metallization layers separated by a dielectric material on the semiconductor wafer; and forming a copper inductor coil plated on the interconnect structure. The copper inductor coil comprises textured copper having at least 90% (111) orientation. The plated copper inductor coil is electrically connected to at least one patterned metallization layer of the interconnect structure.

[0090] In some embodiments, the copper inductor coil comprises textured copper with at least 97% (111) orientation. In some embodiments, an upper dome is formed on a plurality of turns of the copper inductor coil.

[0091] In a non-limiting illustrative embodiment, the RF inductor device includes an insulating layer and a copper inductor coil having a plurality of turns disposed on the insulator. The copper inductor coil comprises textured copper having at least 90% (111) orientation.

[0092] In some embodiments, the copper inductor coil comprises textured copper having at least 97% (111) orientation. In some embodiments, the copper inductor coil has a height between 1 micrometer and 7 micrometers in a height direction transverse to the insulating layer, and the plurality of turns of the copper inductor coil have a width between 1 micrometer and 50 micrometers. In some embodiments, the plurality of turns of the copper inductor coil are spaced apart by a distance between 1 micrometer and 50 micrometers. In some embodiments, the plurality of turns of the copper inductor coil further include a plurality of feet disposed on the insulating layer and extending away from a plurality of opposite sides of the turn by a distance between 0.1 micrometer and 1 micrometer. In some embodiments, an insulating coating is disposed above the copper inductor coil, the insulating coating having a thickness between 0.5 micrometers and 2 micrometers. In some embodiments, the plurality of turns of the copper inductor coil have an upper dome away from the insulating layer. In some embodiments, the copper inductor coil including the upper dome has a height between 1 micrometer and 7 micrometers in a height direction transverse to the insulating layer, and the dome has a height between 0.2 micrometers and 1 micrometer in the same height direction. In some embodiments, the plurality of turns of the copper inductor coil have an upper dome located away from the insulating layer. In some embodiments, the RF inductor device includes an interconnect structure comprising a plurality of patterned metallization layers separated by a dielectric material and electrically interconnected by a plurality of conductive vias through the dielectric material, wherein the copper inductor coil is disposed in or on the interconnect structure, and at least two electrical conductors passing through a high insulating layer and connecting the copper inductor coil to at least one patterned metallization layer of the interconnect structure.

[0093] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A radio frequency inductor device, characterized in that, Include: An insulating layer; and A copper inductor coil having a plurality of turns disposed on the insulating layer, wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation, the plurality of turns having an upper dome away from the insulating layer.

2. The radio frequency inductor device as claimed in claim 1, characterized in that, The copper inductor coil contains textured copper with at least 97% (111) orientation.

3. The radio frequency inductor device as described in claim 2, characterized in that, in: The copper inductor coil has a height between 1 micrometer and 7 micrometers in a direction transverse to the height of the insulating layer; and The multiple turns of the copper inductor coil have a width between 1 micrometer and 50 micrometers.

4. The radio frequency inductor device as described in claim 3, characterized in that, The multiple turns of the copper inductor coil are separated by a distance between 1 micrometer and 50 micrometers.

5. The radio frequency inductor device as described in claim 3, characterized in that, The plurality of turns of the copper inductor coil further include a plurality of base feet disposed on the insulating layer and extending away from a plurality of opposite sides of the turn at a distance between 0.1 micrometers and 1 micrometer.

6. The radio frequency inductor device as claimed in claim 3, characterized in that, Further includes: An insulating coating is placed above the copper inductor coil, the insulating coating having a thickness between 0.5 micrometers and 2 micrometers.

7. A radio frequency inductor device, characterized in that, Include: An insulating layer; and A copper inductor coil having a plurality of turns disposed on the insulating layer, wherein the plurality of turns of the copper inductor coil have an upper dome away from the insulating layer.

8. The radio frequency inductor device as claimed in claim 7, characterized in that, in: The copper inductor coil, including the upper dome, has a height between 1 micrometer and 7 micrometers in a height direction transverse to the insulating layer; and The dome has a height between 0.2 micrometers and 1 micrometer in this height direction.

9. A radio frequency inductor device, characterized in that, Include: An insulating layer; A copper inductor coil having a plurality of turns disposed on the insulating layer, the plurality of turns having an upper dome away from the insulating layer; and An interconnect structure comprising a plurality of patterned metallization layers separated by a dielectric material and electrically interconnected by a plurality of conductive vias through the dielectric material, wherein a copper inductor coil is disposed in or on the interconnect structure.

10. The radio frequency inductor device as claimed in claim 9, characterized in that, Further includes: At least two electrical conductors pass through a high insulating layer and connect the copper inductor coil to at least one patterned metallization layer of the interconnect structure.

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