BMS equalization circuit

Abstract

The utility model relates to a BMS equalization circuit. The BMS equalization circuit comprises an anti-surge module, an equalization module and a charge and discharge control module, the anti-surge module is connected with the equalization module, and the charge and discharge control module is respectively connected with the anti-surge module and the equalization module; the anti-surge module comprises a first resistor, a first capacitor and a diode, and the equalization module comprises a first-stage equalization sub-module and a second-stage equalization sub-module; the first-stage equalization sub-module comprises a first battery cell, a second resistor, a third resistor, a second capacitor, a first inductor and a first switching tube, and the second-stage equalization sub-module comprises a second battery cell, a fourth resistor, a third capacitor, a second inductor and a second switching tube. The BMS equalization circuit can enable the electric quantity of each battery cell to be equalized and consistent, has the characteristic of surge impact prevention, and can prolong the service life of the battery pack.

Description

TECHNICAL FIELD

[0001] The utility model relates to battery management system technical field especially relates to a BMS equalization circuit. BACKGROUND

[0002] BMS equalization circuit is an important component in battery management system, its main function is balancing the charge level of each battery unit in battery pack, ensuring that the battery pack can run normally and prolonging battery life.

[0003] BMS equalization circuit adjusts the current between the batteries, so that the charge of each battery remains relatively balanced. In the battery pack, due to the capacity, internal resistance and charge / discharge characteristics of each battery may be different, which will cause some batteries to charge or discharge faster, while other batteries are relatively slow. Overcharged or over-discharged batteries may be damaged or affect the performance of the entire battery pack. Therefore, the role of BMS equalization circuit is to pass current between batteries to ensure that the charge of each battery remains at a relatively uniform level. In the related art, the BMS equalization circuit has poor adaptability when subjected to inrush current impact, and normal work is easily affected. SUMMARY

[0004] Therefore, it is necessary to provide a BMS equalization circuit to solve the problem that the BMS equalization circuit has poor adaptability when subjected to inrush current impact and normal work is easily affected.

[0005] A BMS equalization circuit, comprising a surge protection module, an equalization module and a charge and discharge control module, the surge protection module is connected with the equalization module, and the charge and discharge control module is connected with the surge protection module and the equalization module respectively;

[0006] The surge protection module comprises a first resistor, a first capacitor and a diode, and the equalization module comprises a first-stage equalization submodule and a second-stage equalization submodule;

[0007] The first-stage equalization submodule comprises a first battery cell, a second resistor, a third resistor, a second capacitor, a first inductor and a first switch tube, and the second-stage equalization submodule comprises a second battery cell, a fourth resistor, a third capacitor, a second inductor and a second switch tube;

[0008] One end of the first resistor and one end of the first capacitor are grounded, the other end of the first resistor is connected to one end of the second resistor and the negative electrode of the first battery, the other end of the second resistor is connected to one end of the second capacitor, the other end of the first capacitor and the drain of the first switch tube, the positive electrode of the first battery is connected to the negative electrode of the second battery and one end of the third resistor, the other end of the third resistor is connected to the other end of the second capacitor, one end of the third capacitor and one end of the first inductor, the other end of the first inductor is connected to the source of the first switch tube and the drain of the second switch tube, one end of the fourth resistor is connected to the positive electrode of the second battery, the other end of the fourth resistor is connected to the other end of the third capacitor and one end of the second inductor, the other end of the second inductor is connected to the source of the second switch tube, the positive electrode of the diode is grounded, and the negative electrode of the diode is connected to the other end of the second resistor.

[0009] The positive electrode of the second battery, the other end of the second inductor, the gate of the second switch tube, the other end of the first inductor, the gate of the first switch tube, the other end of the second resistor and one end of the first resistor are connected to the charge and discharge control module.

[0010] In one embodiment, the charge and discharge control module includes a fifth resistor and a single-chip microcomputer.

[0011] The positive electrode of the second battery is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to a charging power supply or a power consumption load.

[0012] The other end of the second inductor, the gate of the second switch tube, the other end of the first inductor, the gate of the first switch tube, the other end of the second resistor and one end of the first resistor are connected to the single-chip microcomputer.

[0013] In one embodiment, the equalization module further includes an Nth equalization sub-module, where N≥3 and N is an integer.

[0014] The positive electrode of the second battery is connected to one end of the fifth resistor through the Nth equalization sub-module, and the Nth equalization sub-module includes N batteries, N resistors, N capacitors, N inductors and N switch tubes.

[0015] The positive electrode of the N-level electric core is connected with one end of the N-level resistor, the other end of the N-level resistor is connected with one end of the N-level capacitor and one end of the N-level inductor respectively, the other end of the N-level inductor is connected with the source electrode of the N-level switch tube, the negative electrode of the N-level electric core is connected with the positive electrode of the corresponding electric core of the N-1-level balancing sub-module, the other end of the N-level capacitor is connected with one end of the corresponding inductor of the N-1-level balancing sub-module, and the drain electrode of the N-level switch tube is connected with the source electrode of the corresponding switch tube of the N-1-level balancing sub-module.

[0016] The positive electrode of the N-level electric core is also connected with one end of the fifth resistor, the other end of the N-level inductor and the gate electrode of the N-level switch tube are connected with the single-chip microcomputer respectively.

[0017] In one of the embodiments, the first inductor and the second inductor are energy storage inductors.

[0018] In one of the embodiments, the first switch tube and the second switch tube are MOS tubes.

[0019] In one of the embodiments, the first switch tube and the second switch tube are n-type MOS tubes.

[0020] In one of the embodiments, the second capacitor and the third capacitor are energy storage capacitors.

[0021] In one of the embodiments, the N-level switch tube is a MOS tube.

[0022] In one of the embodiments, the N-level switch tube is an n-type MOS tube.

[0023] In one of the embodiments, the N-level capacitor is an energy storage capacitor, and the N-level inductor is an energy storage inductor.

[0024] When the above BMS balancing circuit works, the electric energy can be transferred between the first electric core and the second electric core through the control of the charge and discharge control module, so that the electric quantity of the first electric core and the second electric core is kept balanced and consistent, and the service life of the battery pack is effectively improved; and the surge pulse can be effectively absorbed, thereby improving the stability of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a circuit principle diagram of the BMS balancing circuit of one embodiment of the utility model;

[0026] Figure 2 It is a circuit principle diagram of the BMS balancing circuit of another embodiment of the utility model. DETAILED DESCRIPTION

[0027] For the above purposes, features and advantages of the present application to be more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, a number of specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of different manners other than those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0028] It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or there can be intervening elements. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical", "horizontal", "left", "right", and the like as used herein are for purposes of illustration and description only.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] The utility model discloses a kind of BMS equalization circuits.

[0031] As Figure 1 As shown in the figure, the BMS equalization circuit includes surge protection module, equalization module and charge-discharge control module, surge protection module is connected with equalization module, and charge-discharge control module is connected with surge protection module and equalization module respectively.

[0032] Surge protection module includes first resistor R1, first capacitor C1 and diode D1, and equalization module includes first equalization submodule and second equalization submodule.

[0033] First equalization submodule includes first battery cell CELL1, second resistor R2, third resistor R3, second capacitor C2, first inductor L1 and first switch tube Q1, and second equalization submodule includes second battery cell CELL2, fourth resistor R4, third capacitor C3, second inductor L2 and second switch tube Q2.

[0034] One end of the first resistor R1 and one end of the first capacitor C1 are grounded, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the negative electrode of the first battery cell CELL1, the other end of the second resistor R2 is connected to one end of the second capacitor C2, the other end of the first capacitor C1 and the drain of the first switch tube Q1, the positive electrode of the first battery cell CELL1 is connected to the negative electrode of the second battery cell CELL2 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the other end of the second capacitor C2, one end of the third capacitor C3 and one end of the first inductor L1, the other end of the first inductor L1 is connected to the source of the first switch tube Q1 and the drain of the second switch tube Q2, the positive electrode of the second battery cell CELL2 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the other end of the third capacitor C3 and one end of the second inductor L2, the other end of the second inductor L2 is connected to the source of the second switch tube Q2, the positive electrode of the diode D1 is grounded, and the negative electrode of the diode D1 is connected to the other end of the second resistor R2.

[0035] The positive electrode of the second battery cell CELL2, the other end of the second inductor L2, the gate of the second switch tube Q2, the other end of the first inductor L1, the gate of the first switch tube Q1, the other end of the second resistor R2 and one end of the first resistor R1 are connected to the charge and discharge control module.

[0036] When the above-mentioned BMS equalization circuit works, the electric energy can be transferred between the first battery cell CELL1 and the second battery cell CELL2 through the control of the charge and discharge control module, so that the electric quantity of the first battery cell CELL1 and the second battery cell CELL2 is kept balanced and consistent, which is specifically explained as follows:

[0037] Suppose the voltage of the first battery cell CELL1 is less than the voltage of the second battery cell CELL2, since the second battery cell CELL2 can charge the third capacitor C3 until the voltage of the third capacitor C3 is equal to the voltage of the second battery cell CELL2, when the voltage of the third capacitor C3 is equal to the voltage of the second battery cell CELL2, the charge and discharge control module controls the gate voltage of the second switch tube Q2 to be at a high level, so as to turn on the second switch tube Q2; further making the third capacitor C3 charge the first inductor L1 and the second inductor L2, when the first inductor L1 and the second inductor L2 are fully charged, the charge and discharge control module controls the gate voltage of the second switch tube Q2 to be at a low level, so as to turn off the second switch tube Q2; at the same time, the charge and discharge control module controls the gate voltage of the first switch tube Q1 to be at a high level, so as to turn on the first switch tube Q1, so that the first inductor L1 can charge the second capacitor C2, and further charge the first battery cell CELL1 through the second capacitor C2, so as to realize the transfer of the electric quantity of the second battery cell CELL2 to the first battery cell CELL1, until the voltage of the first battery cell CELL1 is equal to the voltage of the second battery cell CELL2.

[0038] Assuming that the voltage of the first battery cell CELL1 is greater than the voltage of the second battery cell CELL2, since the first battery cell CELL1 can charge the second capacitor C2 until the voltage of the second capacitor C2 is equal to the voltage of the first battery cell CELL1, when the voltage of the second capacitor C2 is equal to the voltage of the first battery cell CELL1, the charge-discharge control module controls the gate voltage of the first switch tube Q1 to be at a high level, so as to turn on the first switch tube Q1; further making the second capacitor C2 charge the first inductor L1, when the first inductor L1 is fully charged, the charge-discharge control module controls the gate voltage of the first switch tube Q1 to be at a low level, so as to turn off the first switch tube Q1; at the same time, the charge-discharge control module controls the gate voltage of the second switch tube Q2 to be at a high level, so as to turn on the second switch tube Q2, so that the first inductor L1 can charge the third capacitor C3 and the second inductor L2, and further charge the second battery cell CELL2 through the third capacitor C3, so as to realize the transfer of the electric quantity of the first battery cell CELL1 to the second battery cell CELL2, until the voltage of the second battery cell CELL2 is equal to the voltage of the first battery cell CELL1.

[0039] In the on-off process of the first switch tube Q1 and the second switch tube Q2, the instantaneous high-low peak pulse generated is absorbed by the RC filter circuit composed of the first resistor R1 and the first capacitor C1, so as to effectively reduce the influence of the inrush voltage and the inrush current on the circuit. The diode D1 plays a role of rectifying and stabilizing the waveform, so that the working waveform of the BMS equalization circuit is more stable.

[0040] Among them, the charge-discharge control module includes a fifth resistor R5 and a single-chip microcomputer (not shown); one end of the positive electrode of the second battery cell CELL2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to a charging power supply or a power load; the other end of the second inductor L2, the gate of the second switch tube Q2, the other end of the first inductor L1, the gate of the first switch tube Q1, the other end of the second resistor R2 and one end of the first resistor R1 are respectively connected to the single-chip microcomputer.

[0041] The fifth resistor R5 is used for voltage division, and the charging and discharging voltage of the BMS equalization circuit can be adjusted. Further, the other end of the fifth resistor R5 is connected to the PACK+ terminal, the other end of the second inductor L2 is connected to the VC2 pin of the single-chip microcomputer, the gate of the second switch tube Q2 is connected to the K2 pin of the single-chip microcomputer, the other end of the first inductor L1 is connected to the VC1 pin of the single-chip microcomputer, the gate of the first switch tube Q1 is connected to the K1 pin of the single-chip microcomputer, the other end of the second resistor R2 is connected to the VC0 pin of the single-chip microcomputer, and one end of the first resistor R1 is connected to the PACK- terminal. The single-chip microcomputer measures the real-time voltage of the first battery cell CELL1 and the second battery cell CELL2 through the VC0 pin, the VC1 pin and the VC2 pin, and controls the on-off of the first switch tube Q1 and the second switch tube Q2 through the K1 pin and the K2 pin. Further, the first battery cell CELL1 and the second battery cell CELL2 can be charged and discharged through the PACK+ terminal and the PACK- terminal.

[0042] As shown in Figure 2 The equalization module further includes an Nth equalization submodule, where N≥3 and N is an integer. The positive terminal of the second battery cell CELL2 is connected to one end of the fifth resistor R5 through the Nth equalization submodule, and the Nth equalization submodule includes an Nth battery cell CELLn, an Nth resistor Rn, an Nth capacitor Cn, an Nth inductor Ln and an Nth switch tube Qn.

[0043] The positive terminal of the Nth battery cell CELLn is connected to one end of the Nth resistor Rn, the other end of the Nth resistor Rn is connected to one end of the Nth capacitor Cn and one end of the Nth inductor Ln respectively, the other end of the Nth inductor Ln is connected to the source of the Nth switch tube Qn, the negative terminal of the Nth battery cell CELLn is connected to the positive terminal of the corresponding battery cell of the (N-1)th equalization submodule, the other end of the Nth capacitor is connected to one end of the corresponding inductor of the (N-1)th equalization submodule, and the drain of the Nth switch tube is connected to the source of the corresponding switch tube of the (N-1)th equalization submodule; the positive terminal of the Nth battery cell CELLn is also connected to one end of the fifth resistor R5, the other end of the Nth inductor Ln and the gate of the Nth switch tube Qn are connected to the single-chip microcomputer. Specifically, the other end of the Nth inductor Ln is connected to the VCn pin of the single-chip microcomputer, and the gate of the Nth switch tube Qn is connected to the Kn pin of the single-chip microcomputer.

[0044] It can be seen that on the basis of the first and second equalization sub-modules, the BMS equalization circuit can further be provided with a third equalization sub-module, a fourth equalization sub-module, a fifth equalization sub-module, etc. The circuit structure of the Nth equalization sub-module is completely identical to that of the second equalization sub-module. Since the single-chip microcomputer can measure the real-time voltages of the first battery cell CELL1, the second battery cell CELL2 and the Nth battery cell CELLn through the VC0 pin, the VC1 pin, the VC2 pin and the VCn pin, and can control the on-off of the first switch tube Q1, the second switch tube Q2 and the Nth switch tube Qn through the K1 pin, the K2 pin and the Kn pin, the Nth battery cell CELLn can be kept in balance with the first battery cell CELL1 and the second battery cell CELL2 in terms of electric quantity.

[0045] The models of the first inductor and the second inductor can be selected according to actual needs. Preferably, the first inductor and the second inductor are both energy storage inductors, so as to meet the need of energy transfer between the first battery cell CELL1 and the second battery cell CELL2.

[0046] Further, the types of the first switch tube Q1 and the second switch tube Q2 can be selected according to actual needs. Preferably, the first switch tube Q1 and the second switch tube Q2 are both MOS tubes. The MOS tube has the advantages of high input impedance, low noise, low power consumption and easy integration.

[0047] Further, the first switch tube Q1 and the second switch tube Q2 are both n-type MOS tubes. Compared with p-type MOS tubes, the n-type MOS tubes have faster switching speed, higher voltage resistance and larger current passing capacity.

[0048] Further, the second capacitor C2 and the third capacitor C3 are both energy storage capacitors. Compared with traditional capacitors, the energy storage capacitors have higher energy density, which makes them applicable to occasions requiring fast energy supply.

[0049] Further, the type of the Nth switch tube Qn can be selected according to actual needs. Preferably, the Nth switch tube Qn is a MOS tube.

[0050] Further, since the n-type MOS tube has faster switching speed, higher voltage resistance and larger current passing capacity than the p-type MOS tube, the Nth switch tube Qn is preferably an n-type MOS tube.

[0051] Further, since the energy storage capacitors and the energy storage inductors have advantages in energy storage, the Nth capacitor Cn is preferably an energy storage capacitor, and the Nth inductor Ln is preferably an energy storage inductor.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A BMS equalization circuit, characterized in that, It includes a surge protection module, an equalization module, and a charge / discharge control module. The surge protection module is connected to the equalization module, and the charge / discharge control module is connected to both the surge protection module and the equalization module. The surge protection module includes a first resistor, a first capacitor, and a diode; the equalization module includes a first-level equalization submodule and a second-level equalization submodule. The first-level equalization submodule includes a first battery cell, a second resistor, a third resistor, a second capacitor, a first inductor, and a first switching transistor; the second-level equalization submodule includes a second battery cell, a fourth resistor, a third capacitor, a second inductor, and a second switching transistor. One end of the first resistor and one end of the first capacitor are grounded. The other end of the first resistor is connected to one end of the second resistor and the negative terminal of the first battery cell. The other end of the second resistor is connected to one end of the second capacitor, the other end of the first capacitor, and the drain of the first switching transistor. The positive terminal of the first battery cell is connected to the negative terminal of the second battery cell and one end of the third resistor. The other end of the third resistor is connected to the other end of the second capacitor, one end of the third capacitor, and one end of the first inductor. The other end of the first inductor is connected to the source of the first switching transistor and the drain of the second switching transistor. The positive terminal of the second battery cell is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the other end of the third capacitor and one end of the second inductor. The other end of the second inductor is connected to the source of the second switching transistor. The positive terminal of the diode is grounded, and the negative terminal of the diode is connected to the other end of the second resistor. The positive terminal of the second battery cell, the other end of the second inductor, the gate of the second switch, the other end of the first inductor, the gate of the first switch, the other end of the second resistor, and one end of the first resistor are respectively connected to the charge and discharge control module.

2. The BMS equalization circuit according to claim 1, characterized in that, The charge / discharge control module includes a fifth resistor and a microcontroller. The positive terminal of the second battery cell is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to a charging power supply or an electrical load. The other end of the second inductor, the gate of the second switching transistor, the other end of the first inductor, the gate of the first switching transistor, the other end of the second resistor, and one end of the first resistor are respectively connected to the microcontroller.

3. The BMS equalization circuit according to claim 2, characterized in that, The equalization module further includes an Nth level equalization submodule, where N≥3 and N is an integer; The positive terminal of the second battery cell is connected to one end of the fifth resistor through the Nth level equalization submodule. The Nth level equalization submodule includes an Nth level battery cell, an Nth level resistor, an Nth level capacitor, an Nth level inductor, and an Nth level switching transistor. The positive terminal of the N-level cell is connected to one end of the N-level resistor, the other end of the N-level resistor is connected to one end of the N-level capacitor and one end of the N-level inductor, the other end of the N-level inductor is connected to the source of the N-level switch, the negative terminal of the N-level cell is connected to the positive terminal of the corresponding cell of the (N-1)th level equalization submodule, the other end of the N-level capacitor is connected to one end of the corresponding inductor of the (N-1)th level equalization submodule, and the drain of the N-level switch is connected to the source of the corresponding switch of the (N-1)th level equalization submodule. The positive terminal of the N-level cell is also connected to one end of the fifth resistor, and the other end of the N-level inductor and the gate of the N-level switch are respectively connected to the microcontroller.

4. The BMS equalization circuit according to claim 1, characterized in that, Both the first inductor and the second inductor are energy storage inductors.

5. The BMS equalization circuit according to claim 1, characterized in that, Both the first and second switching transistors are MOSFETs.

6. The BMS equalization circuit according to claim 5, characterized in that, Both the first and second switching transistors are n-type MOS transistors.

7. The BMS equalization circuit according to claim 1, characterized in that, Both the second capacitor and the third capacitor are energy storage capacitors.

8. The BMS equalization circuit according to claim 3, characterized in that, The N-stage switch is a MOSFET.

9. The BMS equalization circuit according to claim 3, characterized in that, The N-stage switch is an n-type MOS transistor.

10. The BMS equalization circuit according to claim 3, characterized in that, The N-stage capacitor is an energy storage capacitor, and the N-stage inductor is an energy storage inductor.

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