Multilayer printed circuit board and multilayer printed circuit board assembly
By introducing empty pin fan-out paths near signal pins in the circuit layer design of multilayer printed circuit boards, the problem that standard hole technology cannot be used in the prior art is solved, and the production cost is reduced.
Patent Information
- Application Number
- CN202423226287.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-26
AI Technical Summary
Existing technologies cannot use standard hole technology to mount BGA chips with pin pitch less than or equal to 0.5mm, resulting in high HDI technology costs and the inability to reduce production costs.
By introducing empty pin fan-out paths near signal pins in the circuit layer design of multilayer printed circuit boards, signal fan-out is achieved using pure standard via technology, avoiding the use of HDI technology.
This reduces production costs and enables the production of multilayer printed circuit boards that use standard hole technology to mount BGA chips with a pin pitch of less than or equal to 0.5 mm.
Smart Images
Figure CN223694057U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a multilayer printed circuit board (PCB) for mounting a ball grid array (BGA) chip with a pin pitch less than or equal to 0.5 mm and a multilayer printed circuit board assembly having the BGA chip mounted thereon. The BGA chip is particularly a memory, more particularly a Universal Flash Storage (UFS). BACKGROUND
[0002] A UFS is a kind of storage system which packages a Nand Flash and a flash controller protocol interface together, and it is a kind of BGA package. There are many products of printed circuit boards for mounting a UFS in the market. In these products, the standard via technology can be used in the other device areas except the device area for mounting the UFS. However, due to the too small pin pitch (usually about 0.5 mm, i.e. 0.5 mm pin pitch) of the UFS, the standard via technology cannot be used and only the HDI technology can be used. That is to say, if one or more UFS or other BGA chips (such as memories) with a pin pitch less than or equal to 0.5 mm need to be mounted on a PCB, the standard via technology cannot be used for the whole PCB and the HDI technology must be used to complete the design of the PCB.
[0003] However, the cost of the PCB using the HDI technology is much higher than that of the PCB using the pure standard via technology, for example, the cost is usually increased by 30% to 50%. Therefore, it is desirable to provide a PCB for mounting a BGA chip (particularly a memory, more particularly a UFS) with a pin pitch less than or equal to 0.5 mm using the pure standard via technology. SUMMARY
[0004] In view of the above problems, the present application aims to provide a multilayer printed circuit board (PCB) for mounting a BGA chip (particularly a memory, more particularly a UFS) with a pin pitch less than or equal to 0.5 mm and a multilayer printed circuit board assembly having the BGA chip (particularly a memory, more particularly a UFS) mounted thereon.
[0005] According to the first aspect of the utility model, provide a kind of for installing the ball grid array chip of pin pitch less than or equal to 0.5 millimeter, the multilayer printed circuit board of the ball grid array chip, the multilayer printed circuit board is by a plurality of circuit layers and substrate press together, the plurality of circuit layers include the circuit layer being contacted with the ball grid array chip, the ball grid array chip includes signal pin and empty pin, wherein, the circuit layer being contacted with the ball grid array chip has the fan-out path of the signal of at least one signal pin of the ball grid array chip mounted on the multilayer printed circuit board by the fan-out of empty pin near the at least one signal pin.
[0006] According to an embodiment of the utility model, the ball grid array chip includes dense pin array region, the dense pin array region includes at least 3 rows and at least 3 columns of pins, and the row spacing of the pin is not more than 0.5 millimeter, and the column spacing of the pin is not more than 0.5 millimeter, wherein, the at least one signal pin is the pin located in the middle of the dense pin array region, and the empty pin near the at least one signal pin is the pin located at the edge of the dense pin array region.
[0007] According to an embodiment of the utility model, the pin of the dense pin array region is arranged in a plurality of nested "mouth" character patterns.
[0008] According to an embodiment of the utility model, the at least one signal pin and another signal pin adjacent to it constitute a differential pair pin.
[0009] According to an embodiment of the utility model, the other signal pin is located at the edge of the dense pin array region.
[0010] According to an embodiment of the utility model, the empty pin near the at least one signal pin is the empty pin closest to the at least one signal pin.
[0011] According to an embodiment of the utility model, the multilayer printed circuit board does not include blind via.
[0012] According to the second aspect of the utility model, a multilayer printed circuit board assembly is provided, wherein the multilayer printed circuit board assembly includes the multilayer printed circuit board according to any one of the preceding embodiments and at least one ball grid array chip mounted on the multilayer printed circuit board.
[0013] According to an embodiment of the utility model, the ball grid array chip is a universal flash memory.
[0014] According to an embodiment of the utility model, the memory is a universal flash memory.
[0015] Since the circuit layer of the multi-layer printed circuit board of the present utility model that contacts the ball grid array chip (especially a memory, more particularly a UFS) has a fan-out path for fanning out the signal of at least one signal pin of the ball grid array chip mounted on the multi-layer printed circuit board by means of the empty pins near the at least one signal pin, the multi-layer printed circuit board of the present utility model can use a pure standard hole technology to mount a ball grid array chip with a pin pitch less than or equal to 0.5 mm, thereby reducing the cost of producing a multi-layer printed circuit board for mounting a ball grid array chip with a pin pitch less than or equal to 0.5 mm. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Hereinafter, embodiments herein will be described in more detail with reference to the drawings, wherein:
[0017] Figure 1 A schematic diagram of the pins of a ball grid array chip according to an embodiment of the present utility model is schematically shown.
[0018] Figure 2 A schematic diagram of the path for fanning out signals by the circuit layer of a multi-layer printed circuit board according to an embodiment of the present utility model by means of the empty pins (empty pins) of the UFS is schematically shown.
[0019] According to the following detailed description in conjunction with the drawings, other objects and features of the embodiments herein will become apparent. However, it should be understood that the drawings are only schematic representations and are only for illustrative purposes and not for limiting the scope of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0020] Figure 1 A schematic diagram of the pins of a ball grid array chip according to an embodiment of the present utility model is schematically shown. The ball grid array chip in this embodiment is a UFS10, Figure 1 where the paired differential signal pins that need to fan out signals are marked by ellipses. It can be understood that the signal pins that need to fan out signals can be differential signals or non-differential signals, and the signal pins can be paired or non-paired.
[0021] By Figure 1 It can be seen that the UFS10 includes a dense pin array region, and the dense pin array region contains pins in rows A, B, C, M, N, P and columns 1, 2, 3, 12, 13, 14. The row pitch and column pitch of the pins do not exceed 0.5 mm, and the pins in the dense pin array region are arranged in a multi-loop "mouth" - shaped pattern. It can be understood that the pins in the dense pin array region of the ball grid array chip of the present utility model can be arranged in other patterns, and can include any number of rows of pins more than 3 rows and any number of columns of pins more than 3 columns.
[0022] In Figure 1 the example, the pins of the UFS 10 include four circles of "mouth" shaped pattern arranged pins, in which the outermost three circles of pins form a dense pin array region with substantially uniform spacing. For the purpose of illustration, the arrangement of the pins in the lateral direction is marked with the serial numbers of Arabic numerals 1, 2, 3, …, and the arrangement of the pins in the vertical direction is marked with the serial numbers of English letters A, B, C, …. Figure 1 In the example, the number of pins in each row and each column of the outermost three circles of pins arranged in the "mouth" shaped pattern is 14, i.e. the maximum column number is the 14th column and the maximum row number is the Pth row.
[0023] For the purpose of illustration, each pin is represented by P xy , in which x and y represent the row and column of the pin respectively. For example, in Figure 1 , the pin in the 1st column of the Cth row can be represented by P c1 , and in Figure 1 , the pin in the 1st column of the Eth row can be represented by P c1 , which is a null pin, i.e. NC. Similarly, the pins in the 1st column of the Lth row, the 1st column of the Nth row can be represented by P E1 , P L1 , P N1 , respectively, which are also null pins.
[0024] Figure 1 In the example, the paired differential signal pins that need to be fanned out are marked by the ellipses. For the purpose of illustration, the paired differential signal pins that need to be fanned out are represented by P xy+ and P xy- , in which x and y represent the row and column of the pin respectively, and the symbols "+" and "-" represent the positive and negative signals of the differential signal pair respectively. For example, the paired differential signal pins that need to be fanned out in the Dth row are P D1+ and P D2- , in which the pin P D1+ is the differential signal RXDP1 and the pin P D2- is the differential signal RXDN1. Similarly, the other three groups of paired differential signal pins that need to be fanned out are P F1+ and P F2- (differential signals RXDP0 and RXDN0), P K1+ and P K2- (differential signals TXDN0 and TXDP0), P M1+ and P M2- (differential signals TXDN1 and TXDP1).
[0025] This embodiment shows four pairs of differential signal pairs that need to fan out signals, it is easy to understand that there can be fewer or more differential signal pairs that need to fan out signals for different UFS. For example, 1 pair, 2 pairs, 3 pairs, 5 pairs, 6 pairs or more pairs of differential signal pairs that need to fan out signals.
[0026] Figure 2 The path diagram of the substrate of the printed circuit board borrowing the empty pin of the UFS as a path to fan out signals according to one embodiment of the utility model is schematically shown.
[0027] As shown in Figure 2 , one of the paired differential signal pins P D1+ in the D row can directly fan out signals at the outermost circle of the multi-circle "mouth" shape pattern, that is, at the edge of the dense pin array region. The other pin P D2- in the paired differential signal pin in the D row can directly fan out signals at the second outermost circle of the multi-circle "mouth" shape pattern, that is, in the middle of the dense pin array region. Since the spacing between the other pin P D2- and the pin P D1+ is too small, it cannot directly fan out signals. For this purpose, the pin P D2- borrows the empty pin P c1 closest to it in the first column to fan out signals.
[0028] Similarly, the differential signal pins P F1+ , P K2- , and P M2- directly fan out signals, while the differential signal pins P F2- , P K2- , and P M2- borrow the empty pins P E1 , P L1 , and P N1 respectively to fan out signals.
[0029] Since the circuit layer of the multi-layer printed circuit board of the utility model in contact with the ball grid array chip (especially the memory, more particularly the UFS) has a fan-out path that fans out the signals of at least one signal pin of the ball grid array chip mounted on the multi-layer printed circuit board by means of the empty pin near the at least one signal pin, the multi-layer printed circuit board of the utility model can use pure standard hole technology to install the ball grid array chip with a pin pitch less than or equal to 0.5mm, thereby reducing the cost of producing a multi-layer printed circuit board for installing a ball grid array chip with a pin pitch less than or equal to 0.5mm.
[0030] Embodiments of the present application exemplarily illustrate a multilayer printed circuit board (PCB) for mounting a UFS with a pin pitch less than or equal to 0.5 mm. It is readily understood by those skilled in the art that the present application can be used to mount any BGA chip or memory with a pin pitch less than or equal to 0.5 mm.
[0031] Although features of the embodiments of the present application have been described, it is understood that those skilled in the art can make various omissions, substitutions and changes to the structure of the present application, and adjustments to the structure of the present application are possible on the premise that the functions of the present application can be realized.
Claims
1. A multilayer printed circuit board for mounting a ball grid array chip having a pin pitch of less than or equal to 0.5 mm, the multilayer printed circuit board being formed by laminating a plurality of circuit layers and a substrate, the plurality of circuit layers including a circuit layer in contact with the ball grid array chip, the ball grid array chip including signal pins and void pins, characterized in that, The circuit layer in contact with the ball grid array chip has a fanout path for a signal of at least one signal pin of a ball grid array chip mounted on the multilayer printed circuit board by means of empty pins adjacent to the at least one signal pin.
2. The multilayer printed circuit board of claim 1, wherein, The ball grid array chip includes a dense pin array area containing at least 3 rows and at least 3 columns of pins with a row pitch of the pins not more than 0.5 mm and a column pitch of the pins not more than 0.5 mm, wherein the at least one signal pin is a pin located in a middle of the dense pin array area and the empty pins adjacent to the at least one signal pin are pins located at edges of the dense pin array area.
3. The multilayer printed circuit board of claim 2, wherein, The pins of the dense pin array area are arranged in a multi-turn nested "mouth" shape pattern.
4. The multilayer printed circuit board of claim 2, wherein, The at least one signal pin forms a differential pair pin with another signal pin adjacent to the at least one signal pin.
5. The multilayer printed circuit board of claim 4, wherein, The another signal pin is located at an edge of the dense pin array area.
6. The multilayer printed circuit board according to any one of claims 1 to 5, characterized in that, The empty pins adjacent to the at least one signal pin are the empty pins closest to the at least one signal pin.
7. The multilayer printed circuit board according to any one of claims 1 to 5, characterized in that, The multilayer printed circuit board does not include blind vias.
8. A multilayer printed circuit board assembly, characterized by The multilayer printed circuit board assembly includes the multilayer printed circuit board according to any one of claims 1-7 and at least one ball grid array chip mounted on the multilayer printed circuit board.
9. The multilayer printed circuit board assembly of claim 8, wherein, The ball grid array chip is a memory.
10. The multilayer printed circuit board assembly of claim 9, wherein, The memory is a universal flash memory. The memory is a universal flash memory.