Level conversion circuit
By combining a voltage detection unit and an operational amplifier unit, the input terminal of the inverting unit is controlled, enabling level conversion at low effective high level, thus solving the problem of existing level conversion circuits failing when identifying low potentials.
Patent Information
- Application Number
- CN202520064340.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2035-01-13
AI Technical Summary
Existing level conversion circuits cannot perform level conversion properly when effectively recognizing a high potential decreasing to a low potential (e.g., around 1V).
The system employs a combination of a voltage detection unit, an operational amplifier unit, a pull-up PMOS transistor, and an inverting unit. By comparing the external voltage with the threshold voltage, the input of the inverting unit is controlled to achieve level switching.
The system can still perform level conversion normally when the effective high-level signal is as low as about 1V, thus solving the problem of level conversion failure.
Smart Images
Figure CN223729740U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of level conversion, specifically relates to a level conversion circuit. BACKGROUND
[0002] At present, communication modules are widely applied to various electronic equipment, and many communication modules and host control ends communicate and exchange data through UART data bus, and the communication module and the host control module exchange data mainly through switching of level signals.
[0003] When the host control module sends data to the communication module, high level signals and low level signals are sent to the signal receiving port of the communication module in sequence through the signal sending interface of the host control module, and when the communication module sends data to the host control module, high level signals and low level signals are sent to the signal receiving port of the host control module in sequence through the signal sending interface of the communication module; in order to ensure that the chip can work normally, a level switching circuit is usually used to switch the working voltage of different modules.
[0004] The existing level conversion circuit is as shown in the figure, comprising NMOS tube N1, NMOS tube N2, NMOS tube N3, PMOS tube P1, PMOS tube P2 and PMOS tube P3. Figure 1 Among them, NMOS tube N3 and PMOS tube P3 constitute an inverter, Vin is an input signal, high level is VDD, and low level GND is 0; when Vin is high, NMOS tube N1 is turned on, NMOS tube N2 is cut off, OUT is lowered, the gate voltage of PMOS tube P2 is lowered, when OUT is lowered to the standby switching high voltage VDD-VTH, PMOS tube P2 is turned on, the OUT voltage is the standby switching high voltage VDD, the gate voltage of PMOS tube P1 is the standby switching high voltage VDD, PMOS tube P1 is cut off, and the gate-source voltage of PMOS tube P2 is the standby switching high voltage VDD; similarly, when Vin is low, the gate-source voltage of PMOS tube P1 is the standby switching high voltage VDD;
[0005] However, with the development of integrated circuits and the demand for low-power products, the effective recognition of the high potential of the input end Vin is getting lower and lower, for example, vin_H is about 1V, when VDD is too high compared with Vin, at this time, NMOS tube N3 and PMOS tube P3 constitute an inverter, when vin_H is input, it is easy to cause PMOS tube P3 and NMOS tube N3 to be opened, thereby causing the inverter not to invert, so that the level conversion circuit loses the function. UTILITY MODEL CONTENTS
[0006] In view of the deficiencies in the background art, the utility model provides a level conversion circuit, and the technical problem to be solved is that the prior art cannot normally perform level conversion when effectively identifying that a high potential becomes low, for example, at about 1V.
[0007] To solve the above technical problems, the utility model provides the following technical scheme: a level conversion circuit, comprising a voltage detection unit, an operational amplifier unit, a pull-up PMOS tube P4 and an inverting unit;
[0008] The source of the pull-up PMOS tube P4 is used for accessing a power supply voltage VDD, and the drain of the pull-up PMOS tube P4 is electrically connected with the input end of the inverting unit;
[0009] The voltage detection unit is used for detecting an input external voltage, providing a grounding path for the gate of the pull-up PMOS tube P4 when the external voltage is less than a threshold voltage, and providing a reference voltage Vbias for one input end of the operational amplifier unit when the external voltage is greater than the threshold voltage, while the operational amplifier unit compares the reference voltage Vbias and the external voltage and provides a grounding path for the input end of the inverting unit based on the comparison result;
[0010] The inverting unit is used for inverting an input signal.
[0011] In certain embodiments, the operational amplifier unit comprises a PMOS tube P1, a resistor R6, a PMOS tube P2, a PMOS tube P3, an NMOS tube N4, an NMOS tube N5 and an NMOS tube N6.
[0012] The source of the PMOS tube P1 is used for accessing the power supply voltage VDD, the gate of the PMOS tube P1 is electrically connected with the voltage detection unit, the drain of the PMOS tube P1 is electrically connected with the source of the PMOS tube P2 and the source of the PMOS tube P3 through the resistor R6, the gates of the PMOS tube P2 and the PMOS tube P3 are two input ends of the operational amplifier unit, the drain of the PMOS tube P2 is electrically connected with the drain of the NMOS tube N4, the gate of the NMOS tube N4, the gate of the NMOS tube N5 and the gate of the NMOS tube N6, the drain of the PMOS tube P3 is electrically connected with the drain of the NMOS tube N5, the source of the NMOS tube N4, the source of the NMOS tube N5 and the source of the NMOS tube N6 are grounded, and the drain of the NMOS tube N6 is electrically connected with the input end of the inverting unit.
[0013] In certain embodiments, the voltage detection unit comprises a resistor R1, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a voltage dividing unit.
[0014] One end of the resistor R1 is used for inputting the external voltage, and the other end of the resistor R1 is electrically connected with the drain of the NMOS tube N1, the gate of the pull-up PMOS tube P4, the gate of the NMOS tube N2 and the gate of the PMOS tube P3 respectively; the gate and the source of the NMOS tube N1 and the source of the NMOS tube N2 are grounded.
[0015] The input end of the voltage dividing unit is used for accessing the power supply voltage VDD, the output end of the voltage dividing unit is electrically connected with the drain of the NMOS tube N2, the source of the NMOS tube N3 and the gate of the PMOS tube P1 respectively, and one voltage dividing node of the voltage dividing unit is electrically connected with the gate of the NMOS tube N3, the drain of the NMOS tube N3 and the gate of the PMOS tube P2 respectively.
[0016] In some embodiments, the voltage dividing unit comprises N series-connected voltage dividing resistors, and N is a positive integer greater than 1.
[0017] In some embodiments, N is 2.
[0018] In some embodiments, N is 3.
[0019] In some embodiments, N is 4, and the four voltage dividing resistors are resistor R2, resistor R3, resistor R4 and resistor R5, one end of the resistor R2 is used for inputting the power supply voltage VDD, and the other end of the resistor R2 is connected with the resistor R3, the resistor R4 and the resistor R5 in series; one end of the resistor R3 and the resistor R4 is electrically connected with the gate of the NMOS tube N3, the drain of the NMOS tube N3 and the gate of the PMOS tube P2 respectively.
[0020] In some embodiments, the inverting unit comprises M inverters, and M is an odd number; when M is greater than 1, the inverters are connected in series.
[0021] In some embodiments, M is 1.
[0022] In some embodiments, M is 3.
[0023] The advantages of this invention compared to existing technologies are as follows: This invention compares the external voltage with the threshold voltage by setting a voltage detection unit. When the external voltage is less than the threshold voltage, the pull-up PMOS transistor P4 is turned on, making the input of the inverting unit a high-level power supply voltage VDD, and the output of the inverting unit a low-level signal. When the external voltage is greater than the threshold voltage, the pull-up PMOS transistor P4 is turned off, and the operational amplifier unit pulls the input of the inverting unit to ground based on the comparison result of the reference voltage Vbias and the external voltage, making the input of the inverting unit grounded to a low-level state, and the output of the inverting unit outputs a high-level signal, thereby realizing level conversion. The effective high-level signal is set by the threshold voltage. Therefore, by setting different threshold voltages, the effective high-level signal can still perform level conversion normally even when it is around 1V. Attached Figure Description
[0024] Figure 1 The circuit diagram is for an existing level conversion circuit.
[0025] Figure 2 This is a circuit diagram of the present invention in the embodiments;
[0026] Figure 3 for Figure 1 The circuit shown is a simulation diagram in actual use.
[0027] Figure 4 This is a simulation diagram of the present invention at high temperatures;
[0028] Figure 5 This is a simulation diagram of the present invention at low temperatures. Detailed Implementation
[0029] The following specific embodiments illustrate the implementation of a level conversion circuit disclosed in this utility model. Those skilled in the art can understand the advantages and effects of this utility model from the content disclosed in this specification. This utility model can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this utility model. Furthermore, the accompanying drawings of this utility model are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this utility model in detail, but the disclosed content is not intended to limit the scope of protection of this utility model.
[0030] It should be appreciated that, although the terms first, second, third, etc. can be used herein to describe various components or features, these components or features should not be limited by these terms. These terms are generally used only to distinguish one component or feature from another component or feature. Additionally, the term "and / or" as used herein should be interpreted in the manner already set forth above for the term "comprises or comprises."
[0031] As shown in the embodiment, a level conversion circuit comprises a voltage detection unit 1, an operational amplifier unit 2, a pull-up PMOS tube P4 and an inverting unit 3. Figure 2
[0032] The connection relationship of the voltage detection unit 1, the operational amplifier unit 2, the pull-up PMOS tube P4 and the inverting unit 3 is as follows:
[0033] The source of the pull-up PMOS tube P4 is used to access the power supply voltage VDD, and the drain of the pull-up PMOS tube P4 is electrically connected with the input end of the inverting unit 3.
[0034] The voltage detection unit 1 is used to detect the input external voltage VC, and when the external voltage VC is less than the threshold voltage, a ground path is provided for the gate of the pull-up PMOS tube P4, and when the external voltage is greater than the threshold voltage, a reference voltage Vbias is provided for one input end of the operational amplifier unit 2, and the operational amplifier unit 2 compares the reference voltage Vbias and the external voltage VC, and based on the comparison result, a ground path is provided for the input end of the inverting unit 3.
[0035] The inverting unit 3 is used to invert the input signal.
[0036] In actual use, the external voltage VC is compared with the threshold voltage by setting the voltage detection unit 1, when the external voltage VC is less than the threshold voltage, the pull-up PMOS tube P4 is turned on, the inverting unit 3 inputs the high level power supply voltage VDD, and the inverting unit 3 outputs the low level signal.
[0037] When the external voltage VC is greater than the threshold voltage, the pull-up PMOS tube P4 is turned off, the operational amplifier unit 2 makes the input end of the inverting unit 3 pull down to ground based on the comparison result of the reference voltage Vbias and the external voltage VC, the input end of the inverting unit 3 is grounded to be in a low level state, and the output end of the inverting unit 3 outputs a high level signal, so as to realize level conversion, and the effective high level signal is set by the threshold voltage, so that by setting different threshold voltages, the level conversion can still be normally performed when the effective high level signal is about 1V.
[0038] Specifically, in the embodiment, as shown in the figure, Figure 2 As shown, the operational amplification unit 2 includes a PMOS tube P1, a resistor R6, a PMOS tube P2, a PMOS tube P3, an NMOS tube N4, an NMOS tube N5 and an NMOS tube N6;
[0039] The source of the PMOS tube P1 is used to access the power supply voltage VDD, the gate of the PMOS tube P1 is connected with the voltage detection unit, the drain of the PMOS tube P1 is connected with the source of the PMOS tube P2 and the source of the PMOS tube P3 through the resistor R6, the gate of the PMOS tube P2 and the gate of the PMOS tube P3 are two input terminals of the operational amplification unit; the drain of the PMOS tube P2 is connected with the drain of the NMOS tube N4, the gate of the NMOS tube N4, the gate of the NMOS tube N5 and the gate of the NMOS tube N6; the drain of the PMOS tube P3 is connected with the drain of the NMOS tube N5; the source of the NMOS tube N4, the source of the NMOS tube N5 and the source of the NMOS tube N6 are all grounded, and the drain of the NMOS tube N6 is connected with the input terminal of the inverting unit 3.
[0040] More specifically, in the embodiment, as shown in the figure, Figure 2 As shown, the voltage detection unit 1 includes a resistor R1, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a voltage dividing unit 10.
[0041] One end of the resistor R1 is used to input an external voltage, the other end of the resistor R1 is connected with the drain of the NMOS tube N1, the gate of the pull-up PMOS tube P4, the gate of the NMOS tube N2 and the gate of the PMOS tube P3; the gate and the source of the NMOS tube N1 and the source of the NMOS tube N2 are all grounded.
[0042] The input terminal of the voltage dividing unit 10 is used to access the power supply voltage VDD, the output terminal of the voltage dividing unit 10 is connected with the drain of the NMOS tube N2, the source of the NMOS tube N3 and the gate of the PMOS tube P1, one voltage dividing node of the voltage dividing unit 10 is connected with the gate of the NMOS tube N3, the drain of the NMOS tube N3 and the gate of the PMOS tube P2.
[0043] In the embodiment, the voltage dividing unit 10 includes four series voltage dividing resistors, the four voltage dividing resistors are a resistor R2, a resistor R3, a resistor R4 and a resistor R5, one end of the resistor R2 is used to input the power supply voltage VDD, the other end of the resistor R2 is connected with the resistor R3, the resistor R4 and the resistor R5 in series; one end of the resistor R3 connected with the resistor R4 is connected with the gate of the NMOS tube N3, the drain of the NMOS tube N3 and the gate of the PMOS tube P2.
[0044] In some embodiments, the voltage dividing unit 10 can also include two, three or five voltage dividing resistors, which are set according to actual needs.
[0045] As Figure 2 described, in the embodiment, the inverting unit 3 includes three inverters, the three inverters are inverter INV1, inverter INV2 and inverter INV3 respectively, and the three inverters are connected in series.
[0046] In certain embodiments, the inverting unit 3 can include one inverter or five inverters, which is set according to actual needs.
[0047] The circuit shown in Figure 2 is analyzed, and the working process is as follows:
[0048] When the external voltage VC input is less than the opening voltage of the NMOS tube N2, the PMOS tube P1 is closed, the PMOS tube P4 is turned on, and the NMOS tube N6 is closed, at this time, the signal dout output after being shaped by the three inverters of the inverting unit 3 is in a low potential state;
[0049] When the external voltage VC input is higher than the opening voltage of the NMOS tube N2, the drain voltage of the NMOS tube N1 approaches the low potential with the opening of the NMOS tube N1, so that the PMOS tube P1 is opened, the NMOS tube N3 is turned on, the reference voltage Vbias can be obtained by dividing the power supply voltage VDD through the voltage dividing unit 10, and the reference voltage Vbias and the external voltage VC are compared by the operational amplifier unit 2, when the external voltage VC is higher than the reference voltage Vbias, the gate end of the NMOS tube N6 outputs a high potential, so that the NMOS tube N6 is turned on, and the signal dout output by the inverting unit 3 is in a high potential state; when the external voltage VC is too high and greater than the power supply voltage VDD, at this time, the PMOS tube P4 is cut off, and the signal dout output by the inverting unit 3 is in a high potential state; in turn, the level conversion is realized, and the threshold voltage of the voltage detection unit 1 is the opening voltage of the NMOS tube N2.
[0050] The circuit shown in Figure 1 and the circuit of the utility model shown in Figure 2 are simulated, wherein Figure 1 the simulation diagram of the circuit shown in Figure 3 can be obtained from Figure 3 , the simulation diagram of the circuit shown in Figure 1 shows that the level conversion fails when the effective high level is 1V; the simulation diagram of the utility model at high temperature is shown in Figure 4 , from Figure 4 it can be obtained that the utility model can normally perform level conversion when the effective high level is 1V; the simulation diagram of the utility model at low temperature is shown in Figure 5 , from Figure 5 it can be obtained that when the external voltage VC is 500mv, the signal dout output by the inverting unit 3 is in a low potential state, which meets the requirements.
[0051] According to the above disclosure, relevant personnel can make various changes and modifications without deviating from the technical concept of the present application. The technical scope of the present application is not limited to the content of the specification, and must be determined by the scope of the claims.
Claims
1. A level shifting circuit, characterized by, The voltage detection unit, the operational amplifier unit, the pull-up PMOS tube P4 and the inverting unit are included. The source of the pull-up PMOS tube P4 is used for accessing the power supply voltage VDD, and the drain of the pull-up PMOS tube P4 is electrically connected with the input end of the inverting unit. The voltage detection unit is used for detecting the input external voltage, providing a grounding path for the gate of the pull-up PMOS tube P4 when the external voltage is less than the threshold voltage, providing a reference voltage Vbias for one input end of the operational amplifier unit when the external voltage is greater than the threshold voltage, and comparing the reference voltage Vbias and the external voltage by the operational amplifier unit, and providing a grounding path for the input end of the inverting unit based on the comparison result. The inverting unit is used for inverting the input signal.
2. A level shifting circuit according to claim 1, characterized in that The operational amplifier unit includes a PMOS tube P1, a resistor R6, a PMOS tube P2, a PMOS tube P3, an NMOS tube N4, an NMOS tube N5 and an NMOS tube N6. The source of the PMOS tube P1 is used for accessing the power supply voltage VDD, the gate of the PMOS tube P1 is electrically connected with the voltage detection unit, the drain of the PMOS tube P1 is electrically connected with the source of the PMOS tube P2 and the source of the PMOS tube P3 through the resistor R6, the gates of the PMOS tube P2 and the PMOS tube P3 are two input ends of the operational amplifier unit, the drain of the PMOS tube P2 is electrically connected with the drain of the NMOS tube N4, the gate of the NMOS tube N4, the gate of the NMOS tube N5 and the gate of the NMOS tube N6, the drain of the PMOS tube P3 is electrically connected with the drain of the NMOS tube N5, the source of the NMOS tube N4, the source of the NMOS tube N5 and the source of the NMOS tube N6 are grounded, and the drain of the NMOS tube N6 is electrically connected with the input end of the inverting unit.
3. A level shifting circuit according to claim 2, characterised in that, The voltage detection unit includes a resistor R1, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a voltage dividing unit. One end of the resistor R1 is used for inputting the external voltage, the other end of the resistor R1 is electrically connected with the drain of the NMOS tube N1, the gate of the pull-up PMOS tube P4, the gate of the NMOS tube N2 and the gate of the PMOS tube P3, the gate and the source of the NMOS tube N1 and the source of the NMOS tube N2 are grounded. The input end of the voltage dividing unit is used for accessing the power supply voltage VDD, the output end of the voltage dividing unit is electrically connected with the drain of the NMOS tube N2, the source of the NMOS tube N3 and the gate of the PMOS tube P1, and one voltage dividing node of the voltage dividing unit is electrically connected with the gate of the NMOS tube N3, the drain of the NMOS tube N3 and the gate of the PMOS tube P2.
4. A level shifting circuit as claimed in claim 3, characterized in that The voltage dividing unit includes N series voltage dividing resistors, and N is a positive integer greater than 1.
5. A level shifting circuit as claimed in claim 4, characterized in that N is 2.
6. A level shifting circuit as claimed in claim 4, characterized in that N is 3.
7. A level shifting circuit as claimed in claim 4, characterized in that N is 4, four partial pressure resistors are resistor R2, resistor R3, resistor R4 and resistor R5, one end of resistor R2 is used for inputting the power supply voltage VDD, the other end of resistor R2 is connected with resistor R3, resistor R4 and resistor R5 in series; one end of the electric connection between resistor R3 and resistor R4 is electrically connected with the gate of NMOS tube N3, the drain of NMOS tube N3 and the gate of PMOS tube P2 respectively.
8. A level shifting circuit as claimed in claim 1, characterized in that The inverting unit comprises M inverters, M is an odd number, and the inverters are connected in series when M is greater than 1.
9. A level shifting circuit as claimed in claim 8, characterized in that M is 1.
10. A level shifting circuit as claimed in claim 8, characterized in that M is 3.