Semiconductor photonic device

Abstract

The embodiment of the utility model provides a semiconductor photonic device which comprises an optical modulator structure and a modulator heater structure in one or more dielectric layers of the semiconductor photonic device. Isolation trenches are included around the modulator heater structure to reduce the likelihood that thermal stress may cause damage to the dielectric layer. The isolation trench may include an air gap through the dielectric layer, and the air gap surrounds the modulator heater structure in a top view of the semiconductor photonic device. The isolation trench reduces heat absorbed in the dielectric layer as the isolation trench thermally isolates the modulator heater structure from the dielectric layer. This reduces the likelihood of cracks, delamination, and / or other types of damage to the dielectric layer, which may otherwise be caused by thermal stress of the dielectric layer.

Description

Technical Field

[0001] Embodiments of this novel invention relate to a semiconductor photonic device. Background Technology

[0002] Semiconductor components can be configured to use optical signals for high-speed and secure data transmission between integrated circuits and / or semiconductor chips. Optical signals can be transmitted through waveguides within the semiconductor device. Waveguides confine the optical signal, reducing optical loss and improving propagation efficiency. By modulating the light into optical pulses using an optical modulator, data can be encoded into optical signals. These optical pulses are then transmitted to the waveguides to propagate to other areas of the semiconductor device. Utility Model Content

[0003] Some embodiments of the present invention provide a semiconductor photonic device, characterized in that it comprises: a substrate; one or more first dielectric layers on the substrate; an etch stop layer above the one or more first dielectric layers; a plurality of second dielectric layers above the etch stop layer; an optical modulator structure in the one or more first dielectric layers; a modulator heater structure in one or more of the plurality of second dielectric layers, wherein the modulator heater structure is located above the optical modulator structure; and an isolation trench through the plurality of second dielectric layers, wherein the isolation trench terminates at the etch stop layer, and wherein, in a top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure.

[0004] Furthermore, other embodiments of this invention provide a semiconductor photonic device, characterized in that it comprises: a substrate; one or more first dielectric layers on the substrate; an etch stop layer on the one or more first dielectric layers; a plurality of second dielectric layers on the etch stop layer; an optical modulator structure in the one or more first dielectric layers; a modulator heater structure in one or more of the plurality of second dielectric layers, wherein the modulator heater structure is located above the optical modulator structure; and an isolation region of the plurality of second dielectric layers, wherein the isolation region of the plurality of second dielectric layers is located above the optical modulator structure, wherein the modulator heater structure is contained within the isolation region of the plurality of second dielectric layers, wherein the isolation region of the plurality of second dielectric layers is isolated from other regions of the plurality of second dielectric layers through isolation trenches, and wherein the isolation region in the plurality of second dielectric layers has a ring-shaped top view in a top view of the semiconductor photonic device. Attached Figure Description

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a diagram of an exemplary environment in which the systems and / or methods described in this paper can be implemented.

[0007] Figures 2A-2C This is a diagram of an example semiconductor component described in this article.

[0008] Figures 3A-3S These are diagrams illustrating exemplary embodiments of the semiconductor components (or portions thereof) described herein.

[0009] Figure 4 This is a diagram of an exemplary component of the device described in this article.

[0010] Figure 5 This is a flowchart of an exemplary fabrication process related to the formation of the semiconductor photonic device described in this article. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second features. The first and second features are arranged such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0013] Photonic integrated circuit devices in semiconductor photonics can include waveguide structures and optical modulator structures. The waveguide structure and optical modulator structure can be included within one or more dielectric layers of the semiconductor photonic device. The resonant wavelength of the optical modulator structure may be sensitive to variations in process technology and operating temperature. To stabilize the resonant wavelength of the optical modulator structure, a modulator heater structure can be located near the optical modulator structure to provide heat. The heat provided by the modulator heater structure allows the operating temperature of the optical modulator structure to be maintained at a consistent operating temperature throughout the operation of the semiconductor photonic device.

[0014] While some heat generated by the modulator heater structure is transferred to the optical modulator structure, the dielectric layer surrounding the modulator heater structure also absorbs this heat. This absorbed heat creates thermal stress on the dielectric layer. In particular, the absorbed heat can cause localized areas within the dielectric layer to have different temperatures, and these temperature-differential areas may lead to dielectric layer cracking, delamination, and / or other types of damage due to the thermal stress induced by these temperature variations. Additionally and / or alternatively, the absorbed heat causes repeated rapid temperature cycling within the dielectric layer, which can degrade the structural integrity of the dielectric layer over time. These localized areas of different temperatures and / or repeated thermal cycling within the dielectric layer can reduce the reliability of semiconductor photonic devices, potentially shorten their operational lifespan, and / or cause them to fail.

[0015] In some implementations described herein, the semiconductor photonic device includes an optical modulator structure and a modulator heater structure within one or more dielectric layers of the semiconductor photonic device. An isolation trench surrounds the modulator heater structure to reduce the possibility of thermal stress causing damage to the dielectric layer. The isolation trench may include an air gap through the dielectric layer, and in a top view of the semiconductor photonic device, the air gap surrounds the modulator heater structure. The isolation trench is sealed at its top by the dielectric layer to prevent contaminants from entering the isolation trench.

[0016] The isolation trench reduces heat absorption in the dielectric layer because it thermally isolates the modulator heater structure from the dielectric layer. Specifically, the isolation trench prevents heat transfer from the modulator heater structure to the surrounding dielectric layer. This reduces the likelihood of cracking, delamination, and / or other types of damage to the dielectric layer, which could otherwise be caused by thermal stress on the dielectric layer.

[0017] The isolation trench has a circular shape in the top view of the semiconductor photonic device, which further reduces the possibility of dielectric layer cracking, delamination and / or other types of damage, because the circular shape of the isolation trench prevents (or reduces) the possibility of local stress accumulating at any particular location around the isolation trench.

[0018] Figure 1 This is a diagram of an exemplary environment 100 in which the systems and / or methods described in this paper can be implemented. For example... Figure 1 As shown, environment 100 may include a plurality of semiconductor processing tools 102-114 and a wafer / die transport tool 116. The plurality of semiconductor processing tools 102-114 may include deposition tools 102, exposure tools 104, developing tools 106, etching tools 108, planarization tools 110, electroplating tools 112, ion implantation tools 114, and / or another type of semiconductor processing tool. Among other examples, the tools included in exemplary environment 100 may be located in semiconductor cleanrooms, semiconductor fabs, semiconductor processing facilities, and / or manufacturing facilities.

[0019] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, exemplary environment 100 includes various types of deposition tools 102.

[0020] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., deep UV, extreme UV, and / or similar), an X-ray source, an electron beam source, and / or similar. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor component layer patterns for forming one or more semiconductor components, patterns for forming one or more semiconductor component structures, patterns for etching various portions of the semiconductor components, etc. In some implementations, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0021] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve either exposed or unexposed portions of the photoresist layer.

[0022] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, etc. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.

[0023] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or electroplated material. Planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of a semiconductor assembly. Planarization tool 110 may utilize abrasives and corrosive chemical slurries combined with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor assembly). The polishing pad and semiconductor assembly can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and smooth any irregularities in the semiconductor assembly, thus planarizing or planarizing the semiconductor assembly.

[0024] Electroplating tool 112 is a semiconductor processing tool capable of electroplating substrates (e.g., wafers, semiconductor components, etc.) or portions thereof with one or more metals. For example, electroplating tool 112 may include copper plating apparatus, aluminum plating apparatus, nickel plating apparatus, tin plating apparatus, compound material or alloy plating apparatus (e.g., tin-silver, tin-lead, etc.), and / or plating apparatus for one or more other types of conductive materials, metals, and / or similar materials.

[0025] Ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. Ion implantation tool 114 can generate ions from a source material, such as a gas or solid, within an arc chamber. The source material can be supplied to the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions from the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate, such that the ions are implanted below the surface of the substrate.

[0026] The wafer / die transport tool 116 may be included in a clustering tool or another type of tool comprising multiple processing chambers, and may be configured to transport substrates and / or semiconductor assemblies between multiple processing chambers. This includes transporting substrates and / or semiconductor assemblies between processing chambers and buffers, between processing chambers and interface tools such as equipment front-end modules (EFEMs), and / or between processing chambers. Among other examples, chambers and transport carriers (e.g., front-opening unified pods, FOUPs) may be included. In some embodiments, the wafer / die transport tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include pre-cleaning processing chambers (e.g., for cleaning or removing oxides, oxidation, and / or deposits). Other types of contaminants or byproducts from the substrate and / or semiconductor components, as well as various types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0027] In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may be used to perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may be used to form an optical modulator structure in a semiconductor layer above a first dielectric layer of a semiconductor photonic device; may be used to form a second dielectric layer surrounding the optical modulator structure above the first dielectric layer; may be used to form an etch stop layer above the second dielectric layer and above the optical modulator structure; may be used to form a first portion of a third dielectric layer on the etch stop layer; may be used to form a modulator heater structure in the first portion of the third dielectric layer above the optical modulator structure; may be used to form a second portion of the third dielectric layer and multiple dielectric layers above the first portion of the third dielectric layer and above the modulator heater structure; and / or may be used to form an isolation trench that passes through multiple dielectric layers, through the third dielectric layer and to the etch stop layer, wherein, in a top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure, and so on. One or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 can be used to perform other semiconductor processing operations described herein, such as in combination with Figures 3A-3S and / or Figure 5 wait.

[0028] Figure 1 The number and arrangement of the devices shown are provided as one or more examples. In fact, with...Figure 1 Compared to what is shown, there may be additional devices, fewer devices, different devices, or devices arranged differently. Furthermore, Figure 1 The two or more devices shown can be implemented in a single device, or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively, a group of devices (e.g., one or more devices) in the exemplary environment 100 can perform one or more functions described as being performed by another group of devices in the exemplary environment 100.

[0029] Figures 2A-2C This is a diagram of the exemplary semiconductor photonic device 200 described herein. The semiconductor photonic device 200 may include one or more photonic integrated circuits. The semiconductor photonic device 200 may be configured to use optical signals to perform high-speed and secure data transmission between integrated circuits and / or semiconductor dies of the semiconductor photonic device 200 and / or between the semiconductor photonic device 200 and another component.

[0030] Figure 2A A perspective view of a semiconductor photonic device 200 is shown. Figure 2B It shows along Figure 2A A cross-sectional view of the semiconductor photonic device 200 with line AA in the image. Figure 2A and Figure 2B As shown, the semiconductor photonic device 200 may include a substrate 202. The substrate 202 may be formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), and / or another type of semiconductor material. The semiconductor photonic device 200 may also include a dielectric layer 204 above the substrate 202. The dielectric layer 204 may be referred to as a buried oxide (BOX) layer. The dielectric layer 204 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide and / or other dielectric materials.

[0031] The semiconductor photonic device 200 may also include another dielectric layer 206 on top of the substrate 202. The dielectric layer 206 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x Ny ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated quartz glass (FSG), carbon-doped silicon oxide and / or other dielectric materials.

[0032] Semiconductor photonic device 200 includes one or more photonic integrated circuit devices in dielectric layer 206, such as optical modulator structure 208, grating coupler structure 210, and / or another photonic integrated circuit device such as waveguide structure. Data can be encoded into optical signals by modulating light into optical pulses in optical modulator structure 208. The optical pulses are then transmitted to grating coupler structure 210 for propagation to other areas of semiconductor photonic device 200 and / or another device, such as an optical fiber. Additionally and / or alternatively, grating coupler structure 210 can receive optical signals (e.g., from optical fiber) and can transmit the optical signals to optical modulator structure 208 for modulation.

[0033] The optical modulator structure 208 may include a semiconductor structure doped with one or more types of dopants (e.g., a silicon (Si) structure and / or other types of semiconductor structures). Figure 2A and Figure 2B In the example shown, the optical modulator structure 208 includes a ring-shaped top view and can be referred to as a micro-ring modulator (MRM) structure. Therefore, Figure 2A and Figure 2B A cross-section of the optical modulator structure 208 is shown, illustrating opposite sides of the annular shape of the optical modulator structure 208. Alternatively, the optical modulator structure 208 may comprise a Mach-Zehnder modulator (MZM) structure and / or another type of optical modulator structure.

[0034] The optical modulator structure 208 can be used as a resonant chamber and can modulate the optical input signal from the light source to generate a modulated optical signal (e.g., a modulated optical signal). An electrical input signal (e.g., voltage, current) can be applied to the optical modulator structure 208 to modulate the optical input signal. The electrical input signal can be or may correspond to a digital data stream (e.g., 1 and 0 values). The optical modulator structure 208 can modulate the amplitude, phase, frequency, and / or another property of the optical input signal based on the digital data stream of the optical modulator structure 208.

[0035] The grating coupler structure 210 may include a semiconductor structure (e.g., a silicon (Si) structure and / or other types of semiconductor structures). The grating coupler structure 210 may be configured to diffract or redirect an optical signal from an off-plane direction (e.g., the z-direction) in the semiconductor photonic device 200 to an in-plane direction (e.g., the x-direction, y-direction), which lies in the plane of the optical modulator structure 208. The grating coupler structure 210 may include a plurality of periodic gratings. The periodicity of the periodic gratings can be selected to achieve diffraction of one or more wavelengths of the optical signal. In some implementations, the periodicity of the periodic gratings may be selected based on the wavelength of the optical signal.

[0036] The semiconductor photonic device 200 includes one or more etch stop layers (ESLs) 212 and 214 over a dielectric layer 206 and over an optical modulator structure 208 and a grating coupler structure 210. ESLs 212 and 214 enable the etching of additional dielectric layers over the optical modulator structure 208 and the grating coupler structure 210 to form additional structures over the optical modulator structure 208 and the grating coupler structure 210 without etching into the dielectric layer 206. In other words, ESLs 212 and 214 protect the optical modulator structure 208 and the grating coupler structure 210 from damage during subsequent semiconductor processing operations. ESLs 212 and 214 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ESL 212 and ESL 214 may include dielectric materials different from those of other dielectric layers in the semiconductor photonic device 200 to provide etching selectivity of ESL 212 and ESL 214 relative to other dielectric layers.

[0037] Another dielectric layer 216 may be included in ESL 212 and ESL 214. Dielectric layer 216 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated quartz glass (FSG), carbon-doped silicon oxide and / or other dielectric materials.

[0038] Multiple contact structures 218 are included in and / or through ESL 212, ESL 214. Furthermore, contact structures 218 are included in and / or through dielectric layer 216. Contact structures 218 are electrically coupled and / or physically coupled to optical modulator structure 208, enabling the provision of electrical input signals to optical modulator structure 208. Contact structures 218 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), and other examples of conductive materials. Contact structures 218 may each include vias, trenches, contact plugs, and / or other types of conductive structures.

[0039] like Figure 2A and Figure 2B As further shown, the semiconductor photonic device 200 includes a modulator heater structure 220 located above the optical modulator structure 208 in the z-direction within the semiconductor photonic device 200. The modulator heater structure 220 may be included on ESL 214 and dielectric layer 216. As described above, the resonant wavelength of the optical modulator structure 208 may be sensitive to changes in operating temperature. Therefore, the modulator heater structure 220 may be configured to stabilize the operating temperature of the optical modulator structure 208 during operation. Specifically, the modulator heater structure 220 may heat the optical modulator structure 208 (e.g., increase its temperature) to an operating temperature setpoint, thereby stabilizing the operating performance of the optical modulator structure 208. In some embodiments, the modulator heater structure 220 is configured to maintain the operating temperature of the optical modulator structure 208 by modulating the temperature of the heat supplied to the optical modulator structure 208. For example, the temperature of the modulator heater structure 220 can be modulated within a range of approximately 100 degrees Celsius to approximately 800 degrees Celsius to maintain the operating temperature of the optical modulator structure 208 at or within the temperature threshold of the operating temperature setpoint of the optical modulator structure 208. However, other values ​​within this range are also within the scope of this disclosure.

[0040] The modulator heater structure 220 may include tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium-tungsten (TiW), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), molybdenum (Mo), and / or other materials capable of radiating heat through ESL 212 and ESL 214 to heat the optical modulator structure 208. The modulator heater structure 220 may be electrically and / or physically coupled to one or more contact structures 218 included in the dielectric layer 216. The contact structures 218 realize electrical inputs (e.g., voltage, current) that can be dissipated in the modulator heater structure 220, which converts the electrical inputs into thermal outputs (e.g., heat).

[0041] Multiple dielectric layers are included above and / or above dielectric layer 216 and contact structure 218. These dielectric layers may include ESL 222 above and / or above dielectric layer 216, dielectric layer 224 above and / or above dielectric layer 224, and / or dielectric layer 226 above and / or above dielectric layer 226, etc. ESL 222, dielectric layer 224, and dielectric layer 226 may each comprise one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other suitable dielectric materials.

[0042] The contact structure 218 and the modulator heater structure 220, coupled to the optical modulator structure 208, can be electrically and / or physically coupled to one or more metal layers 228. The metal layers 228 can each be included in ESL 222, dielectric layer 224, and / or dielectric layer 226, and can extend through ESL 222, dielectric layer 224, and / or dielectric layer 226. The metal layers 228 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), and other examples of conductive materials. The metal layers 228 can each include vias, trenches, contact plugs, and / or another type of metal layer.

[0043] like Figure 2A and Figure 2B As further shown, the semiconductor photonic device 200 includes an additional dielectric layer above and / or above the dielectric layer 226. For example, an ESL 230 may be included above and / or above the dielectric layer 226. As another example, a passivation layer 232 may be included above and / or above the ESL 230. As another example, a dielectric layer 234 is included above and / or above the passivation layer 232. The ESL 230, passivation layer 232, and dielectric layer 234 each include one or more dielectric materials, such as silicon oxide (SiO2). i O x ), silicon nitride (Si x Ni), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. In some embodiments, the passivation layer 232 comprises one or more polymer layers.

[0044] Metal pad 236 may be included in, and / or extend through, ESL 230, passivation layer 232, and / or dielectric layer 234. In some embodiments, dielectric layer 234 is included above and / or over metal pad 236. Metal pad 236 may include aluminum (Al) pads, copper (Cu) pads, and / or another type of metal pad. Metal pad 236 may be electrically and / or physically coupled to one or more of the metal layers 228.

[0045] A portion of dielectric layer 234 extends in the z-direction into and / or through dielectric layer 224, dielectric layer 226, ESL 230, and passivation layer 232. This portion of dielectric layer 234 includes a grating coupler transmission region 238, which is located above the grating coupler structure 210 in the z-direction of the semiconductor photonic device 200. The grating coupler transmission region 238 provides an area through which optical signals can be transmitted to and / or from the grating coupler structure 210. In some embodiments, an optical fiber may be inserted into the grating coupler transmission region 238, and the dielectric layer 234 encapsulates the optical fiber within the grating coupler transmission region 238. In some embodiments, the grating coupler transmission region 238 is completely filled with a dielectric material incorporated with the dielectric layer 234, and the optical fiber is coupled to the top surface of the dielectric layer 234 above the grating coupler transmission region 238.

[0046] like Figure 2A and Figure 2B As further shown, the semiconductor photonic device 200 includes an isolation trench 240. In Figure 2B and Figure 2C In the top view, the isolation trench 240 is included on the opposite side of the modulator heater structure 220. In the top view of the modulator heater structure 220, the isolation trench 240 is included around the modulator heater structure 220 such that the isolation trench 240 surrounds the modulator heater structure 220 in the top view of the modulator heater structure 220. The isolation trench 240 is included in and / or extends through dielectric layers 216, ESL 222, dielectric layers 224, dielectric layers 226, ESL 230 and / or passivation layer 232. The top opening of the isolation trench 240 is sealed by dielectric layer 234 to prevent contaminants from entering the isolation trench 240. Therefore, a portion of dielectric layer 234 may extend into a portion of the top opening of the isolation trench 240. The grating coupler transmission area 238 extends along one side of the isolation trench 240.

[0047] The isolation trench 240 terminates on ESL 214, thus preventing it from extending into the underlying dielectric layer 206 surrounding ESL 212 and / or the optical modulator structure 208. This allows optical signals to be transmitted between the optical modulator structure 208 and the grating coupler structure 210 (and other photonic integrated circuit components) without interference from the isolation trench 240. Furthermore, this allows ESL 214 to act as an etch stop layer during the etching of the dielectric layer to form the isolation trench 240, reducing the processing time and complexity of forming the isolation trench 240 compared to forming it as dielectric layer 206.

[0048] The isolation trench 240 may be filled with a dielectric gas, such as atmosphere or residual processing gas (e.g., nitrogen (N2), argon (Ar)) from semiconductor processing operations performed to form the isolation trench 240 and / or dielectric layer 234. The isolation trench 240 establishes an isolation region in the dielectric layer surrounding and above the modulator heater structure 220. The isolation region is thermally and / or mechanically isolated from other portions of the dielectric layer. The isolation region may include thermally insulating portions 216a of dielectric layer 216, 222a of ESL 222, 224a of dielectric layer 224, 226a of dielectric layer 226, 230a of ESL 230, 232a of passivation layer 232, etc.

[0049] Isolation trench 240 serves as a thermal isolation trench and / or a stress isolation trench. For example, isolation trench 240 acts as a thermal barrier, preventing (or reducing the likelihood or amount of heat) from the modulator heater structure 220 from dissipating through the isolation sections 216a, 222a, 224a, 226a, 230a, and 232a, and further into the dielectric layers 216, 224, 226, ESL 222, and ESL 230, and the passivation layer 232. Therefore, isolation trench 240 prevents or reduces the possibility of cracking, delamination, and / or other types of damage to the dielectric layers 216, 224, 226, ESL 222, and ESL 230, and the passivation layer 232. Specifically, the heat provided by the modulator heater structure 220 can be modulated to maintain a consistent operating temperature of the optical modulator structure 208, and this thermal modulation (or thermal cycling) may additionally cause fatigue, which may lead to cracking, delamination, and / or other types of damage to the dielectric layers 216, 224, 226, ESL 222 and ESL 230, and the passivation layer 232 (excluding the isolation trench 240). Additionally, the isolation trench 240 also acts as a stress isolation trench, as it prevents (or reduces the likelihood) the propagation of cracking, delamination, and / or other types of damage from the isolation portions 216a, 222a, 224a, 226a, 230a, and 232a to the dielectric layers 216, 224, 226, ESL 222 and ESL 230, and the passivation layer 232.

[0050] Compared to the isolation trench 240 not included around the modulator heater structure 220, the thermal and / or stress isolation provided by the isolation trench 240 allows the metal layer 228 and / or the grating coupler transmission region 238 to be positioned closer to the modulator heater structure 220 in the xy plane of the semiconductor photonic device 200. One or more design parameters of the semiconductor photonic device 200 can specify a minimum distance (e.g., a keep-out zone, KOZ) between the metal layer 228 (and other structures in the semiconductor photonic device 200, such as the grating coupler transmission region 238) and the modulator heater structure 220. This allows reliability parameters of the semiconductor photonic device 200 to be achieved. The minimum distance can be based on the distance and magnitude of thermal propagation from the modulator heater structure 220 to dielectric layers 216, 224, 226, ESL 222 and ESL 230, and passivation layer 232. Because the isolation trench 240 reduces the heat propagation distance and / or amplitude from the modulator heater structure 220 to dielectric layers 216, 224, 226, ESL 222 and ESL 230, and passivation layer 232, the isolation trench 240 allows the metal layer 228 (and other structural devices 200 in semiconductor photonics, such as grating coupler transmission region 238) to be positioned closer to the modulator heater structure 220 without adversely affecting the reliability of the semiconductor photonic device 200. Therefore, the isolation trench 240 allows for a reduction in the size (e.g., size in the xy plane) of the semiconductor photonic device 200 and / or an increase in the density of structures within the semiconductor photonic device 200.

[0051] like Figure 2C As shown, the optical modulator structure 208 may include one or more doped regions. These doped regions may promote and / or facilitate electron flow within the optical modulator structure 208 and / or promote and / or facilitate modulation of the optical input signal from an electrical input signal. For example, the one or more doped regions may be configured as pn junctions, which are configured to generate modulated optical signals. When an electrical input signal is applied to the pn junction of the optical modulator structure 208, the junction depletion width of the pn junction is modified. This results in a change in the electron and hole concentrations within the optical modulator structure 208. This change in electron and hole concentrations can lead to a change in the effective refractive index of the optical modulator structure 208, which can modulate the light intensity of the optical input signal within the optical modulator structure 208, thereby enabling the electrical input signal to be converted into a modulated optical signal.

[0052] One or more doped regions may comprise silicon (and / or another semiconductor material) doped with one or more types of dopants (e.g., n-type dopants and / or p-type dopants). For example, the optical modulator structure 208 may comprise a p-doped region 242 doped with p-type ions. P-type ions may comprise p-type materials (e.g., boron (B) or germanium (Ge)). As another example, the optical modulator structure 208 may comprise an n-doped region 244 doped with n-type ions. N-type ions may comprise n-type materials (e.g., phosphorus (P) or arsenic (As)). The n-doped region 244 and the p-doped region 242 may be adjacent and / or physically coupled, and may correspond to the pn junction of the optical modulator structure 208.

[0053] The optical modulator structure 208 may also include a p-doped region 246 adjacent to the p-doped region 242. The p-doped region 246 may include p-type ions, which may include p-type materials (e.g., boron (B) or germanium (Ge)). The optical modulator structure 208 may also include an n-doped region 248 adjacent to the n-doped region 244. The n-doped region 248 may include n-type ions, which may include n-type materials (e.g., phosphorus (P) or arsenic (As)).

[0054] The optical modulator structure 208 may also include a p+ doped region 250 adjacent to the p-doped region 246. The p+ doped region 250 may include p-type ions, which may include p-type materials (e.g., boron (B) or germanium (Ge), etc.). The optical modulator structure 208 may also include an n+ doped region 252 adjacent to the n-doped region 248. The n+ doped region 252 may include n-type ions, which may include n-type materials (e.g., phosphorus (P) or arsenic (As), etc.).

[0055] p-doped regions 242, 246, and 250 can each include different p-type dopant concentrations. These different p-type dopant concentrations result in a dopant gradient between the center and outer wall of the optical modulator structure 208. The p-type dopant concentration in p+ doped region 250 can be greater than that in p-doped region 246, and the p-type dopant concentration in p-doped region 246 can also be greater than that in p-doped region 246. p-doped region 242. For example, p-doped region 242 can be included in approximately 1xe... 17 p-type ions / cm 3 To approximately 5xe 18 p-type ions / cm 3 The p-type dopant concentration is within the range specified in this disclosure. However, other values ​​within this range are also within the range specified in this disclosure. As another example, the p-doped region 246 may include approximately 1 x e 19 p-type ions / cm 3To approximately 1xe 20 p-type ions / cm 3 The p-type dopant concentration is within the range specified in this disclosure. However, other values ​​within this range are also within the range specified in this disclosure. As another example, the p+ doped region 250 may include approximately 1 x e 20 p-type ions / cm 3 To approximately 5xe 20 p-type ions / cm 3 The range of p-type dopant concentrations. However, other values ​​in this range are also within the range disclosed herein.

[0056] The n-doped regions 244, n-doped regions 248, and n+doped regions 252 may each include different n-type dopant concentrations. Different n-type dopant concentrations result in a dopant gradient between the center of the optical modulator structure 208 and its inner wall. The n-type dopant concentration in the n+doped region 252 can be greater than that in the n-doped region 248, and the n-type dopant concentration in the n-doped region 248 can be greater than that in the n-doped region 244. For example, the n-doped region 244 may include approximately 1 x e 17 n-type ions / cm 3 To approximately 5xe 18 n-type ions / cm 3 The range of n-type dopant concentrations is specified. However, other values ​​within this range are also within the range disclosed herein. As another example, the n-doped region 248 may include approximately 1 x e 19 n-type ions / cm 3 To approximately 1xe 20 n-type ions / cm 3 The range of n-type dopant concentrations is specified. However, other values ​​within this range are also within the range disclosed herein. As another example, the n+ doped region 252 may include approximately 1 x e 20 n-type ions / cm 3 To approximately 5xe 20 n-type ions / cm 3 The range of n-type dopant concentrations. However, other values ​​in this range are also within the range disclosed herein.

[0057] Figure 2C A top view of a cross-section of a portion of the semiconductor photonic device 200 in the xy plane is shown. Figures 2A-2CAs shown, in a top view of the semiconductor photonic device 200, an isolation trench 240 is included around the modulator heater structure 220, such that the isolation trench 240 surrounds the modulator heater structure 220 in the top view. In the top view of the semiconductor photonic device 200, the isolation trench 240 has a circular top view shape, such as an annular top view shape (e.g., an annular air gap) or a circular top view shape. A circular top view shape prevents (or reduces the likelihood) the accumulation of localized stress at any particular location around the isolation trench 240.

[0058] like Figures 2A-2C As further shown, the semiconductor photonic device 200 includes one or more dimensions, such as dimensions D1 and D2. Dimension D1 corresponds to the distance between the modulator heater structure 220 and the isolation trench 240. Therefore, dimension D1 also corresponds to the width of the isolation portions 216a, 222a, 224a, 226a, 230a, and 232a between the modulator heater structure 220 and the isolation trench 240. In some embodiments, dimension D1 is included in the range of about 10 micrometers to about 20 micrometers. If dimension D1 is less than about 10 micrometers, process variations in the process used to etch dielectric layers 216, 224, 226, ESL 222 and ESL 230, and passivation layer 232 to form the isolation trench 240 may cause etching into the modulator heater structure 220. This may damage the modulator heater structure 220 and / or cause the modulator heater structure 220 to malfunction. If the dimension D1 is greater than about 20 micrometers, the isolation portions 216a, 222a, 224a, 226a, 230a, and 232a may be too large, which could lead to cracking, delamination, and / or other types of damage to the isolation portions 216a, 222a, 224a, 226a, 230a, and / or 232a. If the dimension D1 is included in the range of about 10 micrometers to about 20 micrometers, the isolation trench 240 can be formed without etching into the modulator heater structure 220, while reducing the likelihood of cracking, delamination, and / or other types of damage to the isolation portions 216a, 222a, 224a, 226a, 230a, and / or 232a. However, other values ​​of dimension D1, as well as ranges other than about 10 micrometers to about 20 micrometers, are also within the scope of this disclosure.

[0059] Dimension D2 corresponds to the width of the isolation trench 240. Therefore, dimension D2 also corresponds to the distance between the isolation portions 216a, 222a, 224a, 226a, 230a, and 232a and other areas of dielectric layers 216, 224, 226, ESL 222 and ESL 230, and passivation layer 232. In some embodiments, dimension D2 is included in the range of approximately 5 micrometers to approximately 15 micrometers. If dimension D2 is less than approximately 5 micrometers, the isolation trench 240 may be too narrow to allow the etchant used to etch the isolation trench 240 to be completely removed from the isolation trench 240. This could result in residual etchant contaminating dielectric layers 216, 224, 226, ESL 222 and ESL 230, and passivation layer 232, and / or passivation layer 232 to the isolation trench 240. If the size D2 is greater than about 15 micrometers, etch load may occur in the isolation trench 240, which could lead to an uncontrollable etch rate when etching the isolation trench 240. This could result in over-etching (e.g., etching through ESL 212, ESL 214 and into the underlying dielectric layer 206). If the size D2 is within the range of about 5 micrometers to about 15 micrometers, a low probability of over-etching and a high probability of complete etchant removal can be achieved when etching the isolation trench 240. However, other values ​​of size D2, as well as ranges other than about 5 micrometers to about 15 micrometers, are also within the scope of this disclosure.

[0060] As mentioned above, providing Figures 3A-3S As an example. Other examples can be found related to... Figure 3A The descriptions are different.

[0061] Figure 3B This is a diagram illustrating an exemplary embodiment 300 of the semiconductor photonic device 200 (or a portion thereof) described herein. In some embodiments, one or more of the semiconductor processing operations described in connection with exemplary embodiment 300 may be performed by one or more of semiconductor processing tools 102-114 and / or by wafer / die transport tool 116. In some implementations, one or more semiconductor processing operations described in connection with exemplary embodiment 300 may be performed by another semiconductor processing tool.

[0062] Turning Figure 3C A substrate 302 may be provided. The substrate 302 may include a silicon-on-insulator (SOI) substrate, which includes a substrate 202 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a dielectric layer 204 (e.g., a BOX layer and / or another type of insulator), and a semiconductor layer 304 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) on and / or above the substrate 202.

[0063] Alternatively, substrate 202 may be provided as a semiconductor wafer, and deposition tool 102 may form a dielectric layer 204 on and / or over substrate 202, and a semiconductor layer 304 may be formed on and / or over dielectric layer 204. Deposition tool 102 may be used to deposit dielectric layer 204 using CVD technology, PVD technology, oxidation technology (e.g., thermal oxidation technology) and / or another type of deposition technology. Deposition tool 102 may be used to deposit semiconductor layer 304 using CVD technology, PVD technology, epitaxial technology and / or another type of deposition technology.

[0064] like Figure 3D As shown, the optical modulator structure 208 and the grating coupler structure 210 are formed on the semiconductor layer 304. In some embodiments, a pattern in the hard mask layer is used to etch the semiconductor layer 304 to form the optical modulator structure 208 and the grating coupler structure 210.

[0065] Deposition tool 102 can be used to deposit a hard mask layer on semiconductor layer 304 (e.g., using CVD, PVD, and / or another type of deposition technique), and can form a photoresist layer on the hard mask layer (e.g., using spin coating and / or another type of deposition technique). Exposure tool 104 can be used to expose the photoresist layer to a radiation source to form a pattern of the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch the hard mask layer to transfer the pattern from the photoresist layer to the hard mask layer. Etching tool 108 can be used to etch semiconductor layer 304 based on the pattern in the hard mask layer to form optical modulator structure 208 and grating coupler structure 210 by removing portions of semiconductor layer 304 based on the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, the planarization tool 110 is used to remove the remaining portion of the hard mask layer using CMP technology and / or another type of planarization technique.

[0066] like Figure 3EAs shown, dielectric layer 206 is deposited on and / or above dielectric layer 204. Furthermore, dielectric layer 206 is deposited on and / or above the optical modulator structure 208 and the grating coupler structure 210. Deposition tool 102 can be used to deposit dielectric layer 206 using CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique. In some implementations, depositing dielectric layer 206 encapsulates optical modulator structure 208 and / or grating coupler structure 210. Planarization tool 110 can be used to perform CMP operations and / or another type of planarization operation to planarize dielectric layer 206 such that the top surface of dielectric layer 206 is coplanar with the top surface of optical modulator structure 208.

[0067] like Figure 1 As shown, one or more portions of the optical modulator structure 208 may be doped with one or more types of dopants to form one or more doped regions in the optical modulator structure 208. For example, ion implantation tool 114 may be used to implant p-ions into p-doped region 242 using ion implantation technology and / or another type of doping technology. As another example, ion implantation tool 114 may be used to implant n-ions into n-doped region 244 using ion implantation technology and / or another type of doping technology. As another example, ion implantation tool 114 may be used to implant p-ions into p-doped region 246 using ion implantation technology and / or another type of doping technology. As another example, ion implantation tool 114 may be used to implant n-ions into n-doped region 248 using ion implantation technology and / or another type of doping technology. As yet another example, ion implantation tool 114 may be used to implant p+ ions into p+ doped region 250 using ion implantation technology and / or another type of doping technology. As yet another example, ion implantation tool 114 may be used to implant n+ ions into n+ doped region 252 using ion implantation technology and / or another type of doping technology.

[0068] like Figure 3F As shown, after forming the optical modulator structure 208 and / or after forming the grating coupler structure 210, one or more additional layers may be formed on and / or above the dielectric layer 206. For example, ESL 212 and / or ESL 214 may be formed on and / or above the dielectric layer 206. As another example, a first portion of the dielectric layer 216 may be formed on and / or above ESL 214. The deposition tool 102 may use PVD, ALD, CVD, oxidation, or bonding techniques. Figure 3GAnother type of deposition technique, and / or another suitable deposition technique, is described to deposit the first portion of ESL 212, ESL 214, and / or dielectric layer 216. In some embodiments, planarization tool 110 is used to planarize the first portion of ESL 212, ESL 214, and / or dielectric layer 216 after deposition.

[0069] like Figure 1 As shown, a recess 306 is formed in the first portion of dielectric layer 216. The recess 306 is formed along the z-direction above the optical modulator structure 208 in the semiconductor photonic device 200. The recess 306 can be formed during preparation for forming the modulator heater structure 220 in dielectric layer 216.

[0070] In some embodiments, the pattern in the photoresist layer is used to etch a first portion of the dielectric layer 216 to form a recess 306. In these embodiments, a deposition tool 102 is used to form a photoresist layer on the first portion of the dielectric layer 216. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 is used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch the first portion of the dielectric layer 216 based on the pattern to form the recess 306 in the first portion of the dielectric layer 216. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the first portion of the dielectric layer 216.

[0071] like Figure 3H As shown, the modulator heater structure 220 is formed in the recess 306. The deposition tool 102 and / or electroplating tool 112 can be used with CVD, PVD, ALD, electroplating, or other technologies combined with the above. Figure 3H Another deposition technique and / or another suitable deposition technique are described to deposit the modulator heater structure 220. In some embodiments, a first seed layer is deposited, and the modulator heater structure 220 is deposited on the seed layer. In some embodiments, a planarization tool 110 is used to planarize the modulator heater structure 220 after deposition.

[0072] like Figure 3IAs shown, a second portion of dielectric layer 216 is formed on and / or over the first portion of dielectric layer 216. The second portion of dielectric layer 216 is also formed on and / or over modulator heater structure 220. Deposition tool 102 can be used to deposit the second portion of dielectric layer 216 using CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique. In some embodiments, planarization tool 110 is used to planarize dielectric layer 216 after the second portion of dielectric layer 216 has been deposited.

[0073] like Figure 1 As further shown, the recess 308 is formed through the dielectric layer 216, through ESL 214, and / or through ESL 212. For example, the recess 308 reaching the p+ doped region 250 of the optical modulator structure 208 can be formed through the dielectric layer 216, through ESL 214, and through ESL 212, such that the p+ doped region 250 is exposed through the recess 308. As another example, the recess 308 can be formed through the dielectric layer 216, through ESL 214, and through ESL 212 to the n+ doped region 252 of the optical modulator structure 208, such that the n+ doped region 252 is exposed through the recess 308. As yet another example, the recess 308 can be formed in the dielectric layer 216 to the modulator heater structure 220, such that the modulator heater structure 220 is exposed through the recess 308.

[0074] In some embodiments, the pattern in the photoresist layer is used to etch dielectric layer 216, ESL 214, and / or ESL 212 to form recess 308. In these embodiments, deposition tool 102 is used to form a photoresist layer on dielectric layer 216. Exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 is used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 is used to etch through dielectric layer 216, through ESL 214, and / or through ESL 212 to form recess 308. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of recess 308.

[0075] like Figure 3JAs shown, contact structure 218 is formed in a recess 308 above the p+ doped region 250 of the optical modulator structure 208, such that contact structure 218 rests on the p+ doped region 250. Contact structure 218 is also formed in a recess 308 above the n+ doped region 252 of the optical modulator structure 208, such that contact structure 218 rests on the n+ doped region 252. Contact structure 218 is also formed in a recess 308 above the modulator heater structure 220, such that contact structure 218 rests on the modulator heater structure 220.

[0076] Deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and the above combination. Figure 1 Another deposition technique, and / or another suitable deposition technique, is described to deposit the contact structure 218. In some embodiments, a first seed layer is deposited, and one or more of the contact structures 218 are deposited on the seed layer. In some embodiments, a planarization tool 110 is used to planarize one or more of the contact structures 218.

[0077] like Figure 3J As shown, ESL 222 is formed on and / or above dielectric layer 216 and on and / or above contact structure 218. Dielectric layer 224 is formed on and / or above ESL 222. Dielectric layer 226 is formed on and / or above dielectric layer 224. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit ESL 222, dielectric layer 224, and / or dielectric layer 226. In some embodiments, planarization tool 110 is used to planarize ESL 222, dielectric layer 224, and / or dielectric layer 226 after deposition by deposition tool 102.

[0078] like Figure 3K As further shown, the metal layer 228 is formed in and / or through the ESL 222, in and / or through the dielectric layer 224, and / or in and / or through the dielectric layer 226.

[0079] Deposition tool 102 and / or electroplating tool 112 can utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1Another deposition technique and / or another suitable deposition technique are described to deposit the metal layer 228. In some embodiments, a first seed layer is deposited, and one or more metal layers 228 are deposited on the seed layer. In some embodiments, after depositing one or more metal layers 228, a planarization tool 110 is used to planarize the one or more metal layers 228.

[0080] In some embodiments, the metal layer 228 is formed in multiple deposition operations. For example, an ESL 222 and a dielectric layer 224 may be formed, and a first set of one or more metal layers 228 may be formed in and / or through the ESL 222 and dielectric layer 224, such that the first set of one or more metal layers 228 falls on the contact structure 218. A first portion of a dielectric layer 226 may then be formed, and a second set of one or more metal layers 228 may be formed in the first portion of the dielectric layer 226. A second portion of the dielectric layer 226 may then be formed, and a third set of one or more metal layers 228 may be formed in the first portion of the dielectric layer 226. These operations may continue until a certain amount of metal layers 228 are formed.

[0081] like Figure 3L As shown, ESL 230 is formed on and / or above dielectric layer 226. Passivation layer 232 is formed on and / or above ESL 230. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 3M Another type of deposition technique and / or another suitable deposition technique is described to deposit ESL 230 and / or passivation layer 232. In some embodiments, planarization tool 110 is used to planarize ESL 230 and / or passivation layer 232 after deposition.

[0082] like Figure 1 As further shown, the recess 310 is formed through the passivation layer 232 and / or through the ESL 230. One or more metal layers 228 are exposed through the recess 310.

[0083] In some embodiments, the pattern in the photoresist layer is used to etch the passivation layer 232 and / or ESL 230 to form the recess 310. In these embodiments, a deposition tool 102 is used to form a photoresist layer on the passivation layer 232. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 is used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch through the passivation layer 232 and / or through the ESL 230 to form the recess 310. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the recess 310.

[0084] like Figure 3N As shown, a metal pad 236 is formed in the recess 310, such that the metal pad 236 rests on the metal layer 228. The deposition tool 102 and / or electroplating tool 112 can be used with CVD, PVD, ALD, electroplating, or other bonding technologies. Figure 3O Another deposition technique, and / or another suitable deposition technique, is described to deposit the metal pad 236. In some embodiments, a first seed layer is deposited, and one or more of the metal pads 236 are deposited on the seed layer.

[0085] like Figure 3P As shown, isolation trench 240 is formed in and / or through passivation layer 232, ESL 230, dielectric layer 226, dielectric layer 224, ESL 222, and dielectric layer 226. Figure 1 As shown, the isolation trench 240 is formed around the modulator heater structure 220 such that the isolation trench 240 surrounds the modulator heater structure 220 and has a circular (e.g., annular) top view shape in the top view of the semiconductor photonic device 200.

[0086] In some embodiments, the pattern in the photoresist layer is used to etch passivation layer 232, ESL 230, dielectric layer 226, dielectric layer 224, ESL 222, and dielectric layer 216 to form isolation trench 240. In these embodiments, deposition tool 102 is used to form a photoresist layer on passivation layer 232. Exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 is used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 is used to etch through passivation layer 232, ESL 230, dielectric layer 226, dielectric layer 224, ESL 222, and dielectric layer 216 to form isolation trench 240. Etching of isolation trench 240 stops at ESL 214, such that isolation trench 240 does not extend around the optical modulator structure 208 in dielectric layer 206. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the isolation trench 240.

[0087] like Figure 3P As shown, dielectric layer 234 is formed on and / or above passivation layer 232. Dielectric layer 234 is also formed on and / or above metal pad 236. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 3Q Another type of deposition technique and / or another suitable deposition technique is described to deposit dielectric layer 234. In some embodiments, planarization tool 110 is used to planarize dielectric layer 234 after deposition.

[0088] like Figure 3R As further shown, dielectric layer 234 seals the top opening of isolation trench 240. (As illustrated...) Figure 3S As shown, a dielectric layer 234 can be deposited such that the material of the dielectric layer 234 seals the gap between the isolation portion 232a of the passivation layer 232 and the rest of the passivation layer 232 before the isolation trench 240 is completely filled with the material of the dielectric layer 234. This ensures that the dielectric layer 234 is primarily filled with gas, thereby enabling the isolation trench 240 to provide thermal and / or structural isolation.

[0089] like Figures 3A-3S As shown, a recess 312 is formed along one side of the isolation trench 240. The recess 312 can be formed above the grating coupler structure 210 in the z-direction of the semiconductor photonic device 200. The recess 312 can be formed through the dielectric layer 234, passivation layer 232, ESL 230, dielectric layer 226, and dielectric layer 224.

[0090] In some embodiments, the pattern in the photoresist layer is used to etch dielectric layer 234, passivation layer 232, ESL 230, dielectric layer 226, and dielectric layer 224 to form a recess 312. In these embodiments, a deposition tool 102 is used to form a photoresist layer on dielectric layer 234. An exposure tool 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 is used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 is used to etch through dielectric layer 234, passivation layer 232, ESL 230, dielectric layer 226, and dielectric layer 224 to form an isolation trench 240. Etching of the recess 312 stops at ESL 222. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to the pattern-forming recess 312.

[0091] like Figures 3A-3S As shown, the recess 312 can be filled with dielectric material to form a grating coupler transmission region 238 along the side of the isolation trench 240. In some embodiments, an optical fiber can first be inserted into the recess 312, and then the recess 312 can be filled with dielectric material to encapsulate the optical fiber within the recess 312. The dielectric material of the grating coupler transmission region 238 can be incorporated with the dielectric layer 234.

[0092] As mentioned above, providing Figure 4 As an example. Other examples can be found related to... Figure 4 The descriptions are different.

[0093] Figure 4 This is a diagram of exemplary components of the apparatus 400 described herein. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may include one or more of the apparatus 400 and / or one or more components of the apparatus 400. Figure 4 As shown, device 400 may include bus 410, processor 420, memory 430, input component 440, output component 450 and / or communication component 460.

[0094] Bus 410 may include one or more components capable of wired and / or wireless communication between components of device 400. Bus 410 can... Figure 4Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 410 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 420 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 420 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 420 may include one or more processors or processes capable of being programmed to perform one or more operations described elsewhere herein.

[0095] Memory 430 may include volatile and / or non-volatile memory. For example, memory 430 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 430 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a Universal Serial Bus connection). Memory 430 may be a non-transitory computer-readable medium. Memory 430 may store information related to the operation of device 400, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 430 may include one or more memories such as those coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 420) via bus 410. The communicative coupling between processor 420 and memory 430 enables processor 420 to read and / or process information stored in memory 430 and / or information stored in memory 430.

[0096] Input component 440 enables device 400 to receive input, such as user input and / or sensed input. For example, input component 440 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output component 450 enables device 400 to provide output, such as via a display, speaker, and / or LED. Communication component 460 enables device 400 to communicate with other devices via wired and / or wireless connections. For example, communication component 460 may include a receiver, transmitter, transceiver, modem, network adapter, and / or antenna.

[0097] Device 400 may perform one or more of the operating processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 430) may store a set of instructions (e.g., one or more instructions or program code) for execution by processor 420. Processor 420 may execute the set of instructions to perform one or more operating processes described herein. In some implementations, execution of the set of instructions by one or more processors 420 causes one or more processors 420 and / or device 400 to perform one or more operations or processes described herein. In some implementations, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more operations or processes described herein. Alternatively or additionally, processor 420 may be configured to perform one or more operating processes described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuitry and software.

[0098] Figure 5 The number and arrangement of components shown are provided as an example only. Device 400 may include components related to... Figure 5 The components shown are those that are additional, fewer, different, or arranged differently compared to other components. Alternatively, a set of components of device 400 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 400.

[0099] Figure 5 This is a flowchart of an exemplary fabrication process 500 associated with the formation of the semiconductor photonic device described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114) are used to perform the process. Figure 5 One or more process blocks. Alternatively, Figure 5 One or more process blocks may be executed using one or more components of device 400, such as processor 420, memory 430, input component 440, output component 450 and / or communication component 460.

[0100] like Figure 5 As shown, process 500 may include forming an optical modulator structure (block 510) in a semiconductor layer above a first dielectric layer of the semiconductor photonic device. For example, one or more of semiconductor processing tools 102-114 may be used in the first dielectric layer (e.g., dielectric layer 204 of the semiconductor photonic device (e.g., semiconductor photonic device 200)) as described herein.

[0101] like Figure 5As further shown, process 500 may include forming a second dielectric layer (block 520) over the first dielectric layer surrounding the optical modulator structure. For example, one or more of semiconductor processing tools 102-114 may be used to form a second dielectric layer (e.g., dielectric layer 206) over the first dielectric layer surrounding the optical modulator structure, as described herein.

[0102] like Figure 5 As further shown, process 500 may include forming an etch stop layer (block 530) over the second dielectric layer and over the optical modulator structure. For example, one or more of semiconductor processing tools 102-114 may be used to form an etch stop layer (e.g., ESL 214) over the second dielectric layer and over the optical modulator structure, as described herein.

[0103] like Figure 5 As further shown, process 500 may include a first portion (block 540) of forming a third dielectric layer over an etch stop layer. For example, one or more of semiconductor processing tools 102-114 may be used to form a first portion of a third dielectric layer (e.g., dielectric layer 216) over an etch stop layer, as described herein.

[0104] like Figure 5 As further shown, process 500 may include a modulator heater structure (block 550) in a first portion of forming a third dielectric layer over the optical modulator structure. For example, one or more of semiconductor processing tools 102-114 may be used for a modulator heater structure (e.g., modulator heater structure 220) in a first portion of forming a third dielectric layer over the optical modulator structure, as described herein.

[0105] like Figure 5 As further shown, process 500 may include forming a second portion of the third dielectric layer and multiple dielectric layers (block 560) over a first portion of the third dielectric layer and over the modulator heater structure. For example, one or more of semiconductor processing tools 102-114 may be used to form a second portion of the third dielectric layer and multiple dielectric layers (e.g., ESL 222, dielectric layer 224, dielectric layer 226) over the first portion of the third dielectric layer and over the modulator heater structure, as described herein.

[0106] like Figure 5As further shown, process 500 may include forming an isolation trench (block 570) that extends through multiple dielectric layers, through a third dielectric layer, and to an etch stop layer. For example, one or more of semiconductor processing tools 102-114 may be used to form the isolation trench (e.g., isolation trench 240) to the multiple dielectric layers, to the third dielectric layer, and up to the etch stop layer, as described herein. In some embodiments, in a top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure. In some embodiments, the isolation trench has a circular top view shape in a top view of the semiconductor photonic device.

[0107] Process 500 may include other implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0108] In a first embodiment, process 500 includes forming an oxide layer (e.g., dielectric layer 234) over a plurality of dielectric layers, wherein the oxide layer seals the top opening of the isolation trench.

[0109] In the second implementation, either alone or in combination with the first embodiment, process 500 includes forming a grating coupler structure (e.g., grating coupler structure 210) adjacent to the optical modulator structure in a semiconductor layer, and forming a grating coupler transmission region (e.g., grating coupler transmission region 238) through multiple dielectric layers, wherein forming an isolation trench includes forming an isolation trench adjacent to the grating coupler transmission region.

[0110] In the third embodiment, forming an isolation trench, alone or in combination with one or more of the first and second embodiments, includes forming an isolation trench such that the distance (e.g., dimension D1) between the modulator heater structure and the isolation trench is included in the range of about 10 micrometers to about 20 micrometers.

[0111] In the fourth embodiment, forming an isolation trench, alone or in combination with one or more of the first to third embodiments, includes performing an acid-based wet etching operation to form the isolation trench.

[0112] In the fifth embodiment, forming an isolation ditch, alone or in combination with one or more of the first to fourth embodiments, includes forming an isolation ditch such that the width of the isolation ditch (e.g., dimension D2) is in the range of about 5 micrometers to about 15 micrometers.

[0113] although ​ An example block for process 500 is shown, but in some embodiments, process 500 includes... ​The blocks depicted in the diagram are those that are additional, fewer, different, or arranged differently. Alternatively, two or more of the blocks or processes in 500 can be executed in parallel.

[0114] Thus, the semiconductor photonic device includes an optical modulator structure and a modulator heater structure within one or more dielectric layers of the semiconductor photonic device. An isolation trench surrounds the modulator heater structure to reduce the possibility of thermal stress causing damage to the dielectric layer. The isolation trench may include an air gap through the dielectric layer, and in a top view of the semiconductor photonic device, the air gap surrounds the modulator heater structure. The isolation trench reduces the heat absorbed in the dielectric layer because it thermally insulates the modulator heater structure from the dielectric layer. In particular, the isolation trench prevents heat from being transferred from the modulator heater structure to the surrounding dielectric layer. This reduces the likelihood of cracking, delamination, and / or other types of damage to the dielectric layer, which could otherwise be caused by thermal stress on the dielectric layer.

[0115] As described in more detail above, some implementations described herein provide semiconductor photonic devices. A semiconductor photonic device includes a substrate. A semiconductor photonic device includes one or more first dielectric layers above the substrate. A semiconductor photonic device includes an etch stop layer above the one or more first dielectric layers. A semiconductor photonic device includes a plurality of second dielectric layers above the etch stop layer. A semiconductor photonic device includes an optical modulator structure within one or more first dielectric layers. A semiconductor photonic device includes a modulator heater structure within one or more of the plurality of second dielectric layers, wherein the modulator heater structure is located above the optical modulator structure. A semiconductor photonic device includes an isolation trench to the plurality of second dielectric layers, wherein the isolation trench terminates on the etch stop layer, and wherein, in a top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure.

[0116] In this novel embodiment, the modulator heater structure is located on the top surface of the etch stop layer.

[0117] In this novel embodiment, the isolation trench has an annular shape in the top view of the semiconductor photonic device.

[0118] In this novel embodiment, the isolation ditch is filled with gas.

[0119] In this novel embodiment, the distance between the modulator heater structure and the isolation trench is in the range of about 10 micrometers to about 20 micrometers.

[0120] In an embodiment of this novel invention, the width of the isolation ditch is in the range of about 5 micrometers to about 15 micrometers.

[0121] In this novel embodiment, the semiconductor photonic device further includes an oxide layer over the plurality of second dielectric layers, wherein the top of the isolation trench is sealed by the oxide layer.

[0122] In this novel embodiment, the oxide layer includes a portion located along one side of the isolation trench.

[0123] As described in more detail above, some embodiments described herein provide a method. This method includes forming an optical modulator structure in a semiconductor layer above a first dielectric layer of a semiconductor photonic device. The method includes forming a second dielectric layer surrounding the optical modulator structure above the first dielectric layer. The method includes forming an etch stop layer above the second dielectric layer and above the optical modulator structure. The method includes forming a first portion of a third dielectric layer above the etch stop layer. The method includes forming a modulator heater structure above the optical modulator structure in the first portion of the third dielectric layer. The method includes forming a second portion of the third dielectric layer and multiple dielectric layers above the first portion of the third dielectric layer and above the modulator heater structure. The method includes forming an isolation trench through the multiple dielectric layers, through the third dielectric layer, and reaching the etch stop layer, wherein, in a top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure, and wherein the isolation trench has a circular top view shape. [View of the semiconductor photonic device.]

[0124] In an embodiment of this novel method, the method further includes: forming an oxide layer on the plurality of dielectric layers, wherein the oxide layer seals the top opening of the isolation trench.

[0125] In an embodiment of this novel method, the method further includes: forming a grating coupler structure adjacent to the optical modulator structure in the semiconductor layer; and forming a grating coupler transmission region through the plurality of dielectric layers, wherein forming the isolation trench includes: forming the isolation trench adjacent to the grating coupler transmission region.

[0126] In an embodiment of this novel invention, forming the isolation trench includes forming the isolation trench such that the distance between the modulator heater structure and the isolation trench is in the range of about 10 micrometers to about 20 micrometers.

[0127] In an embodiment of this novel invention, forming the isolation trench includes performing an acid-based wet etching operation to form the isolation trench.

[0128] In an embodiment of this novel invention, forming the isolation ditch includes forming the isolation ditch such that the width of the isolation ditch is in the range of about 5 micrometers to about 15 micrometers.

[0129] As described in more detail above, some implementations described herein provide semiconductor photonic devices. A semiconductor photonic device includes a substrate. A semiconductor photonic device includes one or more first dielectric layers above the substrate. A semiconductor photonic device includes an etch stop layer above the one or more first dielectric layers. A semiconductor photonic device includes a plurality of second dielectric layers above the etch stop layer. A semiconductor photonic device includes an optical modulator structure in one or more first dielectric layers. A semiconductor photonic device includes a modulator heater structure in one or more of the plurality of second dielectric layers, wherein the modulator heater structure is located above the optical modulator structure. A semiconductor photonic device includes isolation regions in the plurality of second dielectric layers, wherein the isolation regions in the plurality of second dielectric layers are located above the optical modulator structure, wherein the modulator heater structure is included in the isolation regions in the plurality of second dielectric layers. The isolation regions in the plurality of second dielectric layers are isolated from other regions in the plurality of second dielectric layers through isolation trenches, and wherein the isolation regions in the plurality of second dielectric layers have a ring-shaped top view in a top view of the semiconductor photonic device.

[0130] In an embodiment of this novel invention, the isolation trench includes an annular air gap between the plurality of second dielectric layers and the isolation regions of the plurality of second dielectric layers.

[0131] In this novel embodiment, the width of the isolation region of the plurality of second dielectric layers between the modulator heater structure and the isolation trench is included in the range of about 10 micrometers to about 20 micrometers.

[0132] In this novel embodiment, the semiconductor photonic device further includes an oxide layer over the plurality of second dielectric layers, wherein the isolation trench is sealed at the top of the isolation trench by the oxide layer.

[0133] In this novel embodiment, the modulator heater structure is located on the etch stop layer; and the isolation trench terminates at the etch stop layer.

[0134] In this novel embodiment, the distance between the isolation region of the plurality of second dielectric layers and the other regions of the plurality of second dielectric layers is in the range of about 5 micrometers to about 15 micrometers.

[0135] The terms "approximately" and "substantially" can indicate that the value of a given quantity or range varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not intended to be limiting. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0136] As used in this article, "meeting the threshold" can refer to a value greater than, greater than or equal to, less than, less than or equal to, or equal to the threshold, depending on the context.

[0137] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor photonic device, characterized in that, include: Substrate; The substrate has one or more first dielectric layers; Etching stop layer above the one or more first dielectric layers; Multiple second dielectric layers above the etch stop layer; Optical modulator structure in one or more first dielectric layers; A modulator heater structure in one or more of the plurality of second dielectric layers. The modulator heater structure is located above the optical modulator structure; and Isolation trenches passing through the plurality of second dielectric layers, The isolation trench terminates at the etch stop layer, and In the top view of the semiconductor photonic device, the isolation trench surrounds the modulator heater structure.

2. The semiconductor photonic device according to claim 1, characterized in that, The modulator heater structure is located on the top surface of the etching stop layer.

3. The semiconductor photonic device according to claim 1, characterized in that, The isolation trench has a ring shape in the top view of the semiconductor photonic device.

4. The semiconductor photonic device according to claim 1, characterized in that, The isolation ditch is filled with gas.

5. The semiconductor photonic device according to claim 1, characterized in that, The distance between the modulator heater structure and the isolation trench is in the range of about 10 micrometers to about 20 micrometers.

6. The semiconductor photonic device according to claim 1, characterized in that, The width of the isolation ditch is in the range of about 5 micrometers to about 15 micrometers.

7. The semiconductor photonic device according to claim 1, characterized in that, Also includes: The oxide layer above the plurality of second dielectric layers, The top of the isolation ditch is sealed by the oxide layer.

8. A semiconductor photonic device, characterized in that, include: Substrate; One or more first dielectric layers on the substrate; Etching stop layer above the one or more first dielectric layers; Multiple second dielectric layers above the etch stop layer; Optical modulator structure in one or more first dielectric layers; A modulator heater structure in one or more of the plurality of second dielectric layers. The modulator heater structure is located above the optical modulator structure; and The isolation regions of the plurality of second dielectric layers The isolation regions of the plurality of second dielectric layers are located above the optical modulator structure. The modulator heater structure is contained within the isolation region of the plurality of second dielectric layers. The isolation regions of the plurality of second dielectric layers are established through isolation trenches, and The isolation regions in the plurality of second dielectric layers have a ring-shaped top view in the semiconductor photonic device.

9. The semiconductor photonic device according to claim 8, characterized in that, The isolation trench includes an annular air gap between the plurality of second dielectric layers and the isolation regions of the plurality of second dielectric layers.

10. The semiconductor photonic device according to claim 8, characterized in that, The modulator heater structure is located on the etch stop layer; and The isolation trench terminates at the etch stop layer.

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