Electronic package and electronic device thereof
By employing an electrical connection structure of conductive bumps and conductive vias in the electronic package, the problem of limited transmission speed in existing optical transmission packaging structures is solved, achieving faster transmission speeds and reduced production costs.
Patent Information
- Application Number
- CN202520012055.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-12-12
- Filing Date
- 2025-01-03
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-01-03
AI Technical Summary
Existing optical transmission packaging structures have limited transmission speeds and cannot meet the future demand for larger amounts of information transmission. Furthermore, existing technologies require significant power, complexity, and cable volume loss.
An electronic package structure is adopted, including a carrier structure, a wiring structure, an electronic structure, a covering layer, and connectors. The electronic structure is electrically connected through conductive bumps and conductive vias, and is fabricated using existing semiconductor packaging processes to directly connect the electronic structure.
It achieves faster transmission speeds while reducing production costs, and eliminates the need to develop special processes or purchase special equipment, thus improving the feasibility of technology implementation.
Smart Images
Figure CN223786531U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, and more particularly to an electronic package and electronic device thereof that can improve transmission speed. Background Technology
[0002] As data networks scale proportionally to meet ever-increasing bandwidth requirements, the drawbacks of using copper as the information channel become increasingly apparent. Signal attenuation and crosstalk caused by radiated electromagnetic energy are major obstacles encountered by designers of such systems. Signal attenuation and crosstalk can be mitigated to some extent through equalization, coding, and shielding, but these techniques require considerable power, complexity, and cable volume losses, offering only modest improvements in coverage and very limited scalability. Optical communication has emerged as the successor to overcome these channel limitations.
[0003] like Figure 1 As shown, the existing optical transmission package (CPC) 1 includes a substrate structure 10, an electronic package 11 disposed on the substrate structure 10, and an optical module 12 disposed on the substrate structure 10. The substrate structure 10 is a printed circuit board. The electronic package 11 has a circuit structure 110, an electronic component 111, and a connection port 112. The circuit structure 110 is disposed on the substrate structure 10 via multiple conductive bumps. The electronic component 111 is an application-specific integrated circuit (ASIC) semiconductor chip disposed on the circuit structure 110. The connection port 112 is disposed on the circuit structure 110 and spaced apart from the electronic component 111. The optical module 12 has a photodiode, a transimpedance amplifier, a laser driver, or a clock restorer, and the optical module 12 is connected to the connection port 112 via a transmission line 13. However, the data transmission speed of the existing optical transmission package 1 is still limited, and it will be insufficient for future large-scale information transmission.
[0004] Therefore, overcoming the various problems of the existing technologies has become an urgent issue for the industry. Utility Model Content
[0005] This application provides an electronic package, comprising: a carrier structure; a wiring structure disposed on the carrier structure; an electronic structure disposed on the wiring structure and including a plurality of first conductive bumps and a plurality of second conductive bumps, wherein the plurality of first conductive bumps are electrically connected to the wiring structure; an overlay layer disposed on the wiring structure and covering the electronic structure, and exposing the plurality of second conductive bumps; and a connector disposed on the overlay layer and electrically connected to the plurality of second conductive bumps.
[0006] The electronic package as claimed in the preceding paragraph, further comprises an electronic body having opposite first and second sides, the first plurality of conductive bumps being formed on the first side, and the second plurality of conductive bumps being formed on the second side.
[0007] The electronic package as claimed in the preceding paragraph, further comprises a plurality of conductive vias formed in the electronic body.
[0008] The electronic package as claimed in the preceding paragraph, wherein the second plurality of conductive bumps are electrically connected to the first plurality of conductive bumps via the plurality of conductive vias.
[0009] The electronic package as claimed in the preceding paragraph, wherein the electronic body is a system-on-chip semiconductor chip.
[0010] The electronic package as claimed in the preceding paragraph, wherein the connector is a connection port for connecting a transmission line.
[0011] The electronic package as claimed in the preceding paragraph, further comprising a wiring structure disposed between the encapsulation layer and the connector.
[0012] The electronic package as claimed in the preceding paragraph, further comprising a wiring structure disposed between the encapsulation layer and the connector.
[0013] The electronic package as claimed in the preceding paragraph, wherein the optical module comprises a photodiode, a transimpedance amplifier, a laser driver, or a clock recovery unit.
[0014] The electronic package as claimed in the preceding paragraph, wherein the electronic structure further comprises an electronic body having opposite first and second sides, the first plurality of conductive bumps being formed on the first side, and the second plurality of conductive bumps being formed on the second side.
[0015] The electronic package as claimed in the preceding paragraph, wherein the electronic body further comprises a plurality of conductive vias formed in the electronic body.
[0016] The electronic package as claimed in the preceding paragraph, wherein the electronic body further comprises a plurality of conductive vias formed in the electronic body.
[0017] The electronic package as claimed in the preceding paragraph, wherein the second plurality of conductive bumps are electrically connected to the first plurality of conductive bumps via the plurality of conductive vias.
[0018] As described above in the manufacturing method of electronic packages, the electronic component is a special application integrated circuit type semiconductor chip.
[0019] As described above in the manufacturing method of electronic packages, the connector is a connection port for connecting transmission lines.
[0020] The aforementioned method for manufacturing electronic packages further includes: after forming the covering layer, first forming a circuit structure on the covering layer, and then placing the connector on the circuit structure.
[0021] In summary, the electronic package, electronic device, and manufacturing method of this application allow the connector to be directly connected to the electronic structure. Compared with the existing structure, the transmission speed is faster, and it can be manufactured using existing semiconductor packaging processes without the need to develop special processes or purchase special equipment, effectively reducing production costs and demonstrating high feasibility of technical implementation. Attached Figure Description
[0022] Figure 1 This is a cross-sectional schematic diagram of an existing optical transmission packaging structure.
[0023] Figures 2A-2H This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.
[0024] Figure 2I for Figure 2H A schematic diagram of an application of the electronic package of this application.
[0025] Figures 3A-3C This is a cross-sectional schematic diagram of another method for manufacturing the electronic package of this application.
[0026] Figure 3D for Figure 3C Another application diagram of the electronic package of this application.
[0027] Figure 4 This is a schematic diagram of the electronic device of this application.
[0028] Explanation of reference numerals in the attached figures
[0029] 1 Optical transmission packaging structure
[0030] 10,61 Substrate Structure
[0031] 11,2,3 Electronic Packages
[0032] 110,31 Line Structure
[0033] 111 Electronic Components
[0034] 112 Connection Port
[0035] 12.62 Optical Modules
[0036] 13,4,63 transmission line
[0037] 2a electronic structure
[0038] 20 electronic body
[0039] 20a, 25a, 27a, 31a first side
[0040] 20b, 25b, 27b, 31b second side
[0041] 200 conductive via
[0042] 21 first conductive bump
[0043] 22 second conductive bump
[0044] 23 conductive line
[0045] 24 wiring structure
[0046] 241, 271, 311 dielectric layer
[0047] 242, 272, 312 line layer
[0048] 25 cladding layer
[0049] 26 conductive element
[0050] 27 carrier structure
[0051] 273 primer
[0052] 28 connecting piece
[0053] 29 electrically conductive body
[0054] 5, 64 joint
[0055] 6 electronic device
[0056] 7 carrier plate
[0057] 71 bonding layer
[0058] 8, 9 carrier
[0059] L cutting path. DETAILED DESCRIPTION
[0060] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is contemplated that the application described herein will be readily susceptible to additional advantages and / or modifications as would be apparent to those having ordinary skill in the art, and the application is intended to cover any and all adaptations and modifications as would be apparent to those having ordinary skill in the art.
[0061] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present specification are merely intended to facilitate the understanding of the content disclosed in the present specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions that can be implemented by the present application, and therefore do not have substantial technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.
[0062] Figures 2A-2H A cross-sectional schematic view of a method of manufacturing an electronic package 2.
[0063] As shown in Figure 2A , an electronic body 20 having opposite first and second sides 20a, 20b is provided, a plurality of electrically conductive vias 200 are formed in the electronic body 20, and a plurality of second electrically conductive bumps 22 are formed on the second side 20b of the electronic body 20 and electrically connected to the plurality of electrically conductive vias 200, wherein the electrically conductive vias 200 are not exposed on the first side 20a of the electronic body 20.
[0064] In the present embodiment, the electronic body 20 is an application-specific integrated circuit (ASIC) type semiconductor chip. The electrically conductive vias 200 can be, for example, through-silicon vias (TSVs). The second electrically conductive bumps 22 can be, for example, metal pillars of copper pillars.
[0065] As shown in Figure 2B , the electronic body 20 is placed on a carrier plate 7 with its second side 20b, and the plurality of second electrically conductive bumps 22 are embedded in a bonding layer 71 on the carrier plate 7. Then, the first side 20a of the electronic body 20 is thinned (e.g., a grinding / etching process is performed), so that the plurality of electrically conductive vias 200 are exposed on the first side 20a of the electronic body 20.
[0066] As shown in Figure 2C , electrically conductive lines 23 are formed on the first side 20a of the electronic body 20, and a plurality of first electrically conductive bumps 21 are formed on the electrically conductive lines 23, so that the plurality of first electrically conductive bumps 21 are electrically connected to the plurality of second electrically conductive bumps 22 via the plurality of electrically conductive vias 200.
[0067] In this embodiment, the plurality of first conductive bumps 21 may include, for example, copper pillars and solder material. The conductive line 23 may include an insulating layer and a redistribution layer (RDL) disposed on the insulating layer. The outermost insulating layer may serve as a solder resist layer, and the outermost redistribution layer (e.g., copper) may be exposed on the solder resist layer to serve as an electrical contact pad (e.g., a μ-pad). An under bump metallurgy (UBM) layer, for example, made of copper, may be formed on the electrical contact pad to facilitate bonding of the plurality of first conductive bumps 21.
[0068] like Figure 2D As shown, remove the support plate 7, and along... Figure 2C The cutting path L shown is used for a single-piece cutting process to obtain an electronic structure 2a.
[0069] like Figure 2E As shown, a carrier 8 is provided, and a wiring structure 24 is formed on the carrier 8, and the electronic structure 2a is disposed on the wiring structure 24. It should be understood that there is no sequential order between the fabrication of the wiring structure 24 and the electronic structure 2a.
[0070] The carrier 8 is, for example, a plate made of semiconductor material (such as silicon or glass). The wiring structure 24 includes a dielectric layer 241 and a circuit layer 242 bonded to the dielectric layer 241. The dielectric layer 241 can be made of, for example, poly(p-diazolebenzene) (PBO), polyimide (PI), prepreg (PP), or other dielectric materials, and the circuit layer 242 and the dielectric layer 241 can be formed using a redistribution layer (RDL) process. The circuit layer 242 can be made of copper. The electronic structure 2a is attached to the circuit layer 242 of the wiring structure 24 via a plurality of first conductive bumps 21, so that the plurality of first conductive bumps 21 are electrically connected to the circuit layer 242.
[0071] like Figure 2F As shown, a covering layer 25 is provided on the wiring structure 24 to cover the electronic structure 2a. It should be understood that a portion of the material of the covering layer 25 and the second conductive bumps 22 can be removed through a leveling process (grinding method) so that the end faces of the plurality of second conductive bumps 22 are exposed and flush with the surface of the covering layer 25.
[0072] In this embodiment, the encapsulation layer 25 has opposite first and second sides 25a and 25b, and is bonded to the wiring structure 24 at the first side 25a, and exposes the end faces of the second conductive bumps 22 at the second side 25b. The encapsulation layer 25 is an insulating material, such as polyimide (PI), dry film, encapsulation glue or molding compound such as epoxy, and can be formed on the wiring structure 24 by liquid compound, lamination or compression molding.
[0073] As shown in FIG. 2A, the electronic structure 2a and the wiring structure 24 are disposed on a carrier 9 via the conductive elements 26, and a bottom glue 273 is filled between the wiring structure 24 and the carrier 9 to encapsulate the conductive elements 26. Then, the carrier 8 is removed to expose the second side 25b of the encapsulation layer 25 and the end faces of the second conductive bumps 22. After that, a connector 28 is disposed on the second side 25b of the encapsulation layer 25, and a plurality of conductive bodies 29 are disposed on the other side of the carrier 9 to obtain the electronic package 2 of the present application, wherein the conductive bodies 29 can be, for example, copper bumps or solder bumps. Figure 2G As shown in FIG. 2A, the electronic structure 2a and the wiring structure 24 are disposed on a carrier 9 via the conductive elements 26, and a bottom glue 273 is filled between the wiring structure 24 and the carrier 9 to encapsulate the conductive elements 26. Then, the carrier 8 is removed to expose the second side 25b of the encapsulation layer 25 and the end faces of the second conductive bumps 22. After that, a connector 28 is disposed on the second side 25b of the encapsulation layer 25, and a plurality of conductive bodies 29 are disposed on the other side of the carrier 9 to obtain the electronic package 2 of the present application, wherein the conductive bodies 29 can be, for example, copper bumps or solder bumps.
[0074] As shown in FIG. 2A, the electronic structure 2a and the wiring structure 24 are disposed on a carrier 9 via the conductive elements 26, and a bottom glue 273 is filled between the wiring structure 24 and the carrier 9 to encapsulate the conductive elements 26. Then, the carrier 8 is removed to expose the second side 25b of the encapsulation layer 25 and the end faces of the second conductive bumps 22. After that, a connector 28 is disposed on the second side 25b of the encapsulation layer 25, and a plurality of conductive bodies 29 are disposed on the other side of the carrier 9 to obtain the electronic package 2 of the present application, wherein the conductive bodies 29 can be, for example, copper bumps or solder bumps.
[0075] As shown in FIG. 2A, the electronic structure 2a and the wiring structure 24 are disposed on a carrier 9 via the conductive elements 26, and a bottom glue 273 is filled between the wiring structure 24 and the carrier 9 to encapsulate the conductive elements 26. Then, the carrier 8 is removed to expose the second side 25b of the encapsulation layer 25 and the end faces of the second conductive bumps 22. After that, a connector 28 is disposed on the second side 25b of the encapsulation layer 25, and a plurality of conductive bodies 29 are disposed on the other side of the carrier 9 to obtain the electronic package 2 of the present application, wherein the conductive bodies 29 can be, for example, copper bumps or solder bumps. Figure 2H As shown in FIG. 2A, the electronic structure 2a and the wiring structure 24 are disposed on a carrier 9 via the conductive elements 26, and a bottom glue 273 is filled between the wiring structure 24 and the carrier 9 to encapsulate the conductive elements 26. Then, the carrier 8 is removed to expose the second side 25b of the encapsulation layer 25 and the end faces of the second conductive bumps 22. After that, a connector 28 is disposed on the second side 25b of the encapsulation layer 25, and a plurality of conductive bodies 29 are disposed on the other side of the carrier 9 to obtain the electronic package 2 of the present application, wherein the conductive bodies 29 can be, for example, copper bumps or solder bumps.
[0076] In this embodiment, the carrier structure 27 has opposite first and second sides 27a, 27b. The plurality of conductive elements 26 is disposed on the first side 27a of the carrier structure 27, and the plurality of conductive bodies 29 is disposed on the second side 27b of the carrier structure 27. The carrier structure 27 includes a dielectric layer 271 and a circuit layer 272 coupled to the dielectric layer 271. The dielectric layer 271 is formed of a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or the like. The circuit layer 272 can be formed by a redistribution layer (RDL) process. The circuit layer 272 is electrically connected to the plurality of conductive elements 26 and the plurality of conductive bodies 29. The circuit layer 272 can be formed of copper.
[0077] The connector 28 is electrically connected to the plurality of second conductive bumps 22. The connector 28 can be a connector port for connecting a transmission line, as shown in FIG. 1. Figure 2I The connector 28 can be coupled to a terminal 5 of a transmission line 4, as shown in FIG. 1.
[0078] The present application also provides an electronic package 2 including a carrier structure 27, a wiring structure 24, an electronic structure 2a, a cover layer 25, and a connector 28.
[0079] The carrier structure 27 has opposite first and second sides 27a, 27b. The plurality of conductive bodies 29 is disposed on the second side 27b of the carrier structure 27. The carrier structure 27 includes a dielectric layer 271 and a circuit layer 272 coupled to the dielectric layer 271. The circuit layer 272 is electrically connected to the plurality of conductive bodies 29.
[0080] The wiring structure 24 is disposed on the first side 27a of the carrier structure 27 via the plurality of conductive elements 26. An underfill 273 is disposed between the wiring structure 24 and the carrier structure 27 to encapsulate the plurality of conductive elements 26. The wiring structure 24 includes a dielectric layer 241 and a circuit layer 242 coupled to the dielectric layer 241. The plurality of conductive elements 26 is electrically connected to the circuit layers 242, 272.
[0081] The electronic structure 2a is disposed on the wiring structure 24. In this embodiment, the electronic structure 2a includes an electronic body 20, a plurality of first conductive bumps 21, a plurality of second conductive bumps 22, and a conductive circuit 23.
[0082] The electronic body 20 has opposite first and second sides 20a and 20b, and a plurality of conductive vias 200 are formed in the electronic body 20 to communicate the first and second sides 20a and 20b. A plurality of second conductive bumps 22 are formed on the second side 20b of the electronic body 20 and are electrically connected to the plurality of conductive vias 200. A conductive line 23 is formed on the first side 20a of the electronic body 20, and a plurality of first conductive bumps 21 are formed on the conductive line 23 so that the plurality of first conductive bumps 21 are electrically connected to the plurality of second conductive bumps 22 via the plurality of conductive vias 200, and the electronic structure 2a is mounted on a line layer 242 of the wiring structure 24 through the plurality of first conductive bumps 21 so that the plurality of first conductive bumps 21 are electrically connected to the line layer 242.
[0083] In one embodiment, the electronic body 20 is a special application integrated circuit type semiconductor chip.
[0084] In one embodiment, the conductive line 23 can include an insulating layer and a redistribution layer (RDL) disposed on the insulating layer, wherein the outermost insulating layer can serve as a solder mask layer, and the outermost redistribution layer (e.g., copper) can be exposed to the solder mask layer to serve as an electrical contact pad (e.g., μ-pad), and a UBM (Under Bump Metallurgy) layer (e.g., copper) can be formed on the electrical contact pad to facilitate bonding of the plurality of first conductive bumps 21.
[0085] The encapsulation layer 25 has opposite first and second sides 25a and 25b, and is bonded to the wiring structure 24 at the first side 25a to encapsulate the electronic structure 2a and expose the end surfaces of the plurality of second conductive bumps 22 flush with the second side 25b of the encapsulation layer 25.
[0086] The connecting member 28 is disposed on the second side 25b of the encapsulation layer 25 and is electrically connected to the plurality of second conductive bumps 22. In one embodiment, the connecting member 28 is a connecting port for connecting a transmission line.
[0087] Figures 3A-3C A cross-sectional view of a method of manufacturing the electronic package 3 of the present application is shown, wherein the electronic structure 2a is manufactured in the same manner as in the foregoing embodiments, and the difference between the present embodiment and the foregoing embodiments is only in the wiring structure 31. Only the difference will be described below, and the same technical content will not be described again.
[0088] As shown in FIG. 4, after the foregoing processes, a wiring structure 31 is formed on the second side 25b of the encapsulation layer 25. Figure 3A Figure 2F
[0089] In this embodiment, the circuit structure 31 has opposite first and second sides 31a and 31b, and the circuit structure 31 is disposed on the second side 25b of the cover layer 25 with the first side 31a thereof. The circuit structure 31 includes a dielectric layer 311 and a circuit layer 312 combined with the dielectric layer 311. The material forming the dielectric layer 311 is, for example, a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or the like, and the circuit layer 312 and the dielectric layer 311 can be formed by a redistribution layer (RDL) process. The material forming the circuit layer 312 can be copper, and the plurality of second conductive bumps 22 are electrically connected to the circuit layer 312 exposed on the first side 31a. It should be understood that the number of layers of the dielectric layer 311 and the circuit layer 312 can be designed according to requirements.
[0090] As shown in Figure 3B , the second side 31b of the circuit structure 31 is combined with another carrier 9, and the carrier 8 is removed to expose the wiring structure 24. Then, a plurality of conductive elements 26 are formed on the wiring structure 24 to electrically connect the plurality of conductive elements 26 to the circuit layer 242 of the wiring structure 24.
[0091] As shown in Figure 3C , the electronic structure 2a, the wiring structure 24, and the circuit structure 31 are disposed on a carrier structure 27 through the plurality of conductive elements 26, and then the carrier 9 is removed to expose the second side 31b of the circuit structure 31. Then, a connector 28 is disposed on the second side 31b of the circuit structure 31, and a plurality of conductive bodies 29 are disposed on the carrier structure 27 to obtain the electronic package 3 of the present application, wherein the connector 28 is electrically connected to the circuit layer 312 of the circuit structure 31.
[0092] In an embodiment, the connector 28 can be, for example, a connector for connecting a transmission line, as shown in Figure 3D , the connector 28 can be coupled to a terminal 5 at the end of a transmission line 4.
[0093] The present application also provides an electronic package 3, which includes a carrier structure 27, a wiring structure 24, an electronic structure 2a, a cover layer 25, a circuit structure 31, and a connector 28.
[0094] The carrier structure 27 has opposite first and second sides 27a and 27b, and the plurality of conductive bodies 29 are disposed on the second side 27b of the carrier structure 27. The carrier structure 27 includes a dielectric layer 271 and a circuit layer 272 combined with the dielectric layer 271, and the circuit layer 272 can be electrically connected to the plurality of conductive bodies 29.
[0095] A wiring structure 24 is disposed on a first side 27a of a carrier structure 27 via multiple conductive elements 26, and an adhesive 273 is disposed between the wiring structure 24 and the carrier structure 27 to cover the multiple conductive elements 26. The wiring structure 24 includes a dielectric layer 241 and a circuit layer 242 bonded to the dielectric layer 241. The multiple conductive elements 26 are electrically connected to the circuit layers 242 and 272.
[0096] The electronic structure 2a is disposed on the wiring structure 24. In this embodiment, the electronic structure 2a includes an electronic body 20, a plurality of first conductive bumps 21, a plurality of second conductive bumps 22, and a conductive line 23.
[0097] The electronic body 20 has opposing first sides 20a and second sides 20b, and a plurality of conductive vias 200 are formed within the electronic body 20, connecting the first side 20a and the second side 20b. A plurality of second conductive bumps 22 are formed on the second side 20b of the electronic body 20 and are electrically connected to the plurality of conductive vias 200. A conductive line 23 is formed on the first side 20a of the electronic body 20, and a plurality of first conductive bumps 21 are formed on the conductive line 23, so that the plurality of first conductive bumps 21 are electrically connected to the plurality of second conductive bumps 22 through the plurality of conductive vias 200, and the electronic structure 2a is connected to the wiring layer 242 of the wiring structure 24 through the plurality of first conductive bumps 21, so that the plurality of first conductive bumps 21 are electrically connected to the wiring layer 242.
[0098] In one embodiment, the electronic body 20 is an application-specific integrated circuit type semiconductor chip.
[0099] In one embodiment, the conductive line 23 may include an insulating layer and a redistribution layer (RDL) disposed on the insulating layer. The outermost insulating layer may serve as a solder resist layer, and the outermost redistribution layer (e.g., copper) may be exposed on the solder resist layer to serve as an electrical contact pad (e.g., a μ-pad). An under bump metallurgy (UBM) layer, for example, made of copper, may be formed on the electrical contact pad to facilitate the bonding of the plurality of first conductive bumps 21.
[0100] The cladding layer 25 has a first side 25a and a second side 25b, and is attached to the wiring structure 24 with the first side 25a to cover the electronic structure 2a, and exposes the end faces of a plurality of second conductive bumps 22 and flush with the second side 25b of the cladding layer 25.
[0101] The circuit structure 31 has a first side 31a and a second side 31b, and the circuit structure 31 is disposed on the second side 25b of the covering layer 25 with its first side 31a. The circuit structure 31 includes a dielectric layer 311 and a circuit layer 312 bonded to the dielectric layer 311, and the plurality of second conductive bumps 22 are electrically connected to the circuit layer 312 exposed on the first side 31a.
[0102] The connector 28 is disposed on the second side 31b of the circuit structure 31 to electrically connect the circuit layer 312 and the plurality of second conductive bumps 22. In one embodiment, the connector 28 is a connection port for connecting a transmission line.
[0103] Figure 4 This is a schematic diagram of the electronic device 6 of this application, which is used to install the aforementioned electronic packages 2 and 3.
[0104] Taking electronic package 2 as an example, such as Figure 4 As shown, the electronic device 6 includes a substrate structure 61, an optical module 62, and an electronic package 2. The electronic package 2 is disposed on the substrate structure 61 via a plurality of conductors 29. The optical module 62 is disposed on the substrate structure 61 and spaced apart from the electronic package 2. The connector 28 of the electronic package 2 can be coupled to the connector 64 at the end of a transmission line 63 to connect to the optical module 62.
[0105] In one embodiment, the substrate structure 61 may be, for example, a package substrate with a core layer and a circuit layer, a coreless circuit structure, or a printed circuit board (PCB).
[0106] In one embodiment, the optical module 62 includes a photodiode (PD), a transimpedance amplifier (TIA), a laser diode device (LDD), or a clock and data recovery (CDR).
[0107] In summary, the electronic package, electronic device, and manufacturing method of this application allow the connector to be directly connected to the electronic structure. Compared with the existing structure, the transmission speed is faster, and it can be manufactured using existing semiconductor packaging processes without the need to develop special processes or purchase special equipment, effectively reducing production costs and demonstrating high feasibility of technical implementation.
[0108] The above embodiments are illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: Load-bearing structure; The wiring structure is located on the supporting structure; An electronic structure is disposed on the wiring structure and includes a plurality of first conductive bumps and a plurality of second conductive bumps, wherein the plurality of first conductive bumps are electrically connected to the wiring structure; A covering layer is disposed on the wiring structure and covers the electronic structure, and exposes the plurality of second conductive bumps; and A connector is disposed on the covering layer and electrically connected to the plurality of second conductive bumps.
2. The electronic package as described in claim 1, characterized in that, The electronic structure further includes an electronic body having opposing first and second sides, with a plurality of first conductive bumps formed on the first side and a plurality of second conductive bumps formed on the second side.
3. The electronic package as described in claim 2, characterized in that, Multiple conductive perforations are formed within the electronic body.
4. The electronic package as described in claim 3, characterized in that, The plurality of second conductive bumps are electrically connected to the plurality of first conductive bumps via the plurality of conductive perforations.
5. The electronic package as described in claim 2, characterized in that, The electronic component is a special application integrated circuit type semiconductor chip.
6. The electronic package as claimed in claim 1, characterized in that, This connector is a connection port for connecting transmission lines.
7. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes a circuit structure disposed between the cover layer and the connector.
8. An electronic device, characterized in that, include: Substrate structure; The electronic package as described in any one of claims 1 to 7 is disposed on the substrate structure; as well as An optical module is disposed on the substrate structure and electrically connected to the connector via a transmission line.
9. The electronic device as claimed in claim 8, characterized in that, The optical module includes a photodiode, a transimpedance amplifier, a laser driver, or a clock restorer.