VCSEL chip
By designing curved morphology on the surface of VCSEL chips and forming hyperbolic paraboloids using multilayer photoresist etching, the performance problems caused by lattice mismatch and thermal stress are solved, stress balance is achieved, and the stability and performance of the chips are improved.
Patent Information
- Application Number
- CN202423320988.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing VCSEL chips suffer from severe mismatch stress and thermal stress due to differences in lattice constants and thermal expansion coefficients between multilayers, which affects high-speed communication performance.
By designing curved morphology on the surface of VCSEL chips, a hyperbolic paraboloid is formed by multi-layer photoresist etching to absorb tensile and compressive stresses and achieve stress balance. Specific etching processes and photoresist designs are used to control stress release.
Effectively control high-temperature thermal stress deformation, improve device performance and quality, achieve stress balance, and enhance chip stability.
Smart Images
Figure CN223809427U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a VCSEL chip. BACKGROUND
[0002] VCSEL (Vertical-Cavity Surface-Emitting Laser) components are widely used, for example, high-speed VCSEL components for server rooms, but they need to pass high-temperature and high-current reliability verification.
[0003] Since VCSEL is combined by multiple pairs of DBR (Distributed Bragg Reflector), the reflectivity reaches more than 99%. Therefore, the lattice constants and thermal expansion coefficients of each layer are different, which will produce very serious mismatch stress and thermal stress, affecting the high-speed communication VCSEL. CONTENT OF THE INVENTION
[0004] The purpose of the embodiment of the present application is to provide a VCSEL chip which can effectively absorb both tensile and compressive stresses and achieve stress balance, thereby improving the performance and quality of the device.
[0005] In one aspect of the embodiment of the present application, a VCSEL chip is provided, which comprises, from bottom to top, a substrate, an N-type distributed Bragg reflector, a multi-quantum well layer, a P-type distributed Bragg reflector, and a current contact layer, wherein the surface of the current contact layer is a curved surface.
[0006] Optionally, the curved surface comprises at least a hyperbolic paraboloid.
[0007] Optionally, the curved surface is formed by etching a plurality of layers of photoresist.
[0008] Optionally, the thickness of the plurality of layers of photoresist is different along the stacking direction.
[0009] Optionally, the number of layers of the plurality of layers of photoresist is not more than three.
[0010] Optionally, the thickness of the current contact layer along the stacking direction is λ / 8-λ / 4, and λ is the wavelength of the light incident on the VCSEL chip.
[0011] Optionally, the current contact layer comprises a P-type contact region and an N-type contact region, the P-type contact region is an annular region, current is injected into the light emitting hole at the center of the annular region through the periphery of the annular region, and the N-type contact region encloses the P-type contact region.
[0012] Optionally, a P-type electrode is formed outside the P-type contact region, the P-type electrode is a ring electrode, and a plurality of channels are formed between the P-type electrode and the P-type contact region for injecting current.
[0013] Optionally, the curved surface is located in the P-type electrode and is arranged annularly along the P-type electrode.
[0014] Optionally, the P-type contact region is connected with the P-type distributed Bragg reflector, and the N-type contact region is connected with the N-type distributed Bragg reflector.
[0015] The VCSEL chip provided by the embodiment of the present application is designed by a curved surface on the surface topography of the VCSEL chip to resist stress generated by heat accumulation. The design can effectively control the deformation of the VCSEL chip caused by high-temperature thermal stress, absorb both tensile and compressive stress, and achieve stress balance, so that the surface topography of the VCSEL chip achieves high stress release, thereby improving the performance quality of the device. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0017] Figure 1 is a schematic diagram of the VCSEL chip structure provided by the embodiment of the present application;
[0018] Figure 2 is a schematic diagram of the stress of the curved surface of the current contact layer of the VCSEL chip provided by the embodiment of the present application;
[0019] Figures 3-5 is a schematic diagram of the manufacturing process of the VCSEL chip provided by the embodiment of the present application;
[0020] Figure 6 is a top view of the current injection of Figure 1 .
[0021] Figure: 100 - substrate; 101 - N-type distributed Bragg reflector; 102 - multi-quantum well layer; 103 - P-type distributed Bragg reflector; 104 - current contact layer; 104a - curved surface; 104b - photoresist; 1041 - N-type contact region; 1042 - N-type electrode; 1043 - P-type electrode; 1044 - P-type contact region; 1045 - channel; 1046 - light emitting hole; D - stacking direction. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be described clearly and completely in the description of the present application in combination with the drawings in the embodiments of the present application.
[0023] In the description of the present application, it should be noted that the positions or location relationships indicated by the terms "inner", "outer" and the like are based on the positions or location relationships shown in the drawings or the positions or location relationships in which the products of the present application are usually placed, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements must have a particular position, be constructed and operated in a particular position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only used for differentiation in description and cannot be understood as indicating or implying relative importance.
[0024] It should also be noted that, unless otherwise explicitly specified and limited, the terms "provided", "connected" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be directly connected, or indirectly connected through an intermediate medium; can be connected inside two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.
[0025] Please refer to Figure 1 The VCSEL chip provided by the embodiments of the present application includes: a substrate 100, an N-type distributed Bragg reflector 101, a multi-quantum well layer 102, a P-type distributed Bragg reflector 103 and a current contact layer 104 which are stacked from bottom to top. The surface of the current contact layer 104 is a curved surface 104a.
[0026] The substrate 100, the N-type distributed Bragg reflector 101, the multi-quantum well layer 102, the P-type distributed Bragg reflector 103 and the current contact layer 104 are sequentially stacked to form Figure 1 The VCSEL chip shown in the figure.
[0027] Among them, the surface of the current contact layer 104 in the uppermost layer is a curved surface 104a. The curved surface 104a has an absorbing effect on the stress of the center and both sides of the VCSEL chip, and can effectively withstand pulling and extrusion, forming a balance between pressure and tension, as Figure 2 The curved surface 104a of the present application is a hyperbolic paraboloid, as
[0028] In some embodiments, the curved surface 104a is formed by etching a plurality of photoresists 104b. Specifically, as Figure 3As shown, during epitaxial growth, the thickness of the current contact layer 104 along the stacking direction D needs to be increased to facilitate etching, thus preventing damage to the current contact layer 104. For example, the thickness of the current contact layer 104 along the stacking direction D is λ / 8 to λ / 4, where λ is the wavelength of the light incident on the VCSEL chip.
[0029] like Figure 4 As shown, the photoresist is manufactured using multiple layers of photoresist 104b. Each layer of photoresist 104b is rotated at different speeds to create differences in the thickness of the photoresist 104b in the stacking direction D. Different baking temperatures and times are used, for example, the temperature range of AZ4000 series photoresist 104b is 90℃~150℃, and the baking time is 10min~25min, so that the photoresist 104b produces a curved surface 104a shape. The curvature of the curved surface 104a can be calculated based on the baking temperature and time.
[0030] For example Figure 5 As shown, a plasma etching machine is used to etch the current contact layer 104 and the multilayer photoresist 104b on its surface, increasing the amount of etching nitrogen gas. For example, the etching gas can be 20 sccm~30 sccm of SiCl4 or 10 sccm~30 sccm of N2 to achieve control of the curved surface 104a at the edge, cleaning the photoresist 104b and etching the morphology on the VCSEL surface. It should be noted that, in addition to etching the multilayer photoresist 104b to form the curved surface 104a, the areas of the current contact layer 104 other than the photoresist 104b are also etched as needed to obtain the desired morphology.
[0031] As can be seen, the multilayer photoresist 104b of the current contact layer 104 in this application is used to manufacture the surface morphology of the curved surface 104a. It is baked into a hyperbolic paraboloid design and then etched to obtain the current contact layer 104 with the surface of the curved surface 104a.
[0032] Photoresist 104b, also known as photoresist, is a photosensitive material used in many industrial processes. For example, it is used in photolithography to create a patterned coating on the surface of a material.
[0033] There are two types of 104b photoresist: positive and negative. Positive 104b photoresist dissolves in the developer when exposed to light, while the unexposed parts do not. Negative 104b photoresist also dissolves in the developer when exposed to light, while the unexposed parts do. 104b photoresist is typically used in the ultraviolet (UV) range or shorter wavelengths.
[0034] The resulting photoresist process, also known as photolithography, is a technique that uses optical and chemical principles to precisely fabricate tiny patterns on silicon wafers. Specifically, the photoresist process involves shining light through a mask onto a silicon wafer coated with photoresist, and then using chemical methods to remove or retain the photoresist in the irradiated areas, thereby forming the desired pattern on the silicon wafer. The curved surface 104a of the current contact layer 104 in this application is obtained using the photoresist process.
[0035] Therefore, the VCSEL chip provided in this application embodiment uses a curved surface 104a design on the VCSEL chip surface to counteract the stress generated by thermal accumulation. A hyperbolic paraboloid surface is designed by stacking multiple layers of photoresist 104b, and then etched using ICP while controlling the amount of nitrogen gas to complete the surface morphology design of the curved surface 104a. This design can effectively control the deformation of the VCSEL chip caused by high-temperature thermal stress, absorb both tensile and compressive stresses, and achieve stress balance, so that the VCSEL chip surface morphology achieves high stress release, thereby improving the performance quality of the device.
[0036] It is important to note that, firstly, the number of multilayer 104b photoresist layers should not exceed three, otherwise delamination will occur. Therefore, controlling the thickness and radius of curvature of three-layer 104b photoresist layers is very difficult. This application utilizes the temperature and baking time of the AZ4000 series to control the thickness of the 104b photoresist.
[0037] Secondly, etching requires precise adjustment of gas flow rate and pressure control, and calculation of the load effect caused by the thickness difference between the middle and edge of the photoresist 104b, in order to achieve the hyperbolic paraboloid design. The etching load effect and the ratio of photoresist 104b thickness to the etching area can be calculated. For example, the larger the etching area, the slower the etching rate, and vice versa; when the N2 flow rate is high, the etching speed is slow, and vice versa.
[0038] Finally, the epitaxial design requires thickening the current contact layer 104. For example, the thickness of the current contact layer 104 along the stacking direction D in this application is λ / 8 to λ / 4, and the current path needs to be calculated to prevent current shunting from causing abnormal characteristics. Therefore, the thickness of the current contact layer 104 needs to be calculated through simulation.
[0039] like Figure 6 As shown, the current contact layer 104 forms a current contact area, which includes a P-type contact area 1044 and an N-type contact area 1041. The P-type contact area 1044 is connected to a P-type distributed Bragg reflector, and the N-type contact area 1041 is connected to an N-type distributed Bragg reflector.
[0040] The P-type contact region 1044 is a ring region, and a light emitting hole 1046 is located in the center of the ring region. The current is injected into the light emitting hole 1046 in the center of the ring region through the periphery of the ring region. The N-type contact region 1041 is arranged along the edge of the current injection layer 104, and the N-type contact region 1041 encloses the P-type contact region 1044.
[0041] The P-type electrode 1043 is formed outside the P-type contact region 1044, and the N-type electrode 1042 is formed on the N-type contact region 1041. The P-type electrode 1043 is a ring electrode, and a plurality of channels 1045 are formed between the P-type electrode 1043 and the P-type contact region 1044 for injecting current.
[0042] The present application Figure 6 In an example, four channels 1045 are arranged along the ring circumference, and the current can be injected through the four channels 1045 to obtain stable current injection characteristics.
[0043] The curved surface 104a is located in the P-type electrode 1043 and is arranged in a ring shape along the P-type electrode 1043.
[0044] The above only describes the embodiments of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A VCSEL chip, characterized by, The application relates to a vertical cavity surface emitting laser (VCSEL) chip. The VCSEL chip comprises a substrate, an N-type distributed Bragg reflector, a multi-quantum well layer, a P-type distributed Bragg reflector and a current contact layer, which are stacked from bottom to top, and the surface of the current contact layer is a curved surface.
2. The VCSEL chip of claim 1, wherein, The curved surface comprises at least a hyperbolic paraboloid.
3. The VCSEL chip of claim 1, wherein, The curved surface is formed by etching a plurality of layers of photoresist.
4. The VCSEL chip of claim 3, wherein, The thickness of the plurality of layers of photoresist is different along the stacking direction.
5. The VCSEL chip of claim 3, wherein, The number of layers of the plurality of layers of photoresist is not more than three.
6. The VCSEL chip of claim 1, wherein, The thickness of the current contact layer along the stacking direction is 1 / 8 to 1 / 4 of the wavelength of light incident on the VCSEL chip.
7. The VCSEL chip according to any one of claims 1 to 6, characterized in that, The current contact layer comprises a P-type contact region and an N-type contact region, the P-type contact region is an annular region, current is injected into a light emitting hole in the center of the annular region through the periphery of the annular region, and the N-type contact region encloses the P-type contact region.
8. The VCSEL chip of claim 7, wherein, A P-type electrode is formed outside the P-type contact region, the P-type electrode is an annular electrode, a plurality of annularly distributed channels are formed between the P-type electrode and the P-type contact region for injecting current.
9. The VCSEL chip of claim 8, wherein, The curved surface is located in the P-type electrode and is annularly arranged along the P-type electrode.
10. The VCSEL chip of claim 7, wherein, The P-type contact region is connected with the P-type distributed Bragg reflector, and the N-type contact region is connected with the N-type distributed Bragg reflector.