Field effect transistor circuit

Abstract

The utility model provides a field effect transistor circuit comprising a field effect transistor to be detected, which comprises a grid electrode to be detected, a source electrode to be detected and a leak electrode to be detected; each connecting field effect transistor comprises a connecting grid electrode, a connecting source electrode and a connecting drain electrode; wherein the to-be-detected drain electrode is electrically connected with the plurality of connecting drain electrodes to form a drain electrode current measuring end; the plurality of connecting grids are electrically connected with the plurality of connecting sources, the plurality of connecting grids, the to-be-measured grid and the to-be-measured source form an input end of set voltage, and when the plurality of connecting field-effect transistors are in a turn-off state and the to-be-measured field-effect transistors are in different states, the drain current of the to-be-measured field-effect transistors is measured at the measuring end. According to the utility model, a high-precision source measurement unit is not needed, and the measurement precision of the turn-off current of the field effect transistor can be improved under the condition of low cost.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a field-effect transistor circuit. Background Technology

[0002] For circuit simulation model testing of a single field-effect transistor (FET), the typical approach is to measure the FET's transfer characteristic curve to obtain its turn-off data for modeling. However, current techniques for measuring a single FET suffer from limitations due to the extremely small current in its turn-off state, making accurate measurement difficult and affecting modeling accuracy. Even with high-resolution source measurement units (SMUs), the measurement data in the turn-off state still exhibits fluctuations. Therefore, improvements are needed. Utility Model Content

[0003] This invention provides a field-effect transistor circuit to solve the technical problem in the prior art that it is difficult to accurately measure the current of a single field-effect transistor when it is in the off state.

[0004] This utility model provides a field-effect transistor circuit, comprising:

[0005] The field-effect transistor under test includes a gate, a source, and a drain.

[0006] Multiple interconnected field-effect transistors, wherein each interconnected field-effect transistor includes a gate interconnect, a source interconnect, and a drain interconnect;

[0007] The drain to be tested is electrically connected to multiple connected drains to form a measuring terminal for drain current.

[0008] The plurality of connection gates are electrically connected to the plurality of connection sources, and together with the gate under test and the source under test, form an input terminal for a set voltage;

[0009] When multiple connected field-effect transistors are in the off state and the field-effect transistor under test is in different states, the drain current of the field-effect transistor under test is measured at the measurement terminal.

[0010] In one embodiment of this utility model, the voltage of the measuring terminal is set to the operating voltage of the field-effect transistor under test, the input terminal is grounded, and the drain current of the field-effect transistor under test and multiple connected field-effect transistors in the off state is measured at the measuring terminal.

[0011] In one embodiment of this invention, the voltage of the gate to be measured is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. DThe voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. meas The drain current of the field-effect transistor under test in the off state is I. off The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, satisfying:

[0012] V D =V dd V G =V S =V B =0,

[0013] In one embodiment of this utility model, the voltage of the measuring terminal and the gate under test is set to the operating voltage of the field-effect transistor under test, and the source under test, multiple connected gates and multiple connected sources are grounded. At the measuring terminal, the drain current of the field-effect transistor under test in the on state and the multiple connected field-effect transistors in the off state are measured.

[0014] In one embodiment of this invention, the voltage of the gate to be measured is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. meas The drain current of the field-effect transistor under test in the on state is I. on The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, and the drain current of the N-1 connected field-effect transistors is I. d1 I d3 ...I dN ,satisfy:

[0015] V D =V G =V dd V S =V B =0, I on =I meas -(I d1 +I d3 +...+I dN ).

[0016] In one embodiment of this utility model, when I on with I d1 +I d3 +...+I dN The ratio is 10 3 ~106 At that time, then I on =I meas .

[0017] In one embodiment of this utility model, the voltage of the measuring terminal is set to the operating voltage of the field-effect transistor under test, the voltage of the gate under test is set between zero and the operating voltage of the field-effect transistor under test, the source under test, multiple connected gates and multiple connected sources are grounded, and the drain current of the field-effect transistor under test in the state between off and on and the multiple connected field-effect transistors in the off state is measured at the measuring terminal.

[0018] In one embodiment of this invention, the voltage of the gate to be measured is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. meas The drain current of the field-effect transistor under test in the state between off and on is I. d2 The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, and the drain current of the N-1 connected field-effect transistors is I. d1 I d3 ...I dN ,satisfy:

[0019] V D =V dd V G =0~V dd V S =V B =0, I d2 =I meas -(I d1 +I d3 +...+I dN ).

[0020] In one embodiment of this utility model, when (I d1 +I d3 +...+I dN )=(N-1)I off At that time, then I d2 =I meas -(N-1)I off I off This represents the drain current of the field-effect transistor under test in the off state.

[0021] In one embodiment of this invention, the field-effect transistor under test and the plurality of connected field-effect transistors are metal-oxide-semiconductor field-effect transistors.

[0022] The beneficial effects of this utility model are as follows: The field-effect transistor circuit proposed in this utility model can improve the measurement accuracy of the turn-off current of field-effect transistors by simultaneously putting multiple field-effect transistors in the off state and measuring the current after adding the turn-off currents of multiple field-effect transistors. This can be achieved at low cost. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 A single field-effect transistor provided for existing technology.

[0025] Figure 2 The existing technology provides a measurement of the transfer characteristic curve between the gate voltage and the drain current of a single field-effect transistor.

[0026] Figure 3 A parallel circuit of multiple field-effect transistors provided for existing technology.

[0027] Figure 4 This is a field-effect transistor circuit provided in one embodiment of the present invention.

[0028] Explanation of icon numbers

[0029] 100° turn-off current; 200° intermediate current; 300° turn-on current; 400° parallel MOSFET;

[0030] 10. The field-effect transistor under test; 20. Connecting field-effect transistor. Detailed Implementation

[0031] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.

[0034] Please see Figure 4 This invention proposes a field-effect transistor (FET) circuit. FETs are used in switching circuits, amplifier circuits, digital logic circuits, power management circuits, and other fields. This invention improves the FET circuit, enabling accurate measurement of the FET's drain current in the off state. Furthermore, this circuit can also measure the FET's drain current in the on state, as well as the drain current between the off and on states.

[0035] Please see Figures 1 to 4 In this invention, there are two main types of field-effect transistors: junction field-effect transistors (JFETs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). The following description will use metal-oxide-semiconductor field-effect transistors as an example.

[0036] Please see Figure 4 In one embodiment of this utility model, a field-effect transistor (FET) circuit is proposed, including a FET 10 under test (DUT) and connecting FETs 20. The DUT 10 is the object of measurement, and the number of DUTs 10 is one. Because the drain current of the DUT 10 in the off state is too small, the source measurement unit (SMU) has difficulty performing accurate measurements, thus affecting the modeling accuracy. Therefore, the number of connecting FETs 20 is set to multiple. By connecting multiple connecting FETs 20 to the DUT 10, the source measurement unit measures the drain current of the multiple connecting FETs 20 and the DUT 10, thereby improving the measurement accuracy of the source measurement unit.

[0037] In this invention, it is necessary to measure the drain current of the field-effect transistor 10 under test in the off state, the drain current of the field-effect transistor 10 under test in the on state, and the drain current of the field-effect transistor 10 under test between the off and on states. For example... Figure 2 As shown, for the sake of simplification, the drain current of the field-effect transistor 10 under test in the off state can be denoted as the off current 100, the drain current of the field-effect transistor 10 under test in the on state can be denoted as the on current 300, and the drain current of the field-effect transistor under test between the off state and the on state can be denoted as the intermediate current 200.

[0038] Specifically, such as Figure 4 As shown, the field-effect transistor 10 under test includes a gate (G), a source (S), and a drain (D). The field-effect transistor 20 includes connections to the gate (G), source (S), and drain (D). Figure 4 In this design, the base (B) of the field-effect transistor (FET) 10 under test (DUT) and the connected FET 20 is a substrate to prevent leakage. The DUT is electrically connected to multiple connected drains to form a measurement terminal, which is used to measure the drain current of the DUT 10 and the multiple connected FETs 20. Multiple connected gates are electrically connected to multiple connected sources and form an input terminal with the DUT gate and DUT source. This input terminal sets a voltage for the DUT 10 and the multiple connected FETs 20 to put them in an off state, an on state, or a state between off and on. When the multiple connected FETs 20 are in the off state, and the DUT 10 is in the off state, an on state, or a state between off and on, the drain current of the DUT 10 is measured at the measurement terminal, as described below.

[0039] Please see Figure 4 In one embodiment of this invention, the voltage at the measuring terminal is set to the operating voltage of the field-effect transistor under test (FET), that is, the voltage between the drain under test and the multiple connected drains is set to the operating voltage of the FET. The input terminal is grounded, that is, the voltages of the multiple connected gates, the multiple connected sources, the gate under test, and the source under test are set to zero. At the measuring terminal, the drain current of the FET 10 and the multiple connected FETs 20 in the off state is measured.

[0040] Specifically, the voltage of the gate under test is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. measThe drain current of the field-effect transistor 10 under test in the off state is I. off The operating voltage of the field-effect transistor 10 under test is V. dd The number of connected field-effect transistors 20 is N-1, and the drain current of the N-1 connected field-effect transistors 20 is I. d1 I d3 ...I dN ,satisfy:

[0041] V D =V dd V G =V S =V B =0, I d1 +I off +I d3 +...+I dN =I meas ,

[0042] Specifically, when V D =V dd V G =V S When I = 0, the field-effect transistor 10 under test is in the off state, and the drain current I on the drain electrode under test is... off To cut off the current of 100, such as Figure 2 As shown. When V D =V dd V B When I = 0, multiple connected field-effect transistors 20 are in the off state, and the drain current I on the drain is... d1 I d3 ...I dN To cut off the current of 100, such as Figure 2 As shown.

[0043] In existing technologies, such as Figure 1 As shown, when measuring a single field-effect transistor (FET), the current in its off-state is too small, making accurate measurement difficult and affecting modeling accuracy. Even when measuring the FET using a high-precision source measurement unit, the measurement data still fluctuates in its off-state state. In this embodiment, compared to the prior art, since the FET 10 under test and the multiple connected FETs 20 are all in the off-state, and V... D =V dd V G =V S =V B =0, so I d1 I off I d3 ...I dN They are equal. At the measurement end, the source measurement unit measures I...d1 I off I d3 ...I dN The summed currents are measured, thus improving the accuracy of the measurement. The drain current I of the field-effect transistor 10 under test in the off state can be calculated. off ,

[0044] Please see Figure 4 In one embodiment of this invention, the voltage of the measuring terminal and the gate under test is set to the operating voltage of the field-effect transistor 10 under test, that is, the voltage of the drain under test, the multiple connected drains, and the gate under test are set to the operating voltage of the field-effect transistor 10 under test. The source under test, the multiple connected gates, and the multiple connected sources are grounded, that is, the voltage of the multiple connected gates, the multiple connected sources, and the source under test is set to zero. At the measuring terminal, the drain current of the field-effect transistor 10 under test in the on state and the multiple connected field-effect transistors 20 in the off state are measured.

[0045] Specifically, the voltage of the gate under test is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. meas The drain current of the field-effect transistor 10 under test in the on state is I. on The operating voltage of the field-effect transistor 10 under test is V. dd The number of connected field-effect transistors 20 is N-1, and the drain current of the N-1 connected field-effect transistors 20 is I. d1 I d3 ...I dN ,satisfy:

[0046] V D =V G =V dd V S =V B =0, I d1 +I on +I d3 +...+I dN =I meas .

[0047] Specifically, when V D =V G =V dd V S When I = 0, the field-effect transistor 10 under test is in the on state, and the drain current I on the drain electrode under test is... on For a conduction current of 300, such as Figure 2 As shown. When VD =V dd V B When I = 0, multiple connected field-effect transistors 20 are in the off state, and the drain current I on the drain is... d1 I d3 ...I dN To cut off the current of 100, such as Figure 2 As shown.

[0048] Specifically, the ratio of the on-current 300 to the off-current 100 is 10. 3 ~10 6 Between, i.e., I on with I d1 +I d3 +...+I dN The ratio is 10 3 ~10 6 , when I on with I d1 +I d3 +...+I dN When they coexist, I can be d1 +I d3 +...+I dN Ignore it, thus making I on =I meas .

[0049] In existing technologies, such as Figure 3 As shown, multiple parallel field-effect transistors (FETs) 400 are connected in parallel, meaning multiple gates (G), multiple sources (S), multiple drains (D), and multiple substrates (B). When the source measurement unit measures the multiple parallel FETs 400, it measures the sum of the drain currents of the multiple parallel FETs 400, thereby improving the accuracy of the measurement. The drain current of the parallel FETs 400 in the off state can also be calculated. However, as the size of metal-oxide-semiconductor (MOSFET) field-effect transistors decreases, the on-current 300 of the parallel FETs 400 increases, the channel resistance accounts for a smaller proportion in the measurement circuit, and the influence of metal and other parasitic resistances becomes more significant, affecting the measurement results. After connecting multiple parallel FETs 400, the width-to-length ratio (W / L, the ratio of channel width to length) of the multiple parallel FETs 400 is relatively large, resulting in a larger measurement current I at the measurement terminal. meas The self-heating effect is relatively large, and due to the self-heating effect, the parallel field-effect transistor 400 will exhibit self-heating, which can easily reach the measurement limit of the source measurement unit.

[0050] In this embodiment, compared to the prior art, only the field-effect transistor under test 10 is in the on state, while the multiple connected field-effect transistors 20 are in the off state. The drain current I of the field-effect transistor under test 10... on For a conduction current of 300, the drain current I of multiple connected field-effect transistors 20 d1 I d3 ...I dN The shutdown current is 100. At the measurement terminal, the source measurement unit measures I. d1 I on I d3 ...I dN The summed current is measured, and its value is only around 300 ohms of the conduction current, thus avoiding the self-heating effect.

[0051] In addition, due to I on with I d1 +I d3 +...+I dN The ratio is 10 3 ~10 6 Therefore, the measuring current at the measuring end can be considered to be I. meas That is, the drain current I of the field-effect transistor 10 under test in the on state. on .

[0052] Please see Figure 4 In one embodiment of this invention, the voltage at the measuring terminal is set to the operating voltage of the field-effect transistor 10 under test (FET 10). Specifically, the voltages connecting the multiple drains and the gate under test are set to the operating voltage of FET 10, and the voltage of the gate under test is set between zero and the operating voltage of FET 10. The source under test, the multiple gate connections, and the multiple source connections are grounded, meaning the voltages of the multiple gate connections, the multiple source connections, and the source under test are set to zero. At the measuring terminal, the drain current of FET 10 under test in its off-state and on-state, and the drain current of the multiple connected FETs 20 in their off-state, are measured.

[0053] Specifically, the voltage of the gate under test is V. G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between multiple gates and multiple sources is V. B The measuring current at the measuring end is I. meas The drain current of the field-effect transistor 10 under test in the state between off and on is I. d2 The operating voltage of the field-effect transistor 10 under test is V. dd The number of connected field-effect transistors 20 is N-1, and the drain current of the N-1 connected field-effect transistors 20 is I. d1 I d3 ...IdN ,satisfy:

[0054] V D =V dd V G =0~V dd V S =V B =0, I d1 +I d2 +I d3 +...+I dN =I meas .

[0055] Specifically, when V D =V dd V G =0~V dd V S When I = 0, the field-effect transistor 10 under test is in the state between off and on, and the drain current I on the drain electrode under test is... d2 For an intermediate current of 200, such as Figure 2 As shown. When V D =V dd V B When I = 0, multiple connected field-effect transistors 20 are in the off state, and the drain current I on the drain is... d1 I d3 ...I dN To cut off the current of 100, such as Figure 2 As shown.

[0056] Specifically, since multiple connected field-effect transistors 20 are in the off state, the drain current I on the drain is... d1 I d3 ...I dN To cut off the current of 100, we can let (I) d1 +I d3 +...+I dN )=(N-1)I off I off Given the drain current of the field-effect transistor 10 under test in the off state, I can be obtained. d2 =I meas -(N-1)I off .

[0057] In this embodiment, compared to the prior art, only the field-effect transistor under test 10 is in the state between off and on, while multiple connected field-effect transistors 20 are in the off state. The drain current I of the field-effect transistor under test 10... d2 The intermediate current is 200, and the drain current I of multiple connected field-effect transistors 20 is... d1 I d3 ...I dNThe shutdown current is 100. At the measurement terminal, the source measurement unit measures I. d1 I d2 I d3 ...I dN The summed current is measured, and its value is less than the conduction current of 300, thus avoiding the self-heating effect.

[0058] Additionally, due to the drain current I connected to the drain electrode d1 I d3 ...I dN Given a turn-off current of 100, the drain current I of the field-effect transistor 10 under test is... d2 Given an intermediate current of 200, when the drain current I of the field-effect transistor 10 under test is... d2 The drain current I of multiple connected field-effect transistors 20 d1 I d3 ...I dN The ratio exceeds 10 2 When the current at the measuring end is considered to be I, it can be assumed that the current at the measuring end is I. meas That is, the drain current I of the field-effect transistor 10 under test in the state between off and on. d2 .

[0059] In summary, this invention proposes a field-effect transistor (FET) circuit that measures the sum of the turn-off currents of multiple FETs by simultaneously placing them in the off state. This eliminates the need for a high-precision source measurement unit, thereby improving the accuracy of FET turn-off current measurement at low cost. Furthermore, this FET circuit avoids the impact of excessive parasitic resistance in the FETs on the accuracy of on-current measurement and prevents the FETs from self-heating.

[0060] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model. As used herein and throughout the claims below, unless otherwise specified, "a" and "the" include plural references. Similarly, as used herein and throughout the claims below, unless otherwise specified, "in" means "in" and "on".

Claims

1. A field-effect transistor circuit, characterized in that, include: The field-effect transistor under test includes a gate, a source, and a drain. Multiple interconnected field-effect transistors, wherein each interconnected field-effect transistor includes a gate interconnect, a source interconnect, and a drain interconnect; The drain to be tested is electrically connected to multiple connected drains to form a measuring terminal for drain current. The plurality of connection gates are electrically connected to the plurality of connection sources, and together with the gate under test and the source under test, form an input terminal for a set voltage; When multiple connected field-effect transistors are in the off state and the field-effect transistor under test is in different states, the drain current of the field-effect transistor under test is measured at the measurement terminal.

2. The field-effect transistor circuit according to claim 1, characterized in that, The voltage at the measurement terminal is set to the operating voltage of the field-effect transistor under test. The input terminal is grounded. At the measurement terminal, the drain current of the field-effect transistor under test and the plurality of connected field-effect transistors in the off state is measured.

3. The field-effect transistor circuit according to claim 2, characterized in that, The voltage of the gate under test is V G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between the plurality of connected gates and the plurality of connected sources is V. B The measuring current at the measuring terminal is I. meas The drain current of the field-effect transistor under test in the off state is I. off The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, satisfying: V D =V dd ,V G =V S =V B =0, 4. The field-effect transistor circuit according to claim 1, characterized in that, The voltage of the measuring terminal and the gate under test is set to the operating voltage of the field-effect transistor under test. The source under test, the plurality of connected gates and the plurality of connected sources are grounded. At the measuring terminal, the drain current of the field-effect transistor under test in the on state and the plurality of connected field-effect transistors in the off state are measured.

5. The field-effect transistor circuit according to claim 4, characterized in that, The voltage of the gate under test is V G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between the plurality of connected gates and the plurality of connected sources is V. B The measuring current at the measuring terminal is I. meas The drain current of the field-effect transistor under test in the on-state is I. on The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, and the drain current of the N-1 connected field-effect transistors is I. d1 I d3 ...I dN ,satisfy: V D =V G =V dd ,V S =V B =0,I on =I meas -(I d1 +I d3 +...+I dN )。 6. The field-effect transistor circuit according to claim 5, characterized in that, When I on with I d1 +I d3 +...+I dN The ratio is 10 3 ~10 6 At that time, then I on =I meas .

7. The field-effect transistor circuit according to claim 3, characterized in that, The voltage of the gate under test is set between zero and the operating voltage of the field-effect transistor under test. The source under test, the multiple gates connected to the multiple sources connected to the ground are grounded. At the measurement terminal, the drain current of the field-effect transistor under test in the state between off and on, and the drain current of the multiple connected field-effect transistors in the off state are measured.

8. The field-effect transistor circuit according to claim 7, characterized in that, The voltage of the gate under test is V G The voltage of the source electrode to be measured is V. S The voltage at the measuring terminal is V. D The voltage between the plurality of connected gates and the plurality of connected sources is V. B The measuring current at the measuring terminal is I. meas The drain current of the field-effect transistor under test in the state between off and on is I. d2 The operating voltage of the field-effect transistor under test is V. dd The number of connected field-effect transistors is N-1, and the drain current of the N-1 connected field-effect transistors is I. d1 I d3 ...I dN ,satisfy: V D =V dd ,V G =0~V dd ,V S =V B =0,I d2 =I meas -(I d1 +I d3 +...+I dN )。 9. The field-effect transistor circuit according to claim 8, characterized in that, When(I d1 +I d3 +...+I dN )=(N-1)I off At that time, then I d2 =I meas -(N-1)I off I off The drain current of the field-effect transistor under test in the off state is denoted as .

10. The field-effect transistor circuit according to claim 1, characterized in that, The field-effect transistor under test and the plurality of connected field-effect transistors are metal-oxide-semiconductor field-effect transistors.

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