Chip test circuit and chip test board card

Abstract

The embodiment of the utility model provides a chip test circuit and a chip test board card, a first alarm link is designed for a target detection link, voltage value detection is carried out through the first alarm link, and a preset level is transmitted to a test control chip under the condition that the voltage of the target detection link is abnormal. The test control chip is triggered to control the power supply module corresponding to the target detection link to be powered off, the interface circuit transmits the preset level to the processor, the processor is triggered to read and report the alarm information through the interface circuit, and the test control chip can independently control an abnormal power supply channel to be powered off without influencing other normally working power supply channels. According to the chip testing method, the chip testing safety and the chip testing efficiency can be improved, the testing control chip is combined with the architecture of the first alarm link and the processor to carry out anomaly detection and alarm, the response speed of anomaly alarm can be improved, and the complexity and the design and manufacturing cost of the chip testing circuit can be reduced.

Description

Technical Field

[0001] This disclosure relates to automated testing technology, and in particular to a chip test circuit and a chip test board. Background Technology

[0002] Semiconductor automated testing refers to the use of automated test equipment (ATE) to test various parameters of the device under test (DUT). After the finished product testing is completed, customers will also conduct aging tests on chips with normal parameters to eliminate devices that fail due to aging, thereby controlling the quality of semiconductor devices leaving the factory.

[0003] Current chip aging tests typically connect various detection voltages to a microcontroller unit (MCU), using the MCU's analog-to-digital converter (ADC) for voltage detection. When an abnormal voltage occurs in a particular path, the MCU determines the path and type of abnormality, generates an alarm message, and powers down the corresponding power module for that path. Since chip testing is usually performed on large batches of chips, related technologies primarily use an MCU combined with a multiplexer switch to switch paths and poll the voltage of the corresponding path for each chip under test.

[0004] However, directly powering down the power module via the MCU will power down the entire test board, preventing the normally functioning power path from continuing chip testing. Furthermore, since the MCU operates serially, it needs to run other task threads while performing voltage detection. When there is an abnormality in the path or the chip under test, the MCU may not be able to control the power to shut down in time or generate alarm information, which may lead to damage to the chip under test. Utility Model Content

[0005] This disclosure provides a chip testing circuit and a chip testing board, which can improve the security and efficiency of chip testing.

[0006] In one aspect of this disclosure, a chip test circuit is provided, including a control module, a first alarm module, and at least one power module. The control module includes a test control chip and a processor, and the first alarm module includes at least one first alarm link.

[0007] The power module is connected to the power supply terminal of the corresponding pin of the chip under test through a first link and to the detection terminal of the corresponding pin of the chip under test through a second link. The power module is used to supply power to the chip under test.

[0008] The input end of the first alarm link is connected to the target detection link, and the output end of the first alarm link is connected to the test control chip. The first alarm link is used to compare the voltage value of the target detection link with a preset voltage threshold, and send a preset level to the test control chip when the relationship between the voltage value of the target detection link and the preset voltage threshold meets a preset condition. The target detection link includes at least one of the first link and the second link.

[0009] The test control chip is connected to the power module and is used to control the power module corresponding to the target detection link to power down when the preset level is received. Specifically, when the preset level is received from at least two first alarm links, the test control chip is used to control the power module corresponding to the target detection link connected to the at least two first alarm links to power down in parallel.

[0010] The output of the first alarm link is also connected to the processor through an interface circuit. The interface circuit is used to generate an interrupt signal when the preset level is received. The processor is used to read the alarm information through the interface circuit and send the alarm information to the host computer when the interrupt signal is received.

[0011] Optionally, a comparator is provided in the first alarm link. The input terminals of the comparator include a first input terminal and a second input terminal. The first input terminal is connected to at least one of the first link and the second link, and the second input terminal is connected to a digital-to-analog converter. The digital-to-analog converter is used to output voltage according to the preset voltage threshold.

[0012] The output of the comparator is connected to the test control chip. The comparator is used to output the preset level when the relationship between the voltage value at the first input terminal and the voltage value at the second input terminal satisfies the preset condition.

[0013] Optionally, a power sampling resistor is provided in the first link, and each first alarm link includes at least one first alarm sub-link. The first alarm sub-link includes at least one of an overcurrent alarm link, an overvoltage alarm link, an undervoltage alarm link, and an open circuit alarm link. A comparator is provided in the first alarm sub-link.

[0014] The output of the comparator of each first alarm sub-link is connected to the test control chip through an AND gate circuit. The AND gate circuit is used to perform an AND operation on the output level of the first alarm sub-link in the same first alarm link.

[0015] Optionally, the overcurrent alarm link includes a first amplifier and a first comparator. The two input terminals of the first amplifier are respectively connected to the two ends of the power sampling resistor, and the output terminal of the first amplifier is connected to the first input terminal of the first comparator. The first amplifier is used to amplify the voltage of the power sampling resistor.

[0016] The first input terminal of the second comparator in the overvoltage alarm link is connected to the second link;

[0017] The first input of the third comparator in the undervoltage alarm link is connected to the second link;

[0018] The open-circuit alarm link is equipped with a second amplifier and a fourth comparator. The two input terminals of the second amplifier are connected to the second link and the first link, respectively, and the output terminal of the second amplifier is connected to the first input terminal of the fourth comparator. The second amplifier is used to amplify the voltage difference between the second link and the first link.

[0019] Optionally, the chip under test is disposed in an aging test board, and the circuit further includes a second alarm module, the second alarm module including a second alarm link, the second alarm link including at least one of a ground alarm link and an over-temperature alarm link;

[0020] The grounding alarm link includes a third amplifier and a fifth comparator. The two inputs of the third amplifier are connected to the grounding line of the chip test circuit and the grounding line of the aging test board, respectively. The output of the third amplifier is connected to the first input of the fifth comparator. The digital-to-analog converter is connected to the second input of the fifth comparator. The output of the fifth comparator is connected to the test control chip through the AND gate circuit and to the processor through the interface circuit. The third amplifier is used to amplify the grounding voltage difference between the chip test circuit and the aging test board. The fifth comparator is used to output the preset level when the voltage value at the first input of the fifth comparator is greater than the voltage value at the second input of the fifth comparator.

[0021] The over-temperature alarm link includes a sixth comparator. The first input of the sixth comparator is connected to the over-temperature protection circuit of the power supply module. The digital-to-analog converter is connected to the second input of the sixth comparator. The output of the sixth comparator is connected to the test control chip through the AND gate circuit and to the processor through the interface circuit. The sixth comparator is used to output the preset level when the voltage value at the first input of the sixth comparator is greater than the voltage value at the second input of the sixth comparator.

[0022] Optionally, the control module further includes a controller;

[0023] The processor is connected to the host computer via a network and is used to receive and parse the chip test instructions sent by the host computer, and to forward the chip test instructions to the controller. The chip test instructions are used to indicate the power supply voltage corresponding to the chip under test.

[0024] The controller is connected to the pre-amplifier of the power module and is used to control the pre-amplifier to supply power to the power module based on the chip test instructions.

[0025] Optionally, the first link and the second link are connected to at least one chip under test via a gold finger connector.

[0026] Optionally, a first relay switch is provided in the first link. The first relay switch is connected to the gold finger connector. The test control chip is used to control the opening and closing state of each switch channel in the first relay switch. Different switch channels of the first relay switch are used to connect different chips under test.

[0027] Optionally, the second link is equipped with a second relay switch and an analog switch;

[0028] The second relay switch is connected to the gold finger connector, and the processor is used to control the opening and closing state of each switch channel in the second relay switch. Different switch channels of the second relay switch are used to connect to different chips under test.

[0029] The analog switch is connected to the at least one power module. The test control chip is used to control the opening and closing state of the analog switch to select the chip under test for detection feedback voltage measurement, and to adjust the output voltage of the at least one power module according to the measured detection feedback voltage value.

[0030] In another aspect of this disclosure, a chip test board is provided, wherein the chip test board is provided with the chip test circuit described above.

[0031] Based on the embodiments of this disclosure, a first alarm link is designed for the target detection link. Voltage value detection is performed through the first alarm link. When the voltage of the target detection link is abnormal, a preset level is sent to the test control chip, triggering the test control chip to control the power module corresponding to the target detection link to power down. At the same time, the preset level is sent to the processor through the interface circuit, triggering the processor to read the alarm information through the interface circuit and report it. Compared with the protection mechanism of directly controlling the power down of the resource board through the MCU, the test control chip can control the power down of the abnormal power channel independently without affecting other normally operating power channels, which can improve the safety and efficiency of chip testing. Furthermore, using the above architecture to replace the MCU for anomaly detection and alarm, compared with the serial processing method of the MCU, can improve the response speed of anomaly alarms, and eliminates the need to design communication links and peripheral circuits between multiple MCUs, reducing the complexity of chip test circuits and design and manufacturing costs.

[0032] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0033] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0034] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0035] Figure 1 A schematic diagram of the structure of a chip test circuit provided in an exemplary embodiment of this disclosure;

[0036] Figure 2 A schematic diagram of the structure of a first alarm module and a second alarm module provided for an exemplary embodiment of this disclosure;

[0037] Figure 3 A schematic diagram of the structure of a chip test circuit provided in another exemplary embodiment of this disclosure;

[0038] Figure 4 A schematic diagram of the structure of a chip test circuit provided in another exemplary embodiment of this disclosure;

[0039] Figure 5 A schematic diagram of the structure of a first link provided for an exemplary embodiment of this disclosure;

[0040] Figure 6 This is a schematic diagram of the structure of a second link provided for an exemplary embodiment of this disclosure.

[0041] The attached figures are labeled as follows:

[0042] Control module-1; First alarm module-2; Power module-3; First link-4; Second link-5; ADC-6; Soft-start DAC-7; Potentiometer-8; Interface circuit-9; AND gate circuit-10; Digital-to-analog converter-11; Second alarm module-12; Gold finger connector-13;

[0043] Test control chip-101; processor-102; controller-103; first alarm link-201; power sampling resistor-401; first relay switch-402; second relay switch-501; analog switch-502; operational amplifier link-503; instrumentation amplifier link-504; second alarm link-1201;

[0044] First comparator - 201a; Second comparator - 201b; Third comparator - 201c; Fourth comparator - 201d; First amplifier - 201e; Second amplifier - 201f; Fifth comparator - 1201a; Sixth comparator - 1201b; Third amplifier - 1201c. Detailed Implementation

[0045] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0046] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0047] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0048] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0049] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0050] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0051] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0052] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0053] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.

[0054] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0055] Figure 1 This is a structural block diagram of a chip test circuit provided in an exemplary embodiment of this disclosure. For example... Figure 1 As shown, the chip test circuit includes a control module 1, a first alarm module 2, and at least one power module 3. The control module 1 includes a test control chip 101 and a processor 102. The first alarm module 2 includes at least one first alarm link 201. The chip test circuit is installed in a resource board.

[0056] Power module 3 is connected to the power supply terminal of the corresponding pin of the chip under test (DUT) via a first link 4, and to the detection terminal of the corresponding pin of the DUT via a second link 5. Power module 3 is used to supply power to the DUT. Optionally, the DUT is set in a burn-in board (BIB). At least one power module 3 can be connected to the power supply terminal (force terminal) of a corresponding number of DUTs in the BIB board via at least one first link 4, where the first link 4 is the force link; correspondingly, at least one power module 3 can be connected to the detection terminal (sense terminal) of a corresponding number of DUTs in the BIB board via at least one second link 5, where the second link 5 is the sense link.

[0057] The input of the first alarm link 201 is connected to the target detection link, which includes at least one of the first link 4 and the second link 5. The detection target and the specific link connected to the first alarm link 201 differ depending on the alarm type. The output of the first alarm link 201 is connected to the test control chip 101. The first alarm link 201 compares the voltage value of the target detection link with a preset voltage threshold and sends a preset level to the test control chip 101 when the relationship between the voltage value of the target detection link and the preset voltage threshold meets a preset condition. Optionally, the preset condition includes the voltage value of the target detection link being higher than the corresponding preset voltage threshold, or the voltage value of the target detection link being lower than the corresponding preset voltage threshold, etc. The preset conditions and preset voltage thresholds may differ for different alarm types. Illustratively, the preset level is low. Under normal circumstances, the first alarm link 201 sends a high level to the test control chip 101. When an abnormality is detected in the target detection link, it sends a low level to the test control chip 101 to trigger the alarm and protection mechanism of the test control chip 101.

[0058] The test control chip 101 is connected to the power module and is used to control the power module 3 corresponding to the target detection link to power down when a preset level is received. Specifically, when the preset level is received from at least two first alarm links 201, the test control chip 101 is used to control the power modules 3 corresponding to the target detection links connected to at least two first alarm links 201 to power down in parallel. Indicatively, the test control chip 101 can be a Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), etc. This embodiment uses an FPGA as an example. By controlling the power enable, the FPGA can independently control the power-on and power-off of each power module 3. Therefore, when a preset level is received, it can control the power module corresponding to the abnormal link to power down. Furthermore, since the FPGA can process events in parallel, when the preset level is received from at least two first alarm links, the FPGA can control the power modules corresponding to the target detection links connected to at least two first alarm links to power down in parallel. Optionally, the test control chip 101 can also control the soft-start digital-to-analog converter (DAC) 7, potentiometer 8, and output voltage regulator of each power module 3.

[0059] The output of the first alarm link 201 is also connected to the processor 102 via an interface circuit 9. The interface circuit 9 generates an interrupt signal upon receiving a preset level. The processor 102 reads the alarm information through the interface circuit 9 upon receiving the interrupt signal and sends the alarm information to the host computer. Indicatively, the interface circuit 9 can be implemented using an Enhanced Parallel Port (EPP), Input / Output (IO) expansion chip, etc. This embodiment uses an IO expansion chip as an example. The interface circuit 9 has a register that can store alarm information (e.g., the link identifier of the target detection link, the abnormality type, the specific voltage value, etc.) upon receiving a preset level. Simultaneously, the interface circuit 9 sends an interrupt signal to the processor 102. After receiving the interrupt signal, the processor 102 reads the alarm information through the register of the interface circuit 9 and reports it to the host computer. Indicatively, the processor 102 may be a Reduced Instruction Set Computer (RISC), an Advanced RISC Machine (ARM), or a Microprocessor without interlocked pipelined stages (MIPS).

[0060] Based on the embodiments of this disclosure, a first alarm link is designed for the target detection link. Voltage value detection is performed through the first alarm link. When the voltage of the target detection link is abnormal, a preset level is sent to the test control chip, triggering the test control chip to control the power module corresponding to the target detection link to power down. At the same time, the preset level is sent to the processor through the interface circuit, triggering the processor to read the alarm information through the interface circuit and report it. Compared with the protection mechanism of directly controlling the power down of the resource board through the MCU, the test control chip can control the power down of the abnormal power channel independently without affecting other normally operating power channels, which can improve the safety and efficiency of chip testing. Furthermore, using the above architecture to replace the MCU for anomaly detection and alarm, compared with the serial processing method of the MCU, can improve the response speed of anomaly alarms, and eliminates the need to design communication links and peripheral circuits between multiple MCUs, reducing the complexity of chip test circuits and design and manufacturing costs.

[0061] In one possible implementation, such as Figure 2As shown, a comparator is provided in the first alarm link 201. The comparator has a first input terminal and a second input terminal. The first input terminal is connected to at least one of the first link 4 and the second link 5, and the second input terminal is connected to a digital-to-analog converter (DAC) 11. The DAC 11 outputs a voltage according to a preset voltage threshold. The comparator's output terminal is connected to a test control chip 101 and to a processor 102 through an interface circuit 9. The comparator outputs a preset level when the relationship between the voltage value at the first input terminal and the voltage value at the second input terminal meets a preset condition. For example, when the voltage value at the first input terminal is greater than the voltage value at the second input terminal, the comparator outputs a preset level (low level).

[0062] In this embodiment of the present disclosure, by setting a digital-to-analog converter 11 and a comparator in the chip test circuit, the voltage of the target detection link is compared with the voltage output by the digital-to-analog converter 11 by the comparator, so that when the voltage of the target detection link is abnormal, a preset level is automatically triggered to issue an alarm. There is no need to poll and detect the specific voltage values ​​of each first link 4 and second link 5 through the ADC to issue an abnormal alarm, which can improve the speed of abnormal response.

[0063] In one possible implementation, the chip test circuit provided in this disclosure can implement at least one of the following alarm types: overcurrent protection (OCP) alarm, overvoltage protection (OVP) alarm, undervoltage protection (UVP) alarm, and open circuit alarm. Correspondingly, as... Figure 2 As shown, a power sampling resistor 401 is provided in the first link 4. Each first alarm link 201 includes at least one first alarm sub-link. The first alarm sub-link includes at least one of the following: overcurrent alarm link, overvoltage alarm link, undervoltage alarm link, and open circuit alarm link. Each first alarm sub-link is equipped with a comparator. In the same first alarm link 201, the output terminal of the comparator of each first alarm sub-link is connected to the test control chip 101 through the same AND gate circuit 10. The AND gate circuit 10 is used to perform an AND operation on the output levels of all first alarm sub-links in the same first alarm link 201. That is, when at least one first alarm sub-link in the same first alarm link 201 outputs a preset level, the corresponding AND gate circuit 10 also outputs a preset level, triggering the test control chip 101 to power down the power module 3 corresponding to the target detection link detected by the first alarm link 201.

[0064] Optionally, the preset voltage threshold output by the digital-to-analog converter 11 may vary for different first alarm sub-links, and the preset conditions corresponding to the preset levels output by the comparators in different first alarm sub-links may also differ. Technicians can set these conditions according to actual needs. For example, for an overvoltage alarm link, the comparator outputs a preset level when the voltage at the first input terminal is higher than the voltage at the second input terminal; for an undervoltage alarm link, the comparator outputs a preset level when the voltage at the first input terminal is lower than the voltage at the second input terminal.

[0065] Based on the embodiments of this disclosure, a comparator monitors the voltage of the target detection link. If any voltage abnormality occurs, the comparator immediately outputs a preset level. Taking a low preset level as an example, the output of the comparator is connected to the input of the AND gate circuit 10. Therefore, the output of the AND gate circuit 10 immediately becomes low. The test control chip 101 scans the output of the AND gate circuit 10. Once the test control chip 101 detects that the output level of the AND gate circuit 10 changes from high to low, it immediately adopts a power-down strategy, sequentially powering down the corresponding power supply module 3. Because the test control chip 101 is a logic device, it can perform parallel processing in software control. Therefore, if multiple target detection links malfunction, the test control chip 101 can simultaneously control all target detection links and their corresponding power supply modules 3 to power down sequentially, and simultaneously illuminate the alarm lights. Using AND gate circuit 10 instead of MCU to realize voltage detection and alarm of the power channel (i.e. target detection channel) of chip under test, the design cost of chip test circuit is greatly reduced. At the same time, by using hardware AND gate, the risk of software misjudgment can be reduced, the reliability of detection is increased, and the hardware response speed is faster than the software scanning detection response speed, so it can better protect the chip under test.

[0066] When power module 3 supplies power to the chip under test (DUT) on the BIB board, the DUT acts as a load, generating a load current. This load current produces a voltage drop across the power sampling resistor 401 in the first link 4. Since the resistance of the power sampling resistor 401 is in the mΩ range, the resulting voltage drop is typically only a few tens of mV, making it difficult for the comparator to reliably detect the voltage change and trigger an overcurrent alarm. The open-circuit alarm is determined by detecting the voltage difference between the first link 4 and the second link 5 to identify any power supply abnormalities. During chip testing, the connectors may become damaged after multiple insertions and removals of the BIB board, leading to increased impedance and a significant voltage drop. Therefore, open-circuit alarm detection is necessary. Although the voltage drop is small when the connector malfunctions, typically around 200mV, it can be fatal to the DUT, potentially causing it to malfunction or be damaged. Therefore, accurate detection of this voltage difference is required. To address the aforementioned issues, in one possible implementation, an amplifier can be installed in the overcurrent alarm link and the open circuit alarm link. The input of the amplifier is connected to the target detection link, and the output of the amplifier is connected to the first input of the comparator. This allows the voltage under test to be amplified by the amplifier, and the comparator to accurately and quickly detect voltage changes.

[0067] Optionally, the overcurrent alarm link includes a first amplifier 201e (i.e., the amplifier in the overcurrent alarm link) and a first comparator 201a (i.e., the comparator in the overcurrent alarm link). The two input terminals of the first amplifier 201e are respectively connected to the two ends of the power sampling resistor 401, and the output terminal of the first amplifier 201e is connected to the first input terminal of the first comparator 201a. The first amplifier 201e is used to amplify the voltage of the power sampling resistor 401. When the voltage across the power sampling resistor 401 exceeds the preset voltage threshold of the digital-to-analog converter 11 for overcurrent alarm output, the first comparator 201a outputs a preset level to the AND gate circuit 10, and the AND gate circuit 10 outputs a corresponding preset level to the test control chip 101. This triggers the test control chip 101 to power down the power module 3 corresponding to the target detection link detected by the first alarm link. Simultaneously, the preset level output by the first comparator 201a triggers the corresponding interface circuit 9 to generate an interrupt signal, which in turn triggers the processor 102 to obtain alarm information by reading the interface circuit 9 connected to the corresponding port of the interrupt signal. The processor 102 determines the abnormal target detection link and its abnormality type based on the alarm information, and can control the ADC 6 ( Figure 1 The voltage of the abnormal target detection link is measured to obtain the specific voltage value, and the alarm information is written and reported to the host computer.

[0068] In the overvoltage alarm link, the first input of the second comparator 201b (i.e., the comparator in the overvoltage alarm link) is connected to the second link. In the undervoltage alarm link, the first input of the third comparator 201c (i.e., the comparator in the undervoltage alarm link) is connected to the second link 5. Overvoltage and undervoltage alarms detect the remote sense voltage. When an anomaly occurs (e.g., the voltage at the first input of the second comparator 201b is higher than the voltage at the second input of the second comparator 201b / the voltage at the first input of the third comparator 201c is lower than the voltage at the second input of the third comparator 201c), the second comparator 201b / third comparator 201c outputs a preset level (low level) to the AND gate circuit 10 and the interface circuit 9, thereby triggering the test control chip 101 and the processor 102 to perform corresponding abnormal alarm processing.

[0069] The open-circuit alarm link includes a second amplifier 201f (i.e., the amplifier in the open-circuit alarm link). The two inputs of the second amplifier 201f are connected to the second link and the first link, respectively. The output of the second amplifier 201f is connected to the first input of the fourth comparator 201d (i.e., the comparator in the open-circuit alarm link). The second amplifier 201f amplifies the voltage difference between the second link 5 and the first link 4. The open-circuit alarm determines whether there is a power supply abnormality by detecting the voltage difference between the first link 4 and the second link 5. When an abnormality exists (e.g., the voltage at the first input of the fourth comparator 201d is higher than the voltage at the second input of the fourth comparator 201d), the fourth comparator 201d outputs a preset level (low level) to the AND gate circuit 10 and the interface circuit 9, thereby triggering the test control chip 101 and the processor 102 to perform corresponding abnormal alarm processing.

[0070] In one possible implementation, the chip test circuit provided in this disclosure also has over-temperature protection (OTP) alarm and grounding protection alarm functions. For example... Figure 3 As shown, the chip under test is set in the aging test board, i.e., the BIB board. The chip test circuit also includes a second alarm module 12, which includes at least one second alarm link 1201, including at least one of a ground alarm link and an over-temperature alarm link.

[0071] like Figure 2As shown, the ground alarm link (DGS link) is equipped with a third amplifier 1201c (amplifier in the ground alarm link) and a fifth comparator 1201a (comparator in the ground alarm link). The two input terminals of the third amplifier 1201c are connected to the ground line of the chip test circuit and the ground line of the aging test board (BIB board), respectively. The output terminal of the third amplifier 1201c is connected to the first input terminal of the fifth comparator 1201b. The digital-to-analog converter 11 is connected to the second input terminal of the fifth comparator 1201a. The output terminal of the fifth comparator 1201b is connected to the test control chip 101 through the AND gate circuit 10 and to the processor 102 through the interface circuit 9. The third amplifier 1201c is used to amplify the ground voltage difference between the chip test circuit and the aging test board. The fifth comparator 1201a is used to output a preset level when the voltage value of the first input terminal of the fifth comparator 1201a is greater than the voltage value of the second input terminal of the fifth comparator 1201a. The grounding alarm link is used to detect the voltage difference between the ground of the resource board and the ground of the BIB board. If the voltage difference is too large, it will cause the voltage output by the power module 3 to be inaccurate, affecting the power-on of the chip under test. Since the voltage difference is usually between 100-200mV, which is a small value, it needs to be amplified by the third amplifier 1201c, and then compared with the preset voltage threshold output by the digital-to-analog converter 11 for the grounding alarm circuit by the fifth comparator 1201a. When the voltage value of the voltage difference exceeds the preset voltage threshold, the fifth comparator 1201b outputs a preset level, triggering the test control chip 101 and the processor 102 to perform abnormal alarm processing.

[0072] The over-temperature alarm link includes a sixth comparator 1201b (the comparator in the over-temperature alarm link). The first input terminal of the sixth comparator 1201b is connected to the over-temperature protection circuit of the power module 3. The digital-to-analog converter 11 is connected to the second input terminal of the sixth comparator 1201b. The output terminal of the sixth comparator 1201b is connected to the test control chip 101 through the AND gate circuit 10 and to the processor 102 through the interface circuit 9. The sixth comparator 1201b is used to output a preset level when the voltage value of the first input terminal of the sixth comparator 1201b is greater than the voltage value of the second input terminal of the sixth comparator 1201b. If the power module 3 malfunctions, it may overheat, which could damage the chip test circuit. Therefore, an over-temperature protection circuit can be set for the power module 3. The temperature of the power module 3 will rise, causing the voltage of the over-temperature protection circuit to rise. When the voltage exceeds the preset voltage threshold output by the digital-to-analog converter 11 for the over-temperature alarm circuit, the sixth comparator 1201b outputs a preset level, triggering the test control chip 101 and the processor 102 to perform abnormal alarm processing.

[0073] In one possible implementation, such as Figure 3As shown, the control module 1 also includes a controller 103. The processor 102 is connected to a host computer via a network, used to receive and parse chip test commands sent by the host computer, and to forward chip test commands to the controller 103. The chip test commands indicate the power supply voltage corresponding to the chip under test. The controller 103 is connected to the front-end power supply of each power module 3, used to control the front-end power supply to supply power to each power module 3 based on the chip test commands. Indicatively, the controller 103 can be a microcontroller unit (MCU), system-on-chip (SOC), microprocessor unit (MPU), etc. This embodiment uses an MCU as an example. The MCU can be responsible for the power health management and monitoring of the entire resource board, monitoring whether the voltage of all secondary power supplies of the resource board is normal during operation. In addition, the MCU is also responsible for the power-on sequence control of the secondary power supplies of the resource board, and the front-end power enable control of the power modules 3. By controlling the front-end power enable of the power modules 3, the MCU can supply power to one power module 3 individually, or simultaneously supply power to all power modules 3.

[0074] In the chip testing circuit provided in this embodiment, the first alarm module 2 and the second alarm module 12 can realize various types of anomaly detection and alarm. Open circuits are usually caused by blown fuses. Circuits typically include an overcharge safety device (OSD). When the power supply is overcharged, the voltage generated by the power supply can trigger an internal short circuit in the OSD, generating a large instantaneous current that causes the fuse to blow, thereby cutting off the internal circuit of the power supply and achieving safety protection. For open circuit alarms, current related technologies mainly use the ohmmeter function of a multimeter to measure the link impedance and determine whether an open circuit exists based on the impedance value. Alternatively, they enable the internal 1V voltage source by using the OLSx bit in the FAULT register and determine whether a load open circuit has occurred by checking the status of the OUTx bit in the OUT register. However, the first method is inefficient and costly. The factory manually uses a multimeter to confirm whether the power path is open or not. It can only be used when the resource board is powered off. In addition, there are a large number of resource boards, so it is not possible to quickly detect open circuits in the power paths of all resource boards. The second method has a complex circuit structure, requires the use of multiple circuit components, and has a slow response speed to abnormal alarms.

[0075] The chip testing circuit provided in this embodiment uses a test control chip 101 and a processor 102 as the control core, and an ADC6 as the voltage measurement device. It is equipped with a second amplifier 201f and a fourth comparator 201d to implement open-circuit alarm detection. The test control chip 101 is responsible for driving the power-on and power-off of each power module 3 and for individually powering off the power module 3 corresponding to the target detection link with abnormal voltage. The processor 102 is responsible for confirming abnormal information and interacting with the host computer, and can also control the ADC6 to measure the voltage of the target detection link. When an abnormal voltage occurs in the target detection link, the comparator outputs a preset level, which simultaneously triggers the test control chip 101 and the processor 102 to execute the above-mentioned abnormal alarm process through the AND gate circuit 10 and the interface circuit 9, respectively.

[0076] Compared with traditional open-circuit detection circuits, the chip testing circuit provided in this disclosure has the following advantages:

[0077] 1. High efficiency and fast response time to anomalies

[0078] The chip test circuit provided in this embodiment uses the output of a second amplifier 201f connected to the input of a fourth comparator 201d. The fourth comparator 201d monitors the voltage difference between the first link 4 and the second link 5. If an abnormal voltage difference occurs, the fourth comparator 201d immediately outputs a preset level (e.g., a low level). The preset level of the fourth comparator 201d is connected to the input of the AND gate circuit 10, so the output of the AND gate circuit 10 also immediately changes to the preset level. The test control chip 101 scans the output of the AND gate circuit 10. Once the test control chip 101 detects that the output level of the AND gate circuit 10 changes from a normal level to a preset level, it immediately adopts a power-down strategy, sequentially powering down the corresponding power module 3 and target detection link. Because the test control chip 101 is a logic device that can perform parallel processing in software control, if multiple target detection links experience power abnormalities, the test control chip 101 can simultaneously control all abnormal target detection links and power modules 3 to perform sequential power-down and illuminate the alarm lights.

[0079] 2. Low circuit complexity

[0080] The chip test circuit provided in this embodiment uses an amplifier, a comparator, and an AND gate circuit 10 in a combined design. The output of the comparator is connected to the input of the AND gate circuit 10 and the interface circuit 9. The processor 102 can quickly capture the abnormal target detection link by scanning the input interrupt signal of the interface circuit 9 through IIC scanning, while the test control chip 101 can quickly determine the abnormal target detection link by scanning the output of the AND gate circuit 10 and quickly control the corresponding power module 3 to power down sequentially. Compared with using multiple MCUs to implement the monitoring function, the chip test circuit provided in this embodiment uses the AND gate circuit 10 instead of MCUs for alarm detection, which is simpler and more efficient, and reduces the complexity of circuit design. Using multiple MCUs for monitoring not only requires communication between the MCUs, but also requires uploading abnormal data to the processor 102 for response, making the software design process very complex. In addition, each MCU also requires the design of peripheral circuits, which makes the hardware design of the circuit more complex.

[0081] 3. Lower chip testing costs

[0082] As mentioned in point 2 above, the chip test circuit provided in this embodiment uses an AND gate circuit 10 instead of an MCU to realize the alarm voltage detection of the power channel, which greatly reduces the design cost of the resource board. At the same time, the use of hardware AND gates also reduces the risk of software misjudgment, increases the reliability of detection, and the hardware response speed is faster than the software scanning detection speed. Therefore, the chip test circuit provided in this embodiment can better protect the chip under test.

[0083] 4. Alarm information can be completely saved for easy analysis.

[0084] The chip testing circuit provided in this embodiment adopts an architecture of test control chip 101 + processor 102 + controller 103. The controller 103 is responsible for health management and monitoring of all power supplies on the resource board, and can detect abnormal power supply voltages through polling scans. The processor 102 detects the target detection link and the type of abnormality through the interrupt signal of the IIC scanning interface circuit 9. When a power abnormality alarm occurs on the target detection link, the controller 103 records the current voltage values ​​of all power supplies on the resource board, and the processor 102 records the alarm information and saves all alarm information for further analysis and processing.

[0085] In one possible implementation, such as Figure 4 As shown, the first link 4 and the second link 5 are connected to at least one chip under test via a gold finger connector 13. Alternatively, other types of pluggable connectors, surface mount connectors, and fixed connectors can be used to connect resource boards and BIB boards.

[0086] Figure 5 The diagram illustrates the structure of a first link 4, in which a first relay switch 402 is provided. The first relay switch 402 is connected to a gold finger connector 13. A test control chip 101 is used to control the opening and closing state of each switch channel in the first relay switch 402. Different switch channels of the first relay switch 402 are used to connect different chips under test (DUTs). Indicatively, the first relay switch 402 can be a mechanical relay switch. A BIB board typically contains a large number of DUTs; by switching the first relay switch 402, one or more DUTs can be selected for power supply.

[0087] Figure 6 The diagram illustrates the structure of a second link 5. The second link 5 includes a second relay switch 501 and an analog switch 502. The second relay switch 501 is connected to a gold finger connector 13. A processor 102 controls the opening and closing states of each switch channel in the second relay switch 501, with different switch channels connecting to different chips under test (DUTs). The analog switch 502 is connected to at least one power supply module 3. A test control chip 101 controls the opening and closing states of the analog switch 502 to select the DUT for detection feedback voltage measurement and adjusts the output voltage of at least one power supply module 3 based on the measured detection feedback voltage value. Schematic, the second relay switch 501 can be an optocoupler relay switch. The second link 5 can feed back the voltage of the DUT to the power supply module 3, allowing the power supply module 3 to adjust the output voltage and maintain its stability. Optionally, the second link 5 can include an operational amplifier link 503 and an instrumentation amplifier link 504 to amplify the remote sense voltage, enabling the power supply module 3 to accurately read its voltage value.

[0088] This disclosure also provides a chip test board (such as...). Figure 1 The resource board shown above contains the chip test circuits provided in the above embodiments.

[0089] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0090] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or corresponding parts between embodiments can be referred to interchangeably. The basic principles of this disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the specific details required for its implementation.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0092] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0093] The apparatus and device of this disclosure may be implemented in many ways. For example, the apparatus and device of this disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware.

[0094] It should also be noted that in the apparatus and equipment disclosed herein, the components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered as equivalent solutions to this disclosure.

[0095] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0096] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, adjustments, additions, and sub-combinations therein.

Claims

1. A chip test circuit, characterized by comprising: The test device comprises a control module, a first alarm module and at least one power supply module, the control module comprises a test control chip and a processor, and the first alarm module comprises at least one first alarm link; The power supply module is connected with the power supply end of the pin of the corresponding to-be-tested chip through the first link and connected with the detection end of the pin of the corresponding to-be-tested chip through the second link, and the power supply module is used for supplying power to the to-be-tested chip; The input end of the first alarm link is connected with a target detection link, the output end of the first alarm link is connected with the test control chip, the first alarm link is used for comparing the voltage value of the target detection link with a preset voltage threshold value, and sending a preset level to the test control chip when the relationship between the voltage value of the target detection link and the preset voltage threshold value meets a preset condition, the target detection link comprises at least one of the first link and the second link; The test control chip is connected with the power supply module, and is used for controlling the power supply module corresponding to the target detection link to be powered off when the preset level is received, wherein when the preset level sent by at least two first alarm links is received, the test control chip is used for controlling the power supply module corresponding to the target detection link connected with the at least two first alarm links to be powered off in parallel; The output end of the first alarm link is also connected with the processor through an interface circuit, the interface circuit is used for generating an interrupt signal when the preset level is received, and the processor is used for reading alarm information through the interface circuit when the interrupt signal is received and sending the alarm information to an upper computer.

2. The circuit of claim 1, wherein, A comparator is arranged in the first alarm link, the input end of the comparator comprises a first input end and a second input end, the first input end is connected with at least one of the first link and the second link, the second input end is connected with a digital-to-analog converter, and the digital-to-analog converter is used for outputting a voltage according to the preset voltage threshold value; The output end of the comparator is connected with the test control chip and connected with the processor through the interface circuit, and the comparator is used for outputting the preset level when the relationship between the voltage value of the first input end and the voltage value of the second input end meets the preset condition.

3. The circuit of claim 2, wherein, A power sampling resistor is arranged in the first link, each first alarm link comprises at least one first alarm sub-link, the first alarm sub-link comprises at least one of an overcurrent alarm link, an overvoltage alarm link, an undervoltage alarm link and an open-circuit alarm link, and a comparator is arranged in the first alarm sub-link; The output end of the comparator of each first alarm sub-link is connected with the test control chip through an AND gate circuit, and the AND gate circuit is used for performing AND operation on the output levels of the first alarm sub-links in the same first alarm link.

4. The circuit of claim 3, wherein, The first amplifier is arranged in the over-current alarm link, two input ends of the first amplifier are connected with two ends of the power sampling resistor respectively, and an output end of the first amplifier is connected with a first input end of the first comparator. A first input end of the second comparator in the over-voltage alarm link is connected with the second link. A first input end of the third comparator in the under-voltage alarm link is connected with the second link. The second amplifier is arranged in the open-circuit alarm link, two input ends of the second amplifier are connected with the second link and the first link respectively, and an output end of the second amplifier is connected with a first input end of the fourth comparator.

5. The circuit of claim 3, wherein, The to-be-tested chip is arranged in an aging test board, and the circuit further comprises a second alarm module, the second alarm module comprises a second alarm link, and the second alarm link comprises at least one of a ground alarm link and an over-temperature alarm link. The third amplifier is arranged in the ground alarm link, two input ends of the third amplifier are connected with a ground circuit of the chip test circuit and a ground circuit of the aging test board respectively, an output end of the third amplifier is connected with a first input end of the fifth comparator, the digital-analog converter is connected with a second input end of the fifth comparator, an output end of the fifth comparator is connected with the test control chip through the AND gate circuit and connected with the processor through the interface circuit, the third amplifier is used for amplifying a ground voltage difference between the chip test circuit and the aging test board, and the fifth comparator is used for outputting the preset level when a voltage value of the first input end of the fifth comparator is greater than a voltage value of the second input end of the fifth comparator. The sixth comparator is arranged in the over-temperature alarm link, a first input end of the sixth comparator is connected with an over-temperature protection circuit of the power supply module, the digital-analog converter is connected with a second input end of the sixth comparator, an output end of the sixth comparator is connected with the test control chip through the AND gate circuit and connected with the processor through the interface circuit, and the sixth comparator is used for outputting the preset level when a voltage value of the first input end of the sixth comparator is greater than a voltage value of the second input end of the sixth comparator.

6. The circuit according to any one of claims 1 to 5, characterized in that The control module further comprises a controller. The processor is connected with an upper computer through a network, used for receiving and analyzing a chip test instruction sent by the upper computer, and forwarding the chip test instruction to the controller, the chip test instruction is used for indicating a corresponding power supply voltage of a to-be-tested chip. The controller is connected with a front-stage power supply of the power supply module, used for controlling the front-stage power supply to supply power to the power supply module based on the chip test instruction.

7. The circuit according to any one of claims 1 to 5, characterized in that The first link and the second link are connected with at least one to-be-tested chip through a golden finger connector.

8. The circuit of claim 7, wherein, The first link is provided with first relay switches connected with the LCC, and the test control chip is configured to control the opening and closing states of each switch channel of the first relay switches, and different switch channels of the first relay switches are configured to connect different chips to be tested.

9. The circuit of claim 7, wherein, The second link is provided with second relay switches and analog switches; The second relay switches are connected with the LCC, and the processor is configured to control the opening and closing states of each switch channel of the second relay switches, and different switch channels of the second relay switches are configured to connect different chips to be tested. The analog switches are connected with the at least one power module, and the test control chip is configured to control the opening and closing states of the analog switches to select the chip to be tested for detection feedback voltage measurement, and adjust the output voltage of the at least one power module according to the measured detection feedback voltage value.

10. A chip test board card, characterized by, The chip test board card is provided with the chip test circuit as claimed in any one of claims 1 to 9.

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