Circuit board structure

Abstract

The utility model provides a circuit board structure. The circuit board structure comprises a substrate, a wafer assembly, a first fan-out line, a dielectric layer and a second fan-out line. The wafer assembly is disposed in the substrate. The first fan-out line is electrically connected with the wafer assembly. The dielectric layer is vertically stacked on the first fan-out line. The second fan-out lines are vertically stacked on the dielectric layer and electrically connected with the wafer assembly. The dielectric layer electrically isolates the first fan-out line from the second fan-out line.

Description

Technical Field

[0001] This utility model relates to circuit board structures, and more particularly to a circuit board structure that can improve product reliability through three-dimensional stacked circuits. Background Technology

[0002] With the widespread use of electronic products, higher performance is required. For example, to achieve thinner and smaller designs, the dimensions of individual components (e.g., chips and their interconnects) must be further reduced. However, minimizing component size poses a significant challenge to manufacturing capabilities. Therefore, while existing circuit board structures have gradually met their intended uses, they are not perfect in every aspect. Consequently, there is still a need to develop new circuit board structures. Utility Model Content

[0003] According to some embodiments, a circuit board structure is provided. The circuit board structure includes a substrate, a chip assembly, a first fan-out line, a dielectric layer, and a second fan-out line. The chip assembly is disposed in the substrate. The first fan-out line is electrically connected to the chip assembly. The dielectric layer is vertically stacked on the first fan-out line. The second fan-out line is vertically stacked on the dielectric layer and electrically connected to the chip assembly. The dielectric layer electrically isolates the first fan-out line from the second fan-out line.

[0004] In some embodiments, the first outgoing line and the second outgoing line partially overlap and partially do not overlap.

[0005] In some embodiments, the overlap area between the first outgoing line and the second outgoing line is greater than 75%.

[0006] In some embodiments, the first fan-out line has a first extension and a first connecting portion, and the second fan-out line has a second extension and a second connecting portion, wherein the first extension and the second extension overlap each other, and the first connecting portion and the second connecting portion do not overlap each other.

[0007] In some embodiments, the circuit board structure further includes a first conductive line and a second conductive line. The first conductive line is electrically connected to a first connection portion of the first fan-out line. The second conductive line is electrically connected to a second connection portion of the second fan-out line, and the second conductive line and the first conductive line do not overlap.

[0008] In some embodiments, the first fan-out line has a first height, the second fan-out line has a second height, the first conductive line has a third height, and the second conductive line has a fourth height, wherein the first height and the second height are less than the third height, and the first height and the second height are less than the fourth height.

[0009] In some embodiments, the sum of the first height and the second height is less than the third height, and the sum of the first height and the second height is less than the fourth height.

[0010] In some embodiments, the bottom surface of the first fan-out line is coplanar with the bottom surface of the first conductive line and coplanar with the bottom surface of the second conductive line.

[0011] In some embodiments, the first fan-out line has a first width, the second fan-out line has a second width, the first conductive line has a third width, and the second conductive line has a fourth width, wherein the first width and the second width are less than the third width, and the first width and the second width are less than the fourth width.

[0012] In some embodiments, the first or second outgoing line has an aspect ratio between 1:1 and 3:1.

[0013] The circuit board structure of this invention can be applied to various types of electronic devices. To make the components and advantages of this invention more apparent and understandable, various embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0014] The present invention can be more fully understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0015] Figure 1A This is a top view schematic diagram showing a circuit board structure based on some embodiments of the background art.

[0016] Figure 1B It is along Figure 1A A cross-sectional diagram of line segment A-A'.

[0017] Figures 2 to 8 These are cross-sectional schematic diagrams showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention.

[0018] Figure 9A This is a top view schematic diagram showing the chip connection area, fan-out line and conductive line according to some embodiments of the present invention.

[0019] Figure 9B It is along Figure 9A A cross-sectional diagram of line segment B-B'.

[0020] Figure 9C This is a three-dimensional schematic diagram showing the chip connection area, fan-out lines and conductive lines according to some embodiments of the present invention.

[0021] Figure 10AThis is a top view schematic diagram showing the chip connection area, fan-out line and conductive line according to some embodiments of the present invention.

[0022] Figure 10B It is along Figure 10A A cross-sectional view of line segment C-C'.

[0023] Figure 11 and Figure 12 These are cross-sectional schematic diagrams showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention. Detailed Implementation

[0024] The following provides a detailed description of the apparatus according to various embodiments of the present invention. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present invention. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are only examples and not limitations on the present invention. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention and does not represent any relationship between the different embodiments and / or structures discussed.

[0025] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that element (or those elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.

[0026] In some embodiments of this utility model, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding connection and bonding may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0027] In this text, the terms "approximately," "about," and "substantially" typically indicate a value or range within 10%, 5%, 3%, 2%, 1%, or 50%. The given quantities are approximate; that is, without specific mention of "approximately," "about," or "substantially," their meaning is implied. The phrase "the range is between the first and second values" indicates that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10%, 5%, 3%, 2%, 1%, or 50% between them. If the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, then the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0028] It should be understood that, without departing from the spirit of this utility model, the components in the various embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this invention.

[0030] Reference Figure 1A and Figure 1B These are, respectively, top views and cross-sectional views of a circuit board structure based on some embodiments of the background art. Figure 1B It is along Figure 1A A cross-sectional diagram of line segment A-A'. (See diagram below.) Figure 1AAs shown, in the top view formed by horizontal directions D1 and D2, the wafer connection area CA (where wafer assemblies are disposed) is electrically connected to the conductive line CW via fan-out lines (e.g., fan-out lines FW1 and FW2), and further electrically connected to other electronic components (not shown) via the conductive line CW. The end of the fan-out line connected to the wafer connection area CA has a higher wiring density, while the end connected to the conductive line CW has a lower wiring density. However, as the wafer assembly size shrinks (and the wafer connection area CA shrinks accordingly), this layout poses a considerable challenge to the horizontal accuracy of process capabilities. For example, to accommodate the shrinking wafer assembly size, the distance d between adjacent fan-out lines (e.g., fan-out lines FW1 and FW2) must become smaller, or the width w of a single fan-out line (e.g., fan-out line FW1 or fan-out line FW2) must become smaller. In this case, higher-order process equipment must be used to achieve product miniaturization, which may lead to a significant increase in production costs. In addition, excessive miniaturization may cause the distance d between fan-out lines to be too small, leading to a short circuit, or the width w of the fan-out lines to be too small, leading to an open circuit.

[0031] On the other hand, such as Figure 1B As shown, compared to the width w or distance d of the fan-out line, the height h of the fan-out line still has considerable leeway for adjustment (e.g., reduction). Therefore, this invention provides a circuit board structure in which multiple fan-out lines are stacked three-dimensionally along the vertical direction D3 to utilize space more effectively. In this way, while avoiding some potential problems caused by excessively small fan-out line widths (e.g., open circuits or short circuits due to insufficient precision), the circuit board structure of this invention not only relaxes the process margin but also brings higher reliability.

[0032] It is worth mentioning that, in this invention, the "chip assembly" may include a single chip or multiple chips, which are used to actively perform specific functions. For the sake of simplicity, Figure 1A The box in the image represents the chip connection area CA where the chip assembly is located. However, those skilled in the art will also understand that this box can also represent a controlled collapse chip connection (C4) area.

[0033] Reference Figures 2 to 8These are cross-sectional schematic diagrams showing different stages of the manufacturing process of a circuit board structure according to some embodiments of the present invention. It is worth noting that, for the sake of simplicity and ease of understanding, the dimensions of components and the proportions between them may be exaggerated in the accompanying drawings. Furthermore, some components in the circuit board structure may be omitted in the accompanying drawings, but those skilled in the art will understand that the circuit board structure may also include other common components. For example, for simplicity, only two fan-out lines are shown in the drawings, and other fan-out lines are omitted.

[0034] like Figure 2 As shown, a substrate 10 is provided. In this invention, the substrate 10 is used to support components disposed thereon during manufacturing (e.g., the first fan-out line 15 and the second fan-out line 17 mentioned below). In some embodiments, the substrate 10 may include one or more film layers, such as a core layer, a circuit layer, and a build-up film. For simplicity, Figure 2 These film layers are not specifically illustrated, but those skilled in the art can generally understand the possible composition or structure of the substrate 10 based on common knowledge or some of the possible materials listed below.

[0035] In some embodiments, the core layer material may be a prepreg containing polymeric materials, fibrous materials, or other suitable materials, but the present invention is not limited thereto. For example, the polymeric material may be epoxy resin, polyimide (PI), polypropylene (PP), other suitable polymeric materials, or combinations thereof, but the present invention is not limited thereto. For example, the fibrous material may be carbon fiber, glass fiber, other suitable fibrous materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the circuit layer material may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the buildup film material may be epoxy resin, polyimide (PI), Ajinomoto buildup film (ABF), other suitable polymeric materials, or combinations thereof, but the present invention is not limited thereto.

[0036] like Figure 2As shown, following the above steps, a first conductive material 11 is formed on the substrate 10. In some embodiments, the first conductive material 11 may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), their alloys or compounds, but the present invention is not limited thereto. In some embodiments, the first conductive material 11 may be formed by electroplating, chemical plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes or combinations thereof, but the present invention is not limited thereto.

[0037] like Figure 2 As shown, following the steps described above, a dielectric material 12 is disposed on the first conductive material 11. In some embodiments, the dielectric material 12 may be or may include epoxy resin, polyimide (PI), ABF (advanced polymeric material), other suitable polymeric materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the dielectric material 12 may be formed by lamination, coating, other suitable processes, or combinations thereof, but the present invention is not limited thereto.

[0038] like Figure 2 As shown, following the above steps, a second conductive material 13 is disposed on the dielectric material 12. In some embodiments, the second conductive material 13 may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), their alloys or compounds, but the present invention is not limited thereto. In some embodiments, the second conductive material 13 may be formed by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes or combinations thereof, but the present invention is not limited thereto. In some embodiments, the second conductive material 13 may be the same as or different from the first conductive material 11, depending on design requirements.

[0039] like Figure 3As shown, following the above steps, a masking material is formed on the second conductive material 13, and the masking material is patterned to form a patterned mask 14. The patterned mask 14 exposes a portion of the second conductive material 13. In some embodiments, the masking material may be or may include a hard mask, a soft mask, or a combination thereof. For example, the masking material may be or may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, photoresist, other suitable materials, or combinations thereof, but the present invention is not limited thereto. In this embodiment, the masking material is photoresist. In some embodiments, this can be performed using photolithography. Figure 3 The steps shown are used to pattern the mask material to form a patterned mask 14. For example, the photolithography process may include photoresist setup (e.g., spin-on coating, lamination), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof.

[0040] like Figure 4 As shown, following the above steps, the first conductive material 11, the dielectric material 12, and the second conductive material 13 are patterned to form the first fan-out line 15, the dielectric layer 16, and the second fan-out line 17, respectively. The first fan-out line 15 and the second fan-out line 17 are used to transmit signals, such as control signals, image signals, sound signals, other suitable signals, or combinations thereof, but the present invention is not limited thereto. On the other hand, the dielectric layer 16 is located between the first fan-out line 15 and the second fan-out line 17 and serves to electrically isolate the first fan-out line 15 from the second fan-out line 17.

[0041] In some embodiments, the first conductive material 11, dielectric material 12, and second conductive material 13 can be patterned by dry etching, wet etching, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the first conductive material 11, dielectric material 12, and second conductive material 13 not covered by the patterned mask 14 can be removed in one step by the same etching process, but the present invention is not limited thereto. For example, the first conductive material 11, dielectric material 12, and second conductive material 13 not covered by the patterned mask 14 can also be removed in batches by a multi-pass etching process. Since the first conductive material 11, dielectric material 12, and second conductive material 13 are patterned using the same patterned mask 14, the remaining dielectric material 12 (i.e., dielectric layer 16) and the remaining second conductive material 13 (i.e., second fan-out line 17) are vertically stacked on the remaining first conductive material 11 (i.e., first fan-out line 15). In other words, the first fan-out line 15 and the dielectric layer 16 can be considered to overlap each other, and the first fan-out line 15 and the second fan-out line 17 can overlap each other. Following the above steps, the patterned mask 14 is removed. In some embodiments, the patterned mask 14 can be removed by dry etching, wet etching or a combination thereof to expose the substrate 10, but the present invention is not limited thereto.

[0042] like Figure 5 As shown, following the steps described above, a seed layer 18 is formed on the substrate 10. In some embodiments, the material of the seed layer 18 may be or may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), their alloys, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the seed layer 18 may be formed by a plating process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), but the present invention is not limited thereto. In some embodiments, the seed layer 18 may optionally cover the top surface of the second fan-out line 17, but the present invention is not limited thereto. In other embodiments, when the material of the seed layer 18 is different from the material of the second fan-out line 17, the second fan-out line 17 may be shielded by a patterned mask (not shown) to prevent the seed layer 18 from forming on the top surface of the second fan-out line 17, thereby creating an unintended interface.

[0043] like Figure 6 As shown, following the steps described above, a masking material is applied to the second fan-out line 17 and a portion of the seed layer 18, and the masking material is patterned to form a patterned mask 19. The patterned mask 19 exposes another portion of the seed layer 18. In some embodiments, the masking material may be or may include a hard mask, a soft mask, or a combination thereof. In some embodiments, this can be performed using a photolithography process. Figure 6The steps shown are used to pattern the mask material to form a patterned mask 19. The specific materials and processes of the patterned mask 19 can be found in the description of the patterned mask 14 above, and will not be repeated here.

[0044] like Figure 7 As shown, following the above steps, a conductive material is applied to the seed layer 18 exposed from the patterned mask 19, such that a portion of the seed layer 18 and the conductive material together form a first conductive line 20, and another portion of the seed layer 18 and the conductive material together form a second conductive line 21. In some embodiments, the conductive material may be aluminum (Al), copper (Cu), their alloys, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the conductive material may be applied by a plating process such as electroplating or electroless plating, but the present invention is not limited thereto. In some embodiments, the material of the seed layer 18 may be similar to or the same as the conductive material applied in this step, but the present invention is not limited thereto.

[0045] like Figure 8 As shown, following the above steps, the patterned mask 19 is removed to expose the seed layer 18, which is not covered by the first fan-out line 15 and for which the first conductive line 20 and the second conductive line 21 are not formed. For example, the patterned mask 19 can be removed by an etching process such as dry etching or wet etching, but the present invention is not limited thereto. Further, following the above steps, the remaining seed layer 18 is removed to expose the substrate 10. After this step, the bottom surface of the first fan-out line 15 is coplanar with the bottom surface of the first conductive line 20 and with the bottom surface of the second conductive line 21. On the other hand, the height of the first conductive line 20 and the height of the second conductive line 21 are both greater than the sum of the heights of the first fan-out line 15, the dielectric layer 16, and the second fan-out line 17. In other words, the top surface of the second fan-out line 17 is not coplanar with the top surface of the first conductive line 20 and is not coplanar with the top surface of the second conductive line 21. Of course, the present invention is not limited thereto. In other embodiments, those skilled in the art can adjust the height (or thickness) of the above-mentioned components arbitrarily according to design requirements, or make the surfaces (e.g., top or bottom surfaces) of the above-mentioned components coplanar or non-coplanar by means such as setting a dielectric layer.

[0046] It is worth mentioning that, Figures 2 to 8 The steps roughly describe the formation process of the first sector exit line 15, the second sector exit line 17, the first conductive line 20, and the second conductive line 21. More specifically, Figures 2 to 8 The steps involve the first extension 150 of the first outgoing line 15 and the second extension 170 of the second outgoing line 17. The first extension 150 and the second extension 170 overlap each other and are electrically connected to the components disposed on... Figure 9AThe chip assembly in chip interconnect region 22. As mentioned above, in this invention, a “chip assembly” may include a single chip or multiple chips, which or these chips are used to actively perform a specific function. Alternatively, those skilled in the art will also understand that this block may also be a flip-chip interconnect (C4) region with controllable collapse solder height, so that the first fan-outline 15 and the second fan-outline 17 can connect one or more chips in this region.

[0047] Refer to together Figures 9A to 9C These are, respectively, top view, cross-sectional view, and perspective view of the display chip, fan-out line, and conductive line according to some embodiments of the present invention. Figure 9B It is along Figure 9A A cross-sectional diagram of line segment B-B'. (See diagram below.) Figure 9A As shown, the first outgoing line 15 further includes a first connecting portion 151, and the second outgoing line 17 further includes a second connecting portion 171. The first connecting portion 151 is used to connect the first conductive line 20, and the second connecting portion 171 is used to connect the second conductive line 21, and the first connecting portion 151 and the second connecting portion 171 do not overlap. It is worth mentioning that, although... Figures 2 to 8 The steps do not directly describe the formation process of the first connecting part 151 and the second connecting part 171, but those skilled in the art can refer to some of the methods mentioned herein and make slight adjustments to these methods to form the first connecting part 151 of the first fan-out line 15 and the second connecting part 171 of the second fan-out line 17.

[0048] As described above, since the first connecting portion 151 of the first fan-out line 15 and the second connecting portion 171 of the second fan-out line 17 extend in different directions to connect to the first conductive line 20 and the second conductive line 21 respectively, the first fan-out line 15 and the second fan-out line 17 do not completely overlap. In other words, the first fan-out line 15 and the second fan-out line 17 partially overlap and partially do not overlap. In some embodiments, the overlap area of ​​the first fan-out line 15 and the second fan-out line 17 is greater than 75%. For example, the overlap area of ​​the first fan-out line 15 and the second fan-out line 17 can be 80%, 85%, 90%, 95%, 97.5%, 99%, or any value or range between the above values. Compared to the horizontal wiring methods in the prior art (such as...) Figure 9A As shown in the diagram, this invention can maintain the same number of input / output (I / O) in a specific wiring area and improve the width of the fan-out line (or increase the spacing between two fan-out lines) through three-dimensional stacking, thereby improving the reliability of the device.

[0049] like Figure 9BAs shown, it can be seen from the cross-sectional view that the first outgoing line 15 has a first height h1 and a first width w1, and the second outgoing line 17 has a second height h2 and a second width w2. In some embodiments, the aspect ratio (w1:h1) of the first outgoing line 15 or the aspect ratio (w2:h2) of the second outgoing line 17 is between 1:1 and 3:1, but the present invention is not limited thereto. For example, when the first height h1 of the first outgoing line 15 is x μm, the first width w1 of the first outgoing line 15 can be x μm to 3x μm. Similarly, when the second height h2 of the second outgoing line 17 is x μm, the second width w2 of the second outgoing line 17 can be x μm to 3x μm. In this embodiment, the aspect ratios (h1:w1) of the first outgoing line 15 and (w2:h2) of the second outgoing line 17 are 3:1. In other words, the first height h1 and the first width w1 of the first outgoing line 15 are x μm and 3x μm respectively, and the second height h2 and the second width w2 of the second outgoing line 17 are x μm and 3x μm respectively.

[0050] As Figure 9C shown, it can be seen from the perspective view that the first conductive wire 20 has a third height h3, and the second conductive wire 21 has a fourth height h4. Among them, the first height h1 of the first outgoing line 15 and the second height h2 of the second outgoing line 17 are both less than the third height h3 of the first conductive wire 20 (i.e., h1 < h3 and h2 < h3), and the first height h1 of the first outgoing line 15 and the second height h2 of the second outgoing line 17 are both less than the fourth height h4 of the second conductive wire 21 (i.e., h1 < h4 and h2 < h4). More specifically, the total height ht of the first outgoing line 15, the dielectric layer 16, and the second outgoing line 17 is less than or equal to the third height h3 of the first conductive wire 20 and the fourth height h4 of the second conductive wire 21 (i.e., ht ≤ h3 and ht ≤ h4). Without considering the thickness of the dielectric layer 16 that is not used for conduction, the total length of the outgoing lines for the redistribution function in the vertical direction D3 (i.e., h1 + h2) is less than the total length of the conductive wires for connection in the vertical direction D3 (i.e., h3 or h4). In other words, the present invention improves the space utilization by reducing the height of the outgoing lines in the vertical direction D3.

[0051] Referring Figure 10A and Figure 10B , which are respectively the top view schematic diagram and the cross-sectional schematic diagram showing the wafer, the outgoing lines, and the conductive wires according to some embodiments of the present invention. The difference from the Figures 9A to 9C embodiment shown is that Figure 10A and Figure 10BThe embodiment further reduces the width of the fan-out line extension to achieve a greater number of input / output (I / O) connections within a specific wiring area. In this embodiment, the aspect ratio (h1:w1) of the first fan-out line 15 and the aspect ratio (w2:h2) of the second fan-out line 17 are both 1:1. In other words, the first height h1 and the first width w1 of the first fan-out line 15 are both x μm, and the second height h2 and the second width w2 of the second fan-out line 17 are both x μm. This effectively improves the applicability of the product.

[0052] Reference Figure 11 and Figure 12 This is a cross-sectional schematic diagram showing the circuit board structure at different stages of the manufacturing process, according to some embodiments of the present invention. For example... Figure 11 As shown, continuing Figure 8 The steps involve blanketing a dielectric layer 23 onto the first conductive line 20, the second fan-out line 17, the second conductive line 21, and the substrate 10. In some embodiments, the material of the dielectric layer 23 may be epoxy resin, polyimide (PI), build-up material (ABF), other suitable polymer materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the dielectric layer 23 may be formed by lamination, coating, other suitable processes, or combinations thereof, but the present invention is not limited thereto.

[0053] In some embodiments, the dielectric layer 23 and the substrate 10 may be collectively referred to as substrate 24. Thus, the circuit board structure includes substrate 24, a chip assembly, a first fan-out line 15, a dielectric layer 16, and a second fan-out line 17. The chip assembly is disposed in substrate 24 and located in chip interconnect region 22. The first fan-out line 15 is electrically connected to the chip assembly. The dielectric layer 16 is vertically stacked on the first fan-out line 15. The second fan-out line 17 is vertically stacked on the dielectric layer 16 and is electrically connected to the chip assembly. The dielectric layer 16 electrically isolates the first fan-out line 15 from the second fan-out line 17.

[0054] like Figure 12 As shown, following the above steps, according to the design requirements, further components such as vertical connectors for vias, horizontal connectors for circuit layers, active components such as chips, passive components such as antennas, or protective components such as green paint are added to complete the manufacturing of circuit board structure 1.

[0055] In summary, this invention provides a circuit board structure in which multiple fan-out lines are stacked vertically along the D3 direction, thereby avoiding potential problems caused by excessively narrow fan-out lines (e.g., open circuits or short circuits due to insufficient precision). As a result, this circuit board structure not only relaxes the process margin but also brings higher product reliability. In some cases, this circuit board structure can also increase the number of inputs / outputs, thereby improving product applicability.

[0056] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0057] [Symbol Explanation]

[0058] 1: Circuit board structure

[0059] 10:Substrate

[0060] 11: First conductive material

[0061] 12: Dielectric materials

[0062] 13: Second conductive material

[0063] 14: Patterned Masking

[0064] 15: First outgoing line

[0065] 150: First Extension

[0066] 151: First connecting part

[0067] 16: Dielectric layer

[0068] 17: Second door outgoing line

[0069] 170: Second Extension

[0070] 171: Second connecting part

[0071] 18: Seed layer

[0072] 19: Patterned Mask

[0073] 20: First conductive line

[0074] 21: Second conductive wire

[0075] 22: Chip Connectivity Area

[0076] 23: Dielectric layer

[0077] 24:Substrate

[0078] A-A': Line segment

[0079] B-B': line segment

[0080] CA: Chip Connectivity Area

[0081] CW: Conductive wire

[0082] C-C': line segment

[0083] d: distance

[0084] D1: Horizontal direction

[0085] D2: Horizontal direction

[0086] D3: vertical direction

[0087] h: height

[0088] h1: First Height

[0089] h2: Second altitude

[0090] h3: Third Height

[0091] h4: Fourth Altitude

[0092] ht: Total height

[0093] FW1: Fan-out cable

[0094] FW2: Fan-out cable

[0095] w: width

[0096] w1: First width

[0097] w2: Second width

[0098] w3: Third width

[0099] w4: Fourth width.

Claims

1. A circuit board structure, characterized in that, include: substrate; A chip assembly is disposed in the substrate; The first output line is electrically connected to the chip assembly; A dielectric layer is vertically stacked on the first fan-out line; as well as The second lead-out line is vertically stacked on the dielectric layer and electrically connected to the chip assembly. The dielectric layer electrically isolates the first outgoing line from the second outgoing line.

2. The circuit board structure according to claim 1, characterized in that, The first outgoing line and the second outgoing line partially overlap and partially do not overlap.

3. The circuit board structure according to claim 2, characterized in that, The overlap area between the first and second outgoing lines is greater than 75%.

4. The circuit board structure according to claim 1, characterized in that, The first fan-out line has a first extension and a first connecting portion, and the second fan-out line has a second extension and a second connecting portion, wherein the first extension and the second extension overlap each other, and the first connecting portion and the second connecting portion do not overlap each other.

5. The circuit board structure according to claim 4, characterized in that, Also includes: The first conductive wire is electrically connected to the first connection portion of the first fan-out line; as well as The second conductive line is electrically connected to the second connecting portion of the second fan-out line, and the second conductive line does not overlap with the first conductive line.

6. The circuit board structure according to claim 5, characterized in that, The first fan-out line has a first height, the second fan-out line has a second height, the first conductive line has a third height, and the second conductive line has a fourth height, wherein the first height and the second height are less than the third height, and the first height and the second height are less than the fourth height.

7. The circuit board structure according to claim 6, characterized in that, The sum of the first height and the second height is less than the third height, and the sum of the first height and the second height is less than the fourth height.

8. The circuit board structure according to claim 5, characterized in that, The bottom surface of the first fan-out line is coplanar with the bottom surface of the first conductive line and coplanar with the bottom surface of the second conductive line.

9. The circuit board structure according to claim 5, characterized in that, The first fan-out line has a first width, the second fan-out line has a second width, the first conductive line has a third width, and the second conductive line has a fourth width, wherein the first width and the second width are smaller than the third width, and the first width and the second width are smaller than the fourth width.

10. The circuit board structure according to claim 1, characterized in that, The first or second outgoing cable has a width-to-height ratio between 1:1 and 3:1.

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