360-pin AI core board

Abstract

The utility model belongs to the technical field of circuit boards of artificial intelligence equipment, in particular to a 360-pin AI core board, which comprises a processor, a power management module, a memory and an electronic hard disk, and is characterized in that a board-to-board connector used for being plugged with an external bottom board is arranged on one side of a board body; the interfaces arranged on the board-to-board connector comprise a power input interface, a power output interface, an I2C interface, an SPI interface, a UART interface and a GPIO interface, the board is provided with very complete data interfaces, is suitable for coding and decoding in various formats, is high in operation processing efficiency, is suitable for graphic processing, is remarkable in AI operation advantage, supports multi-path display and high-performance peripheral interfaces, and is suitable for being applied to various types of data processing. As an independent module embedded system, development time can be saved, risks can be reduced, marketing can be accelerated, and the system is high in practicability and cost performance in the field of artificial intelligence Internet of Things and has great popularization value.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the circuit board technical field of artificial intelligence equipment, specifically relates to a 360pin's AI core board. BACKGROUND

[0002] Under the market pattern of fast change and multiple needs in the contemporary, the existing most core boards expose certain limitation. They are mostly designed based on the specific requirements of customers and aimed at fixed application scene, which leads to the relatively single interface type and limited quantity, and it is difficult to meet the growing expansion needs. In the environment of emerging technologies emerging in various fields and different industries accelerating cross-border integration, rich interfaces are crucial for the core board to quickly adapt to new scenes and seamlessly interface with other devices. The current situation of insufficient interfaces undoubtedly limits the expansion application of the core board in a wider field, and it has become one of the key factors restricting the further development and growth of the core board in the contemporary pattern. UTILITY MODEL CONTENT

[0003] The utility model aims at providing a 360pin's AI core board, solving the technical problems of insufficient video encoding and decoding capability, limited 3D graphics processing capability and low AI operation efficiency in the field of artificial intelligence Internet of Things, and lack of complete development board for secondary development.

[0004] To solve the above technical problems, the utility model adopts the following technical scheme:

[0005] A 360pin's AI core board is provided, comprising a PCB board, a processor, a power management module and a memory are arranged on the PCB board, and a board-to-board connector is arranged on the PCB board for plugging with an external bottom plate, the board-to-board connector has 360 pins, a plurality of interfaces with different functions are arranged in the 360 pins, and the interfaces include a power input interface, a power output interface, an RGMII interface, an SDMMC interface, an ADC interface, an MIPI_DSI interface, an eDP interface, a USB interface, a PCIe interface, a Type-C interface, an HDMI interface, an MIPI_CSI interface, an SDIO interface, an I2S interface, an I2C interface, an SPI interface, a UART interface and a GPIO interface.

[0006] Preferably, the board-to-board connector includes a board-to-board connector A, a board-to-board connector B, a board-to-board connector C and a board-to-board connector D, and the board-to-board connector A, the board-to-board connector C and the board-to-board connector B and the board-to-board connector D are arranged on the two sides of the bottom of the PCB board.

[0007] Preferably, the board-to-board connector A and the board-to-board connector B have 80 pins respectively, and the board-to-board connector C and the board-to-board connector D have 100 pins respectively.

[0008] Preferably, the 80 pins of board-to-board connector A are pins A1 to A80, the 80 pins of board-to-board connector B are pins B1 to B80, the 100 pins of board-to-board connector C are pins C1 to C100, and the 100 pins of board-to-board connector D are pins D1 to D100, wherein:

[0009] The power input interface is constructed via pins A67, A68, A69, A70, A71, A72, A73, A74, A75, A76, A77, A78, A79, and A80 of board-to-board connector A; the RGMII interface is constructed via pins D64, D66, D68, D70, D72, D73, D74, D75, D79, D81, D89, D91, D93, D95, D97, and D99 of board-to-board connector D; the SDMMC interface is constructed via pins A11, A13, A15, A17, A19, A21, and A23 of board-to-board connector A; the A The DC interface is constructed via pins A20, A22, A28, A30, and A32 of board-to-board connector A; the MIPI_DSI interface is constructed via pins A3 and A27 of board-to-board connector A, pins B57 and B61 of board-to-board connector B, and pins C41, C43, C45, C47, C49, C51, C53, C55, C57, C59, C63, C65, C67, C69, C71, C73, C75, C77, C79, and C81 of board-to-board connector C; the eDP interface is constructed via pins C1, C3, C5, C7, C9, C11, C13, C15, and C16 of board-to-board connector C. 7. The USB interface is constructed using pins C19, C82, C84, C86, C88, C90, C92, C94, C96, C98, and C100; the USB interface is constructed using pins A36, A38, A44, and A46 of board-to-board connector A; the PCIe interface is constructed using pins A31, A33, and A35 of board-to-board connector A, pins B24, B34, B60, B76, B79, and B80 of board-to-board connector B, and pins D3, D5, D7, D9, D11, D13, D17, D19, D21, D23, D25, D27, D31, D33, D35, and D37 of board-to-board connector D. The Type-C interface is constructed using pins D39, D41, D4, D6, D10, D12, D16, D18, D22, D24, D28, D30, D34, D36, D40, D42, D46, D48, D52, D54, D58, and D60; the Type-C interface is constructed using pins A5, A7, A40, A42, A50, and A52 of board-to-board connector A, pins C2, C4, C6, C8, C10, C12, C14, C16, C72, C74, C76, C78, ​​C85, C87, C91, and C93 of board-to-board connector C, and pins D83 and D85 of board-to-board connector D.The HDMI interface is constructed via pins A4, A14, A26, A34, A39, A45, A47, A49, A51, A53, and A55 of board-to-board connector A; pins B77, B32, B40, and B70 of board-to-board connector B; and pins C23, C25, C27, C29, C31, C33, C35, and C37 of board-to-board connector C. The MIPI_CSI interface is constructed via pin A37 of board-to-board connector A; and pins B77, B32, B40, and B70 of board-to-board connector B. Pins B55, B18, B20, B22, B26, B36, B44, B50, B58, B62, and B64; pins C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C42, C44, C46, ​​C48, C50, C52, C54, C56, C58, and C60 of board-to-board connector C; and pins D45, D47, D49, D51, D53, D55, and D59 of board-to-board connector D. The SDIO interface is constructed using pins D61, D63, D65, D67, D69, D78, D80, D82, D84, D86, D88, D90, D92, D94, D96, D98, and D100 of board-to-board connector A; the I2S interface is constructed using pins B2, B4, B6, B8, and B10 of board-to-board connector B; and the I2C interface is constructed using board-to-board connector B. The connector A's pins A6 and A8, and the board-to-board connector B's pins B49, B51, B54, B56, B66, and B68 constitute the interface; the UART interface is formed by the board-to-board connector B's pins B69, B71, B14, B16, B38, and B42; several reusable GPIO pins are provided on the board-to-board connectors A, B, and D, and the SPI interface, GPIO interface, and power output interface are formed by these reusable GPIO pins.

[0010] Preferably, board-to-board connector A and board-to-board connector B have a bandwidth of 5Gbps, a pin pitch of 0.5mm, and a height of 3mm; board-to-board connector C and board-to-board connector D have a bandwidth of 10Gbps, a pin pitch of 0.5mm, and a height of 3mm.

[0011] Preferably, the processor, power management module, and memory are located on one side of the PCB board, and the board-to-board connector is located on the other side of the PCB board.

[0012] Preferably, the processor is an RK3588 processor.

[0013] Preferably, the memory includes a memory module and a secondary memory module.

[0014] Compared with existing technologies, the beneficial effects of this utility model are as follows: The 360-pin AI core board includes onboard components such as a processor, power management module, memory, and electronic hard disk. A board-to-board connector for interfacing with an external baseboard is located on one side of the board. This connector has pins corresponding to multiple different functional interfaces, including power input, power output, RGMII, SDMMC, ADC, MIPI_DSI, eDP, USB, PCIe, Type-C, HDMI, MIPI_CSI, SDIO, I2S, I2C, SPI, UART, and GPIO interfaces. This 360-pin AI core board features a comprehensive set of data interfaces. Based on the Rockchip RK3588 processor, it boasts powerful video encoding and decoding capabilities, supports 8K multi-format encoding and decoding, offers high processing efficiency, excellent graphics processing, significant AI computing advantages, supports multi-channel display and high-performance peripheral interfaces, and includes a complete development kit. Embedded as an independent module, this system saves development time, reduces risk, and accelerates time-to-market. It is highly practical and cost-effective in the field of AIoT (Artificial Intelligence of Things), making it extremely valuable for widespread adoption. The pins constituting the interfaces on this 360-pin AI core board are carefully planned and arranged from four board-to-board connectors. The position of each interface is arranged according to the bandwidth of the corresponding board-to-board connector, resulting in a rational layout that reduces mutual interference and promotes signal stability. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:

[0016] Figure 1 This is a front structural diagram of an embodiment of the 360-pin AI core board of this utility model.

[0017] Figure 2 This is a reverse structural diagram of an embodiment of the 360-pin AI core board of this utility model.

[0018] Figure 3 This is a front component layout diagram of an embodiment of the 360pin AI core board of this utility model.

[0019] Figure 4 This is a reverse component layout diagram of an embodiment of the 360pin AI core board of this utility model.

[0020] Figure 5 This is a pin diagram of an embodiment of the 360-pin AI core board of this utility model.

[0021] Figure 6 for Figure 5 Enlarged view of the pins of connector A.

[0022] Figure 7 for Figure 5 Enlarged view of the pins of the B-type connector.

[0023] Figure 8 for Figure 5 Enlarged view of the pins of the C-type connector.

[0024] Figure 9 for Figure 5 Enlarged view of the pins of the D-type connector. Detailed Implementation

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0026] In one embodiment, a 360-pin AI core board is provided; please refer to [link / reference]. Figures 1 to 9 .

[0027] like Figure 1 As shown, the 360-pin AI core board includes a PCB board 1, on which a processor 2, a power management module 3, and a memory are mounted. The memory includes a main memory module and an external storage module. The main memory module includes DDR4 memory chips 4 and DDR4 memory chips 5, and the external storage module is an electronic hard disk 6. Figure 1 As shown, the two DDR4 memory chips, DDR4 memory chip 4 and DDR4 memory chip 5, and the electronic hard drive 6 are electrically connected to the processor 2 through the internal circuitry of the PCB board 1. The power management module 3 provides power to the two DDR4 memory chips, the electronic hard drive 6, and the processor 2. The processor 2 can read and write data from the two DDR4 memory chips and the electronic hard drive 6. The PCB board 1 also has peripheral circuits such as a clock circuit, which enable the processor 2, the power management module 3, the two DDR4 memory chips, and the electronic hard drive 6 to function normally. This 360-pin AI core board also includes board-to-board connectors for interfacing with an external baseboard, such as... Figure 1 and 2 As shown, the processor 2, power management module 3 and memory are located on the upper side of PCB board 1, and the board-to-board connector is located on the lower side of PCB board 1. This layout is relatively reasonable and facilitates the docking of the 360-pin AI core board with the baseboard.

[0028] like Figure 1 and2 As shown, the board-to-board connectors in this 360-pin AI core board include board-to-board connector A7, board-to-board connector B8, board-to-board connector C9, and board-to-board connector D10. Board-to-board connectors A7, C9, B8, and D10 are respectively located on both sides of the bottom of PCB board 1. In this embodiment, board-to-board connectors A, B, C, and D have a total of 360 pins, which are used to configure multiple interfaces with different functions. Board-to-board connectors A and B have a bandwidth of 5Gbps, a pin pitch of 0.5mm, and a height of 3mm; board-to-board connectors C and D have a bandwidth of 10Gbps, a pin pitch of 0.5mm, and a height of 3mm, to facilitate the arrangement of corresponding functional interfaces.

[0029] Each interface with different functions is composed of a variable number of pins, and each pin has its own specific function in an interface. In this embodiment, these data interfaces include RGMII interface, SDMMC interface, ADC interface, MIPI_DSI interface, eDP interface, USB interface, PCIe interface, Type-C interface, HDMI interface, MIPI_CSI interface, SDIO interface, I2S interface, I2C interface, SPI interface, UART interface, and GPIO interface.

[0030] The functions of each interface are as follows: the RGMII interface is used to connect the Gigabit Ethernet controller to the physical layer, switches, routers, etc.; the SDMMC interface is used to connect TF or SD cards; the ADC interface is used to acquire analog signals and can connect to devices such as microphones, temperature and humidity sensors, and pressure sensors; the MIPI_DSI interface is used to transmit image data from mobile devices to display devices; the eDP interface can be used to connect to the LCD screen of computers, monitors, etc. The eDP interface can transmit high-resolution video signals and also supports audio transmission and control signals.

[0031] The Type-C interface can be used for data transfer, charging, video output, and peripheral connection. The MIPI_CSI interface can be used to connect to a display screen, or it can be converted to an HDMI interface through a converter chip. The HDMI interface is another type of display screen interface. The USB interface can be used to connect devices such as USB flash drives and mice. The PCIe interface is used to connect internal components of electronic devices such as graphics cards, network cards, and sound cards. The MIPI_CSI interface is used to connect camera modules.

[0032] The SDIO interface is used to connect Wi-Fi modules, Bluetooth modules, GPS receiver modules, etc.; the SPI interface is used to connect the processor to external devices such as memory, clock, AD converter, digital signal processor, and decoder; the I2S interface (I2S can also be written as IIS, I...) 2 S) is used to transmit audio signals; IIC interface (here, IIC can also be written as I2C, I... ... 2 C) Both UART interfaces are universal communication protocol interfaces that can be used to connect to many devices, such as laptops, ID card readers, OLED displays, RTC modules, etc., and have a wide range of applications.

[0033] GPIO interfaces can simulate most of the hardware interfaces mentioned above through software. They cannot simulate USB or ADC interfaces, but they can simulate IIC, UART, and other interfaces. One GPIO is one pin. When using GPIO to simulate other interfaces, multiple GPIOs may need to work together to simulate them. GPIO interfaces are the most common chip pin resources.

[0034] The board-to-board connector is also equipped with a power input interface and a power output interface. The power input interface is used to input power to the core board; the power output interface is the interface for the core board to output power to the outside.

[0035] Specifically, the 360 ​​pins of this 360-pin AI core board are led out through four board-to-board connectors. Board-to-board connectors A7 and B8 are each 80 pins, and board-to-board connectors C9 and D10 are each 100 pins. The correspondence between the terminals of these interfaces and the pins of board-to-board connectors A7, B8, C9, and D10 is shown in Tables 1 to 4 below. In the tables, A indicates that the pin is on board-to-board connector A7, B indicates that the pin is on board-to-board connector B8, C indicates that the pin is on board-to-board connector C9, and D indicates that the pin is on board-to-board connector D10. "CPU pin" refers to which pin of the core board is directly connected to the processor, and "--" indicates that the core board pin is not connected to the CPU.

[0036] All core board pins have their functions defined by the "Default Functions" in Tables 1 to 4 below. For example, in Table 1, AK27 represents the pin numbered AK27 on processor 2, and the AK27 pin is electrically connected to pin numbered 3 on board-to-board connector A7. Core board pins represent pins on board-to-board connectors A7, B8, C9, and D10. For example, A3 represents pin numbered 3 on board-to-board connector A7, which is the reset pin of the MIPIDSI1 interface.

[0037] The power input interface is constructed via pins A67, A68, A69, A70, A71, A72, A73, A74, A75, A76, A77, A78, A79, and A80 of board-to-board connector A7.

[0038] The power output interface can be configured as needed using unused GPIO function pins;

[0039] The RGMII interface is constructed using pins D64, D66, D68, D70, D72, D73, D74, D75, D79, D81, D89, D91, D93, D95, D97, and D99 on the board-to-board connector D10.

[0040] The SDMMC interface is constructed using pins A11, A13, A15, A17, A19, A21, and A23 of board-to-board connector A7.

[0041] The ADC interface is constructed via pins A20, A22, A28, A30, and A32 of board-to-board connector A7;

[0042] The MIPI_DSI interface is constructed through pins A3 and A27 of board-to-board connector A, pins B57 and B61 of board-to-board connector B, and pins C41, C43, C45, C47, C49, C51, C53, C55, C57, C59, C63, C65, C67, C69, C71, C73, C75, C77, C79, and C81 of board-to-board connector C.

[0043] The eDP interface is constructed using pins C1, C3, C5, C7, C9, C11, C13, C15, C17, C19, C82, C84, C86, C88, C90, C92, C94, C96, C98, and C100 of the board-to-board connector C.

[0044] The USB interface is formed by pins A36, A38, A44, and A46 of board-to-board connector A;

[0045] The PCIe interface is constructed using pins A31, A33, and A35 of board-to-board connector A; pins B24, B34, B60, B76, B79, and B80 of board-to-board connector B; and pins D3, D5, D7, D9, D11, D13, D17, D19, D21, D23, D25, D27, D31, D33, D35, D37, D39, D41, D4, D6, D10, D12, D16, D18, D22, D24, D28, D30, D34, D36, D40, D42, D46, D48, D52, D54, D58, and D60 of board-to-board connector D.

[0046] The Type-C interface is formed by pins A5, A7, A40, A42, A50, and A52 of board-to-board connector A, pins C2, C4, C6, C8, C10, C12, C14, C16, C72, C74, C76, C78, ​​C85, C87, C91, and C93 of board-to-board connector C, and pins D83 and D85 of board-to-board connector D.

[0047] The HDMI interface is constructed through pins A4, A14, A26, A34, A39, A45, A47, A49, A51, A53, and A55 of board-to-board connector A, pins B77, B32, B40, and B70 of board-to-board connector B, and pins C23, C25, C27, C29, C31, C33, C35, and C37 of board-to-board connector C.

[0048] The MIPI_CSI interface is accessed via pin A37 of board-to-board connector A, pins B55, B18, B20, B22, B26, B36, B44, B50, B58, B62, and B64 of board-to-board connector B, and pins C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C42, C44, and C4 of board-to-board connector C. 6. Pins C48, C50, C52, C54, C56, C58, and C60 constitute the board-to-board connector D, specifically pins D45, D47, D49, D51, D53, D55, D59, D61, D63, D65, D67, D69, D78, D80, D82, D84, D86, D88, D90, D92, D94, D96, D98, and D100.

[0049] The SDIO interface is constructed using pins A11, A13, A15, A17, A19, A21, and A23 of board-to-board connector A.

[0050] The I2S interface is formed by pins B2, B4, B6, B8, and B10 of the board-to-board connector B.

[0051] The I2C interface is formed by pins A6 and A8 of board-to-board connector A and pins B49, B51, B54, B56, B66, and B68 of board-to-board connector B.

[0052] The UART interface is constructed through pins B69, B71, B14, B16, B38, and B42 of the board-to-board connector B.

[0053] Several reusable GPIO pins are provided on board-to-board connector A, board-to-board connector B and board-to-board connector D. The SPI interface and GPIO interface are composed of the corresponding GPIO pins.

[0054] Table 1. Pin Descriptions of Board-to-Board Connector A

[0055]

[0056]

[0057]

[0058]

[0059]

[0060] Table 2. Pin Descriptions of Board-to-Board Connector B

[0061]

[0062]

[0063]

[0064]

[0065] Table 3. Board-to-board connector C-pin description

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072] Table 4. Pin Descriptions of Board-to-Board Connector D-Socket

[0073]

[0074]

[0075]

[0076]

[0077]

[0078] The 360-pin AI core board in this embodiment features a comprehensive array of interfaces, including a power input interface, a power output interface, an RGMII interface, an SDMMC interface, an ADC interface, a MIPI_DSI interface, an eDP interface, a USB interface, a PCIe interface, a Type-C interface, an HDMI interface, a MIPI_CSI interface, an SDIO interface, an I2S interface, an I2C interface, an SPI interface, a UART interface, and a GPIO interface. Based on the Rockchip RK3588 processor, it boasts powerful video encoding and decoding capabilities, supporting 8K multi-format encoding and decoding. It exhibits high computational efficiency, excellent graphics processing, and significant AI computing advantages. Supporting multi-channel display and high-performance peripheral interfaces, it comes with a complete development kit. As an independent module embedded in a system, it saves development time, reduces risk, and accelerates time-to-market. With strong practicality and cost-effectiveness in the field of AIoT, it has significant promotional value.

[0079] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A 360-pin AI core board, comprising a PCB board, wherein the PCB board is provided with a processor, a power management module and a memory, and a board-to-board connector for interfacing with an external baseboard, characterized in that: The board-to-board connector has 360 pins, which correspond to multiple interfaces with different functions. These interfaces include a power input interface, a power output interface, an RGMII interface, an SDMMC interface, an ADC interface, a MIPI_DSI interface, an eDP interface, a USB interface, a PCIe interface, a Type-C interface, an HDMI interface, a MIPI_CSI interface, an SDIO interface, an I2S interface, an I2C interface, an SPI interface, a UART interface, and a GPIO interface.

2. The 360-pin AI core board according to claim 1, characterized in that: The board-to-board connectors include board-to-board connector A, board-to-board connector B, board-to-board connector C, and board-to-board connector D. Board-to-board connector A, board-to-board connector C, board-to-board connector B, and board-to-board connector D are respectively located on both sides of the bottom of the PCB board.

3. The 360-pin AI core board according to claim 1, characterized in that: Board-to-board connector A and board-to-board connector B each have 80 pins; board-to-board connector C and board-to-board connector D each have 100 pins.

4. The 360-pin AI core board according to claim 3, characterized in that: The board-to-board connector A has 80 pins, designated A1 to A80; the board-to-board connector B has 80 pins, designated B1 to B80; the board-to-board connector C has 100 pins, designated C1 to C100; and the board-to-board connector D has 100 pins, designated D1 to D100. Wherein: The power input interface is constructed through pins A67, A68, A69, A70, A71, A72, A73, A74, A75, A76, A77, A78, A79, and A80 of board-to-board connector A; The RGMII interface is constructed through pins D64, D66, D68, D70, D72, D73, D74, D75, D79, D81, D89, D91, D93, D95, D97, and D99 on the board-to-board connector D. The SDMMC interface is constructed using pins A11, A13, A15, A17, A19, A21, and A23 of board-to-board connector A. The ADC interface is constructed via pins A20, A22, A28, A30, and A32 of board-to-board connector A; The MIPI_DSI interface is constructed through pins A3 and A27 of board-to-board connector A, pins B57 and B61 of board-to-board connector B, and pins C41, C43, C45, C47, C49, C51, C53, C55, C57, C59, C63, C65, C67, C69, C71, C73, C75, C77, C79, and C81 of board-to-board connector C. The eDP interface is constructed through pins C1, C3, C5, C7, C9, C11, C13, C15, C17, C19, C82, C84, C86, C88, C90, C92, C94, C96, C98, and C100 of the board-to-board connector C. The USB interface is formed by pins A36, A38, A44, and A46 of the board-to-board connector A; The PCIe interface is constructed via pins A31, A33, and A35 of board-to-board connector A, pins B24, B34, B60, B76, B79, and B80 of board-to-board connector B, and pins D3, D5, D7, D9, D11, D13, D17, D19, D21, D23, D25, D27, D31, D33, D35, D37, D39, D41, D4, D6, D10, D12, D16, D18, D22, D24, D28, D30, D34, D36, D40, D42, D46, D48, D52, D54, D58, and D60 of board-to-board connector D. The Type-C interface is constructed via pins A5, A7, A40, A42, A50, and A52 of board-to-board connector A, pins C2, C4, C6, C8, C10, C12, C14, C16, C72, C74, C76, C78, ​​C85, C87, C91, and C93 of board-to-board connector C, and pins D83 and D85 of board-to-board connector D. The HDMI interface is constructed via pins A4, A14, A26, A34, A39, A45, A47, A49, A51, A53, and A55 of board-to-board connector A, pins B77, B32, B40, and B70 of board-to-board connector B, and pins C23, C25, C27, C29, C31, C33, C35, and C37 of board-to-board connector C. The MIPI_CSI interface is accessed via pin A37 of board-to-board connector A, pins B55, B18, B20, B22, B26, B36, B44, B50, B58, B62, and B64 of board-to-board connector B, and pins C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C42, C44, C46, ​​and C46 of board-to-board connector C.

8. Pins C50, C52, C54, C56, C58, and C60, and pins D45, D47, D49, D51, D53, D55, D59, D61, D63, D65, D67, D69, D78, D80, D82, D84, D86, D88, D90, D92, D94, D96, D98, and D100 of the board-to-board connector D; The SDIO interface is constructed through pins A11, A13, A15, A17, A19, A21, and A23 of board-to-board connector A; The I2S interface is formed by pins B2, B4, B6, B8, and B10 of the board-to-board connector B. The I2C interface is constructed through pins A6 and A8 of board-to-board connector A and pins B49, B51, B54, B56, B66, and B68 of board-to-board connector B. The UART interface is constructed via pins B69, B71, B14, B16, B38, and B42 of the board-to-board connector B. Board-to-board connector A, board-to-board connector B, and board-to-board connector D are provided with several reusable GPIO pins, and the SPI interface, GPIO interface, and power output interface are composed of the reusable GPIO pins.

5. The 360-pin AI core board according to claim 4, characterized in that: The board-to-board connectors A and B have a bandwidth of 5Gbps, a pin pitch of 0.5mm, and a height of 3mm; the board-to-board connectors C and D have a bandwidth of 10Gbps, a pin pitch of 0.5mm, and a height of 3mm.

6. The 360-pin AI core board according to claim 1, characterized in that: The processor, power management module, and memory are located on one side of the PCB board, and the board-to-board connector is located on the other side of the PCB board.

7. The 360-pin AI core board according to claim 1, characterized in that: The processor is an RK3588 processor.

8. The 360-pin AI core board according to claim 1, characterized in that: The storage device includes a memory module and a secondary storage module.

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