Voltage displacement driving circuit
By designing a voltage displacement drive circuit, the design difficulties of traditional level conversion circuits in switching between different voltage domains were solved, achieving the effects of voltage polarity conversion and power consumption reduction.
Patent Information
- Application Number
- CN202322974753.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-03
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2033-11-03
Smart Images
Figure CN223899209U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, specifically, a voltage displacement driving circuit. Background Technology
[0002] Traditional level conversion circuits transform one voltage to another, typically with the same voltage polarity, differing only in voltage level. In contrast, the level shift conversion circuit of this invention transforms two or more voltage domains. That is, the input is a voltage range of one polarity, and the output is a voltage range of the opposite polarity. For example, if the input voltage is zero to a low positive voltage, the output voltage may be zero to a high negative voltage. The circuit's supply voltage is also zero and negative. Designing such voltage conversion circuits in chip design is generally quite difficult. The technology claimed in this application was designed to solve this technical problem. Summary of the Invention
[0003] The purpose of this invention is to design a voltage displacement driving circuit that can complete real-time driving from input to output under different voltage polarities, and to meet the driving transformation of signals generated from the positive voltage domain to the negative voltage domain in certain applications.
[0004] This utility model is achieved through the following technical solution: a voltage displacement driving circuit, including an input amplifier circuit, an inverter, and an output conversion circuit, wherein the input amplifier circuit is connected to the inverter and the output conversion circuit, and the inverter is connected to the output conversion circuit; the output conversion circuit includes a signal amplifier circuit, a clamping circuit, a positive feedback circuit, and an output driving circuit, wherein the signal amplifier circuit is connected to the input amplifier circuit, the inverter, the clamping circuit, and the output driving circuit respectively, the clamping circuit is connected to the positive feedback circuit and the output driving circuit respectively, and the positive feedback circuit is connected to the output driving circuit.
[0005] To further improve the voltage displacement driving circuit described in this utility model, the following configuration is specifically adopted: the signal amplification circuit includes a first amplification tube, a second amplification tube, a third amplification tube, and a fourth amplification tube. The first ends of the first, second, third, and fourth amplification tubes are all connected together. The second ends of the second and fourth amplification tubes are directly connected to the input amplification circuit. The second ends of the first and third amplification tubes are connected to the input amplification circuit through an inverter. The third ends of the first and second amplification tubes are connected to a clamping circuit, and the third ends of the third and fourth amplification tubes are connected to an output driving circuit.
[0006] To further improve the voltage displacement driving circuit described in this utility model, the following configuration is adopted: the first ends of the first amplifier tube, the second amplifier tube, the third amplifier tube, and the fourth amplifier tube are all connected to a power supply.
[0007] To further improve the voltage displacement driving circuit described in this utility model, the following configuration structure is specifically adopted: the output driving circuit includes a first output transistor and a second output transistor. The first end of the first output transistor is connected to a signal amplification circuit and forms a first output terminal. The second end of the first output transistor is connected to a clamping circuit and a positive feedback circuit. The third end of the first output transistor is connected to the third end of the second output transistor and connected to a second low level. The first end of the second output transistor is connected to a signal amplification circuit and forms a second output terminal. The second end of the second output transistor is also connected to a clamping circuit and a positive feedback circuit.
[0008] To further improve the voltage displacement driving circuit described in this utility model, the following configuration structure is adopted: the clamping circuit includes a first clamping transistor and a second clamping transistor. The first end of the first clamping transistor is connected to a signal amplification circuit, the first end of the second clamping transistor is connected to a signal amplification circuit, the second ends of both the first and second clamping transistors are connected to a third bias voltage, the third end of the first clamping transistor is connected to a positive feedback circuit and an output driving circuit, and the third end of the second clamping transistor is connected to both a positive feedback circuit and an output driving circuit.
[0009] To further improve the voltage displacement driving circuit described in this utility model, the following configuration structure is adopted: the positive feedback circuit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the second terminal of the second transistor, the clamping circuit (the third terminal of the first clamping transistor), and the output driving circuit. The first terminal of the second transistor is connected to the clamping circuit (the third terminal of the second clamping transistor), the second terminal of the first transistor, and the output driving circuit. The third terminals of the first transistor and the second transistor are connected together and connected to the second low level.
[0010] To further improve the voltage displacement driving circuit described in this utility model, the following configuration structure is adopted: the input amplifier circuit includes a first input transistor and a second input transistor. The first end of the first input transistor is connected to the input signal, the second end of the first input transistor is connected to the first bias voltage, the third end of the first input transistor is connected to the input end of the inverter, the first end of the second input transistor and the signal amplifier circuit, the second end of the second input transistor is connected to the second bias voltage, and the third end of the second input transistor is connected to the first low level.
[0011] To further improve the voltage displacement driving circuit described in this utility model, the following configuration is adopted: the output terminal of the inverter is connected to a signal amplification circuit, and the inverter is also connected to a power supply and a first low level.
[0012] Compared with the prior art, this utility model has the following advantages and beneficial effects:
[0013] Firstly, this invention realizes a voltage displacement driving circuit that can complete real-time driving from input to output when the input and output voltage polarities are different. It also satisfies the driving transformation of signals generated from the positive voltage domain to the negative voltage domain in some applications.
[0014] This invention can reduce the logic value of the input voltage VIN to "0" (when VIN - Vb0). <V TH1 (when) or logic "1" (when VIN-Vb0>>V TH1 When VA is converted to the logic "0" (close to VSS1) and logic "1" (when VA > VDD - |VSS1) output at point VA, the logic is converted to the logic "1" (when VA > VDD - |VSS1) output at point VA. TH3 |Up to VIN), the logic level of VA is then converted to VSS1 to VDD to drive the next stage M2 and the last stage M5. When M2 or M3 is fully on, the gate voltage is close to VSS1, while when off, the gate voltage is greater than VDD-|V TH2 |or greater than VDD-|V TH3 | (where |V) TH2 |、|V TH3 | represents the absolute value of the threshold voltages of M2 and M3, where the maximum turn-off voltage of M2 is VDD and the maximum turn-off voltage of M3 is VIN. However, once turned off, it no longer affects the driving performance of M2 to M7 and M9 (the drain voltage of M9 at this time is close to VSS2), while the drain voltage of M3 to M8 and M10 at this time is close to Vb2-V. TH8 M7 and M8 are used as clamping circuits. This voltage can fully turn on the output transistor M11 of the next stage, thereby generating the corresponding output. M9 and M10 form a positive feedback circuit. When one MOSFET is turned on (for example, M9 is turned on), the other is completely turned off (at this time, M10 is turned off).
[0015] In this invention, only one power supply voltage VDD and two ground voltages VSS1 and VSS2 are used, but the input range has an additional VIN (when Vb0=VDD). The entire circuit does not need to provide a power supply voltage to VIN. VIN is an independent voltage, which is higher than VDD. Unlike traditional voltage level displacement drive circuits, each device can only work normally under a power supply voltage, thus simplifying the circuit structure and saving power consumption.
[0016] In this invention, the circuit operates in an environment with a large voltage difference, where VSS1 can be much higher than VSS2. Thus, when the input signal VIN changes, the gate voltages of MOSFETs M2 and M4 instantaneously become VSS1, and the gate voltages of M3 and M5 instantaneously become VDD-|V TH3The voltage change amplitude (with M3 and M5 off) is much smaller than VDD-VSS2, effectively reducing the instantaneous high power consumption at this node. Similarly, there are two NMOS transistors M7 and M8 in the branches M2 and M3. When M2 or M3 is on, to ensure that M7 and M8 are conducting while the gate voltages of M11 and M12 do not exceed a certain value, that is, M11: V G11 ≤ V b2 - V TH8 M12: V G12 ≤ V b2 - V TH7 This effectively reduces the instantaneous high power consumption of the gate voltages of M11 and M12.
[0017] In this invention, the voltage value of logic "1" in VIN can also be slightly smaller than the value of VDD, but it must satisfy VIN > VDD - |V TH2 |and VIN>VDD-|V TH3 |and VIN>VDD-|V TH4 |and VIN>VDD-|V TH5 Under normal circumstances, a logical "1" in VIN must ensure that M2, M3, M4, and M5 are in the off state.
[0018] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.
[0020] Figure 1 This is a typical circuit schematic diagram of this utility model.
[0021] Figure 2 This is one of the typical circuit schematics of this utility model.
[0022] Figure 3 This is the second typical circuit schematic diagram of this utility model.
[0023] Figure 4 This is the third typical circuit schematic diagram of this utility model. Detailed Implementation
[0024] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.
[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model. Therefore, the following detailed description of the embodiments of this utility model provided in the accompanying drawings is not intended to limit the scope of the claimed utility model, but merely to represent selected embodiments of this utility model.
[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.
[0027] In the description of this utility model, it should be understood that the orientation or positional relationship indicated by terms, etc., is based on the orientation or positional relationship shown in the drawings and is only for the convenience of describing this utility model and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "multiple" means two or more, and "multiple" means two or more, unless otherwise explicitly specified.
[0029] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can also refer to an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0030] It should be noted that in some embodiments, the MOS transistor or MOSFET in the circuit can be replaced by other transistors that perform the same function. For example, the MOS transistor can be replaced by a bipolar transistor, silicon carbide (SiC) transistor, gallium nitride (GaN) transistor, cubic indium phosphide (InP) transistor, gallium arsenide (GaAs) transistor, field-effect transistor (FET), junction field-effect transistor (JFET), heterojunction bipolar transistor (HBT), or insulated-gate bipolar transistor (IGBT). Therefore, the MOS transistor structure in the above examples should not be construed as a limitation of this application.
[0031] Electronic devices can be devices that include circuits or apparatuses containing semiconductor devices, such as mobile phones, computers, televisions, communication devices, etc. The electronic devices provided in this application embodiment have the same implementation principle and technical effects as the high data flow transmission interface structure circuit embodiment described below. For the sake of brevity, any parts not mentioned in the electronic device embodiment can be referred to the corresponding content in the high data flow transmission interface structure circuit embodiment.
[0032] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0033] It can be replaced and can be implemented, wholly or partially, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, wholly or partially, in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this utility model are generated.
[0034] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, principle, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, principle, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, principle, article, or apparatus that includes said element.
[0035] This invention can be considered as a three-stage drive. The first stage involves inputting a positive voltage or a high voltage (VIN), which is in the positive voltage domain. This voltage is input from the source of NMOSFET M1. The gate of M1 is connected to a fixed potential Vb0, and the output is the drain of NMOSFET M1, which is connected to point A in Figure 1. Vb0 and the power supply voltage VDD of the subsequent two-stage level shift drive circuits can be connected together or form a fixed potential difference. M6 acts as the constant current source load for M1. Its gate is connected to voltage Vb1, its source is connected to VSS1 (the first low level), and its drain is connected to point A in Figure 1. The voltage at point A drives the two PMOSFETs M3 and M5 of the subsequent two-stage level shift drive circuits on one hand, and on the other hand, drives the two PMOSFETs M2 and M4 of the subsequent two-stage level shift drive circuits through an inverter (or a circuit with inverting function). The power supply and ground of this inverter are between the power supply voltages VDD and VSS1 of the subsequent two-stage level shift drive circuits. This creates a voltage transformation, converting the input voltage VIN to a range from VSS1 to Vb0 and VDD. The second stage of driving involves the voltage VA driving PMOSFET M3 and the inverter after VA driving PMOSFET M2. Since the voltage range of VA is between VIN and VSS1, and there is a fixed voltage difference or equality between Vb0 and VDD, VA can drive PMOSFETs M3 and M5 as the third stage of driving. Their turn-on and turn-off voltage range is between the maximum signal values of VSS1 and VIN. M2, M3, M7, M8, M9, and M10, located between VSS2 (the second low level) and VDD, form the second stage of driving. In this stage, M2 and M3 receive the signal input. M7 and M8 function as NMOSFETs with a voltage limit, their gate voltages connected to a reference voltage Vb2. This voltage, along with VSS2, is a fixed value that can be determined based on the specific application. They are primarily used for driving, and their on / off range is determined by the gate voltages of the subsequent drive transistors M11 and M12. The final drive stage consists of transistors M4, M5, M11, and M12. M9 and M10 form a hierarchical positive feedback structure, with the output voltage range between Vb2 and VSS2. TH7 (or Vb2-V) TH8 V TH7 With V TH8 These are the threshold voltages for M7 and M8, respectively. Vb2 is greater than V. TH7 +VDS9 or Vb2 is greater than V TH8(M7 and M8 only conduct after +VDS10) and VSS2 facilitate rapid output of high and low levels of VSS2 to drive M11 and M12. The final stage of the drive circuit, consisting of transistors M4, M5, M11, and M12, has a wide driving voltage range from VSS2 to VDD, outputting a large driving voltage to drive devices or subsequent circuits in our practical applications.
[0036] Example 1:
[0037] A voltage displacement driving circuit, such as Figure 1 As shown, it includes an input amplifier circuit, an inverter, and an output conversion circuit. The input amplifier circuit is connected to the inverter and the output conversion circuit, and the inverter is connected to the output conversion circuit. The output conversion circuit includes a signal amplifier circuit, a clamping circuit, a positive feedback circuit, and an output drive circuit. The signal amplifier circuit is connected to the input amplifier circuit, the inverter, the clamping circuit, and the output drive circuit, respectively. The clamping circuit is connected to the positive feedback circuit and the output drive circuit, respectively. The positive feedback circuit is connected to the output drive circuit.
[0038] In a preferred design, the input amplifier circuit is a source-input amplifier circuit, used as both an input signal level shifter and an input signal driver circuit to receive the input signal VIN. When used as an input signal level shifter, the input signal level VIN ranges from VSS0 (VSS0 is the minimum voltage of VIN, i.e., the external ground level) to VDD1 (VDD1 is the maximum voltage of VIN, i.e., the external power supply voltage level), and the output voltage range becomes VSS1 to VDD1. The inverter (i.e., a circuit with inverting function) converts the input signal (i.e., the output voltage signal of VIN) into a signal with a high level of VDD and a low level of VSS1, and a 180° phase difference from the input signal; it also functions as a level shifter. The output conversion circuit is used to achieve the desired output voltage.
[0039] The output conversion circuit mainly consists of four parts: a signal amplification circuit, a clamping circuit, a positive feedback circuit, and an output drive circuit. One signal from the signal amplification circuit is obtained from the output of the inverter and applied to the gate of transistor M2. The other signal is obtained from the output of the source input amplifier circuit, VA, and applied to the gate of transistor M3. These two signals are amplified by M2 and M3 respectively and then clamped to Vb2-V by M7 and M8. TH7 (or clamp to Vb2-V) TH8 Then, by connecting M9 and M10 to form positive feedback, the signals from M2 and M3 are further amplified to full amplitude. That is, when M9 is cut off, the drain voltage of M9 is Vb2-V. TH7This voltage will fully turn on M10, making its drain voltage close to or equal to VSS2; thus driving the gate voltage of M11 to VSS2, and the gate voltage of M12 to Vb2-V. TH7 This forms a differential output drive circuit, used to output the required voltage (between VSS2 and VDD).
[0040] Example 2:
[0041] This embodiment is a further optimization based on the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1 As shown, to further better realize the voltage displacement driving circuit described in this utility model, the following configuration structure is specifically adopted: the signal amplification circuit includes a first amplification tube, a second amplification tube, a third amplification tube, and a fourth amplification tube. The first ends of the first amplification tube, the second amplification tube, the third amplification tube, and the fourth amplification tube are all connected together. The second ends of the second amplification tube and the fourth amplification tube are directly connected to the input amplification circuit. The second ends of the first amplification tube and the third amplification tube are connected to the input amplification circuit through an inverter. The third ends of the first amplification tube and the second amplification tube are connected to a clamping circuit. The third amplification tube and the fourth amplification tube are connected to the output driving circuit. The first ends of the first amplification tube, the second amplification tube, the third amplification tube, and the fourth amplification tube are all connected to the power supply VDD.
[0042] As a preferred design, the signal amplification circuit is equipped with four amplification transistors (first amplification transistor M2, second amplification transistor M3, third amplification transistor M4, and fourth amplification transistor M5). Preferably, the first amplification transistor M2, second amplification transistor M3, third amplification transistor M4, and fourth amplification transistor M5 are all PMOS transistors. The sources of the first amplification transistor M2, second amplification transistor M3, third amplification transistor M4, and fourth amplification transistor M5 are all connected to a common power supply (high level) VDD. The gates of the second amplification transistor M3 and fourth amplification transistor M5 are directly connected to the input amplification circuit. The gates of the first amplification transistor M2 and third amplification transistor M4 are connected to the output terminal of inverter U1, and the input terminal of inverter U1 is connected to the input amplification circuit. The drains of the first amplification transistor M2 and second amplification transistor M3 are connected to the clamping circuit, and the drains of the third amplification transistor M4 and fourth amplification transistor M5 are connected to the output drive terminals out1 and out2.
[0043] Preferably, the first amplifying tube M2, the second amplifying tube M3, the third amplifying tube M4, and the fourth amplifying tube M5 can also be PNP transistors.
[0044] Example 3:
[0045] This embodiment is a further optimization based on any of the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1As shown, to further better realize the voltage displacement driving circuit of this utility model, the following configuration structure is specifically adopted: the output driving circuit includes a first output transistor and a second output transistor. The first end of the first output transistor is connected to the signal amplification circuit (the third end of the third amplification transistor) and forms the first output terminal (out1). The second end of the first output transistor is connected to the clamping circuit and the positive feedback circuit. The third end of the first output transistor is connected to the third end of the second output transistor and connected to the second low level VSS2. The first end of the second output transistor is connected to the signal amplification circuit (the third end of the fourth amplification transistor) and forms the second output terminal (out2). The second end of the second output transistor is also connected to the clamping circuit and the positive feedback circuit.
[0046] As a preferred design, the output drive circuit is mainly constructed from two output transistors (first output transistor M11 and second output transistor M12). Both the first output transistor M11 and the second output transistor M12 are NMOS transistors. The drain of the first output transistor M11 is connected to the drain of the third amplifier transistor M4 in the signal amplifier circuit and forms the first output terminal (out1). The gate of the first output transistor M11 is connected to the clamping circuit and the positive feedback circuit. The source of the first output transistor M11 is connected to the source of the second output transistor M12 and connected to the second low level VSS2. The drain of the second output transistor M12 is connected to the drain of the fourth amplifier transistor M5 in the signal amplifier circuit and forms the second output terminal (out2). The gate of the second output transistor M12 is also connected to the clamping circuit and the positive feedback circuit.
[0047] The preferred first output transistor M11 and the second output transistor M12 can also be NPN transistors.
[0048] Example 4:
[0049] This embodiment is a further optimization based on any of the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1 As shown, in order to better realize the voltage displacement driving circuit of this utility model, the following configuration structure is adopted: a second low level VSS2 is connected to the first output terminal (out1) and the second output terminal (out2) respectively through a capacitor load.
[0050] As a preferred design, the first output terminal (out1) is connected to the second low level VSS2 through capacitor C1, and the second output terminal (out2) is connected to the second low level VSS2 through capacitor C2, wherein capacitors C1 and C2 are used as loads in this circuit.
[0051] Example 5:
[0052] This embodiment is a further optimization based on any of the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1As shown, to further better realize the voltage displacement driving circuit of this utility model, the following configuration structure is specifically adopted: The clamping circuit includes a first clamping transistor (M7) and a second clamping transistor (M8). The first end of the first clamping transistor is connected to the signal amplification circuit (the third end of the first amplification transistor), and the first end of the second clamping transistor is connected to the signal amplification circuit (the third end of the second amplification transistor). The second ends of both the first clamping transistor and the second clamping transistor are connected to a third bias voltage. The third end of the first clamping transistor is connected to the positive feedback circuit (the second end of the second transistor and the first end of the first transistor) and the output driving circuit (the second end of the second output transistor), respectively. The third end of the second clamping transistor is connected to the positive feedback circuit (the second end of the first transistor and the first end of the second transistor) and the output driving circuit (the second end of the first output transistor), respectively.
[0053] As a preferred design, the clamping circuit is mainly constructed from two clamping transistors (first clamping transistor M7 and second clamping transistor M8). Preferably, the first clamping transistor M7 and the second clamping transistor M8 are NMOS transistors. The drain of the first clamping transistor M7 is connected to the drain of the first amplifying transistor M2 in the signal amplification circuit, and the drain of the second clamping transistor M8 is connected to the drain of the second amplifying transistor M3 in the signal amplification circuit. The gates of both the first clamping transistor M7 and the second clamping transistor M8 are connected to a third bias voltage Vb2. The source of the first clamping transistor M7 is connected to the positive feedback circuit (the gate of the second transistor M10 and the drain of the first transistor M9) and the gate of the second output transistor M12 in the output drive circuit, respectively. The source of the second clamping transistor M8 is connected to the positive feedback circuit (the gate of the first transistor M9 and the drain of the second transistor M10) and the gate of the first output transistor M11 in the output drive circuit, respectively.
[0054] Example 6:
[0055] This embodiment is a further optimization based on any of the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1 As shown, the positive feedback circuit includes a first transistor (M9) and a second transistor (M10). The first terminal of the first transistor is connected to the second terminal of the second transistor, the clamping circuit (the third terminal of the first clamping transistor), and the output driving circuit (the second terminal of the second output transistor). The first terminal of the second transistor is connected to the clamping circuit (the third terminal of the second clamping transistor), the second terminal of the first transistor, and the output driving circuit (the second terminal of the first output transistor). The third terminals of the first transistor and the second transistor are connected together and connected to the second low level VSS2.
[0056] As a preferred design, the positive feedback circuit is mainly constructed from two transistors (first transistor M9 and second transistor M10); wherein, the first transistor M9 and the second transistor M10 are preferably NMOS transistors; the drain of the first transistor M9 is connected to the gate of the second transistor M10, the source of the first clamping transistor M7 in the clamping circuit, and the gate of the second output transistor M12 in the output driving circuit, respectively; the drain of the second transistor M10 is connected to the source of the second clamping transistor M8 in the clamping circuit, the gate of the first transistor M9, and the gate of the first output transistor M11 in the output driving circuit, respectively; the sources of the first transistor M9 and the second transistor M10 are shared and connected to the second low level VSS2.
[0057] Preferably, the first clamping transistor M7, the second clamping transistor M8, the first transistor M9, and the second transistor M10 can also be NPN transistors.
[0058] Example 7:
[0059] This embodiment is a further optimization based on any of the above embodiments. The similarities with the aforementioned technical solutions will not be repeated here. Figure 1 As shown, to further better realize the voltage displacement driving circuit of this utility model, the following configuration structure is specifically adopted: the input amplification circuit includes a first input tube and a second input tube. The first end of the first input tube is connected to the input signal, the second end of the first input tube is connected to the first bias voltage, the third end of the first input tube is connected to the input end of the inverter, the first end of the second input tube and the signal amplification circuit (the second end of the second amplification tube and the second end of the fourth amplification tube), the second end of the second input tube is connected to the second bias voltage, and the third end of the second input tube is connected to the first low level VSS1.
[0060] As a preferred design, the input amplifier circuit is mainly constructed from two control transistors (first input transistor M1 and second input transistor M6). The first input transistor M1 is preferably a PMOS transistor, and the second input transistor M6 is preferably an NMOS transistor. The source of the first input transistor M1 is connected to the input signal VIN, and the gate of the first input transistor M1 is connected to the first bias voltage Vb0. The drain of the first input transistor M1 is connected to the input terminal of the inverter U1, the drain of the second input transistor M6, and the gates of the second amplifier transistor M3 and the fourth amplifier transistor M5 in the signal amplifier circuit. The gate of the second input transistor M6 is connected to the second bias voltage Vb1, and the source of the second input transistor M6 is connected to the first low level VSS1. The output terminal of the inverter U1 is connected to the gates of the first amplifier transistor M2 and the third amplifier transistor M4 in the signal amplifier circuit. The power supply pin of the inverter U1 is also connected to the power supply VDD, and the ground pin of the inverter U1 is connected to the first low level VSS1.
[0061] Preferably, the first input transistor M1 can also be a PNP transistor, and the second input transistor M6 can also be an NPN transistor.
[0062] Example 8:
[0063] A voltage displacement driving circuit includes a signal amplification circuit composed of four PMOS transistors (first amplification transistor M2, second amplification transistor M3, third amplification transistor M4, and fourth amplification transistor M5), an input amplification circuit composed of one PMOS transistor M1 and one NMOS transistor M6, an inverter U1, a clamping circuit composed of two clamping transistors (first clamping transistor M7 and second clamping transistor M8 using NMOS transistors), a positive feedback circuit composed of two transistors (first transistor M9 and second transistor M10 using NMOS transistors), an output driving circuit composed of two NMOS transistors as output transistors (first output transistor M11 and second output transistor M12), two capacitors (capacitor C1 and capacitor C2, serving as circuit load), a power supply (high level) VDD, an input signal VIN, a first low level VSS1, a second low level VSS2, a first bias voltage Vb0, a second bias voltage Vb1, and a third bias voltage Vb2.
[0064] The source of the first input transistor M1 is connected to the input signal VIN, and the gate of the first input transistor M1 is connected to the first bias voltage Vb0. The drain of the first input transistor M1 is connected to the input terminal of the inverter U1, the drain of the second input transistor M6, the gate of the second amplifier transistor M3, and the gate of the fourth amplifier transistor M5, respectively. The gate of the second input transistor M6 is connected to the second bias voltage Vb1, and the source of the second input transistor M6 is connected to the first low level VSS1. The output terminal of the inverter U1 is connected to the gate of the first amplifier transistor M2 and the gate of the third amplifier transistor M4. The power supply pin of the inverter U1 is connected to the power supply VDD, and the ground pin of the inverter U1 is connected to the first low level VSS1.
[0065] The sources of the first amplifier transistor M2, the second amplifier transistor M3, the third amplifier transistor M4, and the fourth amplifier transistor M5 are all connected to the same power supply VDD. The drain of the first amplifier transistor M2 is connected to the drain of the first clamping transistor M7. The drain of the second amplifier transistor M3 is connected to the drain of the second clamping transistor M8. The drain of the third amplifier transistor M4 is connected to the drain of the first output transistor M11 and forms the first output terminal (out1). The drain of the fourth amplifier transistor M5 is connected to the drain of the second output transistor M12 and forms the second output terminal (out2). The first output terminal (out1) is also connected to the second low level VSS2 through capacitor C1. The second output terminal (out2) is also connected to the second low level VSS2 through capacitor C2.
[0066] The gates of the first clamping transistor M7 and the second clamping transistor M8 are both connected to the third bias voltage Vb2. The source of the first clamping transistor M7 is connected to the gate of the second transistor M10, the drain of the first transistor M9, and the gate of the second output transistor M12, respectively. The source of the second clamping transistor M8 is connected to the gate of the first transistor M9, the drain of the second transistor M10, and the gate of the first output transistor M11, respectively. The sources of the first transistor M9, the second transistor M10, the first output transistor M11, and the second output transistor M12 are all connected to the second low level VSS2.
[0067] The PMOS transistor (first input transistor M1) and the NMOS transistor (second input transistor M6) form a source-input amplifier circuit, which is used as an input signal level shifter and input signal driver circuit to receive the input signal VIN. When used as an input signal level shifter, the input signal level VIN ranges from VSS0 (VSS0 is the minimum voltage of VIN, i.e., the external ground level) to VDD1 (VDD1 is the maximum voltage of VIN, i.e., the external power supply voltage level of VIN), and the output voltage range becomes VSS1 to VDD1. The second input transistor M6 can be a constant current source. The inverter converts the input signal (i.e., the output voltage signal of VIN) into a signal with a high level of VDD and a low level of VSS1, and a phase difference of 180° from the input signal; it also functions as a level shifter.
[0068] The PMOS transistor (first input transistor M1) and the NMOS transistor (second input transistor M6) together constitute the input amplifier circuit. The gate bias voltage of the first input transistor M1 (the first bias voltage Vb0 can be grounded) controls the conduction and turn-off of the second amplifier transistor M3 and the fourth amplifier transistor M5 by changing the gate-source voltage of the first input transistor M1. Furthermore, when the gate of the first input transistor M1 (with its gate grounded) changes, the input signal VIN changes according to the condition 0~V... TH1 (V) TH1 When the threshold voltage of transistor M1 is reached, the first input transistor M1 is in the off state, and the gate voltages of the second amplifier transistor M3 and the fourth amplifier transistor M5 are pulled to VSS1. At this time, the gate voltages of the first amplifier transistor M2 and the third amplifier transistor M4 are controlled to VDD by the output of the input signal VIN through inverter U1. The width-to-length ratio (W / L) of the second input transistor M6 and its bias voltage (second bias voltage Vb1) control the power consumption of this branch (i.e., the input amplifier circuit).
[0069] The first amplifier transistors M2 through M5 serve as intermediate stage signal amplifiers. Simultaneously, the first amplifier transistor M2, the second amplifier transistor M3, the first clamping transistor M7, the second clamping transistor M8, the first transistor M9, and the second transistor M10 form a level shifting circuit. The first clamping transistor M7 and the second clamping transistor M8 can clamp the gate voltages of the first output transistor M11 and the second output transistor M12 to a limited value (Vb2 - V). TH7 and Vb2-V TH8 ), where V TH7 and V TH8 These are the threshold voltages for the first clamping transistor M7 and the second clamping transistor M8, respectively; the first transistor M9 and the second transistor M10 form a positive feedback structure (positive feedback circuit), which can improve the circuit's response speed; the third amplifying transistor M4, the fourth amplifying transistor M5, the first output transistor M11, and the second output transistor M12 are used as output drivers.
[0070] On the output conversion circuit side:
[0071] When the input signal VIN is high, the second amplifier M3 and the fourth amplifier M5 are turned off, and the first amplifier M2 and the third amplifier M4 are turned on. As a result, the drains of the first amplifier M2 and the third amplifier M4 are pulled to high level, and the first output terminal (out1) outputs high (VDD). Meanwhile, the branch of the first amplifier M2 (which is composed of M2, M7, and M9) connected to the gate of the second output transistor M12 is at a high level, so the second output terminal (out2) outputs low (VSS2).
[0072] When the input signal VIN is low, the second amplifier M3 and the fourth amplifier M5 are turned on, and the first amplifier M2 and the third amplifier M4 are turned off. As a result, the drains of the second amplifier M3 and the fourth amplifier M5 are pulled to a high level, and the second output terminal (out2) outputs high (VDD). Meanwhile, the branch of the second amplifier M3 (which is composed of M3, M8, and M10) connected to the gate of the first output transistor M11 is at a high level, so the first output terminal (out1) outputs low (VSS2).
[0073] When the circuit operates in an environment with a large voltage difference, VSS1 can be much higher than VSS2. Thus, when the input signal VIN changes, the gate voltages of the first amplifier M2, the second amplifier M3, the third amplifier M4, and the fourth amplifier M5 are VSS1, effectively reducing the high power consumption during the instantaneous output pull-up process (due to the small voltage change range). Similarly, under the branches of the first amplifier M2 and the second amplifier M3, there are two NMOS transistors (M7 and M9 on the M2 branch, and M8 and M10 on the M3 branch). When the first amplifier M2 or the second amplifier M3 is turned on, to ensure that the first clamping transistor M7 and the second clamping transistor M8 are conducting while the gate voltages of the first output transistor M11 and the second output transistor M12 do not exceed a certain value, i.e., M11: V G11 ≤ V b2 - V TH8 M12: V G12 ≤ V b2 - V TH7 ;in V TH8 This is the threshold voltage for the second clamping transistor M8. V TH7 (This is the threshold voltage of the first clamping transistor M7).
[0074] This effectively reduces the high power consumption during the instantaneous output pull-down process.
[0075] Example 9:
[0076] This embodiment is a variation of the circuit disclosed in Embodiment 8. The similarities with the technical solution of Embodiment 8 will not be repeated here. Figure 2 As shown, in this circuit structure, two (but not limited to) diodes are connected in series between the drain of the first input transistor M1 and the drain of the second input transistor M6, and the negative terminal of the diode serves as the common connection point (point A) of the drain of the second input transistor M6, the input terminal of the inverter, and the gate of the second amplifier transistor M3.
[0077] Example 10:
[0078] This embodiment is a variation of the circuit disclosed in Embodiment 8. The similarities with the technical solution of Embodiment 8 will not be repeated here. Figure 3As shown, in this circuit structure, two (but not limited to) field-effect transistors (FETs) are connected between the drain of the first input transistor M1 and the drain of the second input transistor M6. These two FETs are FET M13 and FET M14, respectively. The source of FET M13 is connected to the drain of the first input transistor M1. The gate and drain of FET M13 are connected together and connected to the source of FET M14. The gate and drain of FET M14 are connected together and serve as the common connection point (point A) of the drain of the second input transistor M6, the input terminal of the inverter, and the gate of the second amplifier transistor M3.
[0079] Example 11:
[0080] This embodiment is a variation of the circuit disclosed in Embodiment 8. The similarities with the technical solution of Embodiment 8 will not be repeated here. Figure 4 As shown, in this circuit structure, the inverter is removed, and two (but not limited to) field-effect transistors (FETs) are added. These two FETs are FET M13 and FET M14. The source of FET M13 is connected to VDD, and the gate of FET M13 is connected to point A (the drain of the first input transistor M1 and the drain of the second input transistor M6). The drains of FET M13 and FET M14 are connected together and connected to the gates of the first amplifier transistor M2 and the third discharge transistor M4. The gate of FET M14 is connected to the gate of the second input transistor M6, and the source of FET M14 is connected to VSS1.
[0081] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model are within the protection scope of the present utility model.
Claims
1. A voltage displacement driving circuit, characterized in that: The system includes an input amplifier circuit, an inverter, and an output conversion circuit. The input amplifier circuit is connected to the inverter and the output conversion circuit, and the inverter is connected to the output conversion circuit. The output conversion circuit includes a signal amplifier circuit, a clamping circuit, a positive feedback circuit, and an output drive circuit. The signal amplifier circuit is connected to the input amplifier circuit, the inverter, the clamping circuit, and the output drive circuit, respectively. The clamping circuit is connected to the positive feedback circuit and the output drive circuit, respectively. The positive feedback circuit is connected to the output drive circuit.
2. The voltage displacement driving circuit according to claim 1, characterized in that: The signal amplification circuit includes a first amplifying transistor, a second amplifying transistor, a third amplifying transistor, and a fourth amplifying transistor. The first terminals of the first, second, third, and fourth amplifying transistors are all connected together. The second terminals of the second and fourth amplifying transistors are directly connected to the input amplification circuit. The second terminals of the first and third amplifying transistors are connected to the input amplification circuit through an inverter. The third terminals of the first and second amplifying transistors are connected to a clamping circuit, and the third terminals of the third and fourth amplifying transistors are connected to an output driving circuit.
3. The voltage displacement driving circuit according to claim 2, characterized in that: The first end of the first amplifying tube, the second amplifying tube, the third amplifying tube, and the fourth amplifying tube are all connected to a power source.
4. The voltage displacement driving circuit according to claim 1, characterized in that: The output driving circuit includes a first output transistor and a second output transistor. The first end of the first output transistor is connected to a signal amplification circuit and forms a first output terminal. The second end of the first output transistor is connected to a clamping circuit and a positive feedback circuit. The third end of the first output transistor is connected to the third end of the second output transistor and connected to a second low level. The first end of the second output transistor is connected to a signal amplification circuit and forms a second output terminal. The second end of the second output transistor is also connected to a clamping circuit and a positive feedback circuit.
5. The voltage displacement driving circuit according to claim 1, characterized in that: The clamping circuit includes a first clamping transistor and a second clamping transistor. The first end of the first clamping transistor is connected to a signal amplification circuit, and the first end of the second clamping transistor is also connected to a signal amplification circuit. The second ends of both the first and second clamping transistors are connected to a third bias voltage. The third end of the first clamping transistor is connected to a positive feedback circuit and an output drive circuit, respectively. The third end of the second clamping transistor is also connected to a positive feedback circuit and an output drive circuit, respectively.
6. The voltage displacement driving circuit according to claim 1, characterized in that: The positive feedback circuit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the second terminal of the second transistor, a clamping circuit, and an output driving circuit. The first terminal of the second transistor is connected to the clamping circuit, the second terminal of the first transistor, and the output driving circuit. The third terminals of the first transistor and the second transistor are connected together and connected to a second low level.
7. The voltage displacement driving circuit according to claim 1, characterized in that: The input amplifier circuit includes a first input transistor and a second input transistor. The first end of the first input transistor is connected to the input signal, the second end of the first input transistor is connected to the first bias voltage, the third end of the first input transistor is connected to the input end of the inverter, the first end of the second input transistor and the signal amplifier circuit, the second end of the second input transistor is connected to the second bias voltage, and the third end of the second input transistor is connected to the first low level.
8. The voltage displacement driving circuit according to claim 1, characterized in that: The output of the inverter is connected to a signal amplification circuit, and the inverter is also connected to a power supply and a first low level.