Packaging structure for medium-high power element

Abstract

The utility model discloses a packaging structure for medium and high power elements, which comprises a chip, a first pin and a second pin which are arranged in a packaging body, the first pin and the second pin are respectively electrically connected with the chip, and the first pin and the second pin partially extend outwards from the packaging body. The first pin is provided with a heat dissipation part used for dissipating heat outwards and upwards, and the heat dissipation part is located on the upper side of the chip and exposed out of the upper surface of the packaging body. The heat dissipation component is arranged on the pin, and the heat dissipation component is exposed from the upper surface of the packaging body, so that heat energy generated when the chip works is guided to be discharged upwards through the heat dissipation component, and junction temperature rise is effectively reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging, and in particular to a packaging structure for medium- and high-power components. Background Technology

[0002] Chinese utility model patent application CN222190713U discloses a high-power surface-mount diode. This diode employs a conventional packaging structure with the heat dissipation and heat conduction structure located at the bottom of the package. This is because, in traditional solutions, the majority of the heat dissipated during semiconductor operation is conducted to the PCB, forming a hot air field on the PCB surface. The air field then drives airflow on the PCB surface to achieve an overall cooling effect.

[0003] In fact, due to the smaller size, increased density, and higher power of components, the junction temperature rises higher under the original heat dissipation structure. The heat of the components cannot be dissipated in time, affecting their operational stability and lifespan. Utility Model Content

[0004] In order to overcome the above-mentioned defects of the prior art, the purpose of this utility model is to provide a packaging structure for medium and high power components to improve the heat dissipation efficiency of semiconductors.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0006] A package structure for medium-to-high power components includes a chip, a first pin, and a second pin disposed within the package. The first pin and the second pin are electrically interconnected with the chip. The first pin and the second pin extend outward from the package. The first pin has a heat dissipation component for dissipating heat outward and upward. The heat dissipation component is located on the upper side of the chip and exposed on the upper surface of the package.

[0007] In a preferred embodiment of the present invention, the first pin is further provided with at least one pair of bosses for assisting the mold in positioning during the molding process.

[0008] In a preferred embodiment of the present invention, the first pin includes a bend.

[0009] In a preferred embodiment of the present invention, the at least one pair of bosses includes a pair of first bosses, which are positioned opposite each other at the distal end of the heat dissipation component.

[0010] In a preferred embodiment of the present invention, the at least one pair of bosses further includes a pair of second bosses, the pair of second bosses being positioned opposite each other at the proximal end of the heat dissipation component.

[0011] In a preferred embodiment of the present invention, the first pin and / or the second pin have at least one pin for electrical connection to an external device.

[0012] In a preferred embodiment of this invention, the chip is a diode or a transistor.

[0013] In a preferred embodiment of this utility model, the packaging structure is a surface mount package.

[0014] The beneficial effects of this utility model are as follows:

[0015] The packaging structure for medium-to-high power components provided by this utility model effectively reduces junction temperature rise by setting heat dissipation components on the pins and exposing the heat dissipation components from the upper surface of the package. This allows the heat generated during chip operation to be discharged upward through the heat dissipation components. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0017] Figure 1 This is the top axial side view of this utility model.

[0018] Figure 2 yes Figure 1 A perspective view (the dashed lines in the figure represent the internal elements after perspective).

[0019] Figure 3 This is a schematic diagram of the first pin in the first implementation method.

[0020] Figure 4 This is the top side view of the second embodiment.

[0021] Figure 5 This is a schematic diagram of the first pin in the second implementation method. Detailed Implementation

[0022] In the description of this utility model, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. The above description is for the purpose of simplifying the description of this utility model and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model.

[0023] Exemplary embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that this application can be presented in many different ways and is not limited to the embodiments described below. It should also be understood that the embodiments disclosed herein can be combined in various ways to provide further additional embodiments. Throughout the drawings, the same reference numerals denote the same or functionally identical elements.

[0024] Figure 1 and Figure 2 A packaging structure for improving the heat dissipation efficiency of power components is demonstrated. This structure includes a chip 40 disposed within a package 10, and a first pin 20 and a second pin 30 for electrical connection to the chip 40. The first pin 20 and the second pin 30 extend outward from the package 10 for connection to external devices such as a PCB board. In one embodiment, the first pin 20 and the second pin 30 may have multiple pins 22 for connection to external devices. Further, a third pin or a fourth pin may be provided. These are all conventional configurations in the art and will not be elaborated further. Preferably, the package 10 is made of epoxy resin; the first pin 20 and the second pin 30 are made of copper foil.

[0025] The first pin 20 extends to the upper part of the chip 40 and is connected thereto. The first pin 20 has a heat dissipation component 21 placed on the upper part of the chip 40, and the heat dissipation component 21 is exposed from the upper surface of the package 10, thereby guiding the heat generated by the chip 40 during operation to be discharged upward through the heat dissipation component 21, reducing the junction temperature rise.

[0026] Reference Figure 3 Since the heat dissipation component 21 is exposed over a large area on the upper surface of the package 10 in the above scheme, multiple pairs of bosses are set on the heat dissipation component 21 to improve the positioning accuracy of the first pin 20 in conjunction with the mold during the molding process.

[0027] In a first embodiment, the boss includes a pair of first bosses 24, which are positioned at the distal end of the heat dissipation component 21 (i.e., the end away from the pin 22). During the molding process, the mold clamps and fixes the first bosses 24 and leaves a groove 11 on the package 10.

[0028] Figures 4 to 5 The second implementation is shown. Since the first pin 20 extends to the upper part of the chip 40 after the bend 23, and the pin 22 and the heat sink 21 are located on different planes, a second protrusion 25 is provided. The second protrusion 25 is positioned at the near end of the heat sink 21 (i.e., the end close to the pin 22 and the bend 23).

[0029] In specific implementations, this top heat dissipation structure is used for diode or transistor packages, particularly for surface mount packages of medium-to-high power components operating in the 15-20A range. The preferred surface mount package is TO-277.

[0030] Unless otherwise specified, the singular forms “a,” “the,” and “the” used in this specification include the plural forms. The terms “comprising,” “including,” and “containing” used in this specification indicate the presence of the claimed feature but do not exclude the presence of one or more other features. The term “and / or” used in this specification includes any and all combinations of one or more of the relevant listed items.

[0031] When a component is described in the specification as being "on", "fixed" to, "connected" to, or "joined" to another component, the component may be directly located on, fixed to, connected to, joined to, or in contact with the other component, or there may be an intermediate component present.

[0032] It is understood that although the terms "first," "second," etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Therefore, a first element may be referred to as a second element without departing from the teachings of this application.

Claims

1. A package structure for medium-to-high power components, comprising a chip, a first pin, and a second pin disposed within the package body, wherein the first pin and the second pin are electrically interconnected with the chip, and portions of the first pin and the second pin extend outward from the package body, characterized in that, The first pin has a heat dissipation component for dissipating heat outward and upward, the heat dissipation component being located on the upper side of the chip and exposed on the upper surface of the package.

2. The packaging structure for medium-to-high power components as described in claim 1, characterized in that, The first pin is also provided with at least one pair of bosses for assisting the mold in positioning during the molding process.

3. The packaging structure for medium-to-high power components as described in claim 2, characterized in that, The first pin includes a bend.

4. The packaging structure for medium-to-high power components as described in claim 3, characterized in that, The at least one pair of bosses includes a pair of first bosses, which are positioned opposite each other at the distal end of the heat dissipation component.

5. The packaging structure for medium-to-high power components as described in claim 3, characterized in that, The at least one pair of bosses also includes a pair of second bosses, the pair of second bosses being positioned opposite each other at the proximal end of the heat dissipation component.

6. The packaging structure for medium-to-high power components as described in any one of claims 1 to 5, characterized in that, The first pin and / or the second pin have at least one pin for electrical connection to an external device.

7. The packaging structure for medium-to-high power components as described in any one of claims 1 to 5, characterized in that, The chip is a diode or a transistor.

8. The packaging structure for medium-to-high power components as described in any one of claims 1 to 5, characterized in that, The packaging structure is a surface mount package.

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