Controller compatible with optical fiber and physical IO interface

Abstract

The utility model relates to a controller compatible with an optical fiber and a physical IO interface, a housing of the controller is provided with a multipath optical fiber interface SFP, a physical I / O interface and an Ethernet interface, and the controller is internally provided with a CPU and an FPGA; the FPGA is respectively connected with the multi-path optical fiber interface SFP and the physical I / O interface, is used for receiving data transmitted by the physical I / O interface or the optical fiber interface SFP, and is in signal connection with the CPU; analog signal and digital signal input and output circuits are respectively arranged between the FPGA and the physical I / O interface; the CPU is in communication connection with an upper computer through Ethernet interface signals. Compared with the prior art, two operation modes of optical fiber and physical I / O can be realized under the same real-time architecture, and the control circuit is suitable for control application of large-scale power electronic systems such as parallel inverters, multi-level converters and the like.

Description

Technical Field

[0001] This utility model relates to the field of controller technology, and in particular to a controller compatible with both fiber optic and physical I / O interfaces. Background Technology

[0002] With the rapid development of industrial automation, power electronics, and embedded systems, controllers need to process larger volumes of data and respond in shorter timeframes. This is especially true in applications such as power system protection, servo control, and real-time simulation, which place higher demands on the controller's interface compatibility, transmission speed, and flexibility. Fiber optic interfaces offer high-speed data transmission capabilities to meet the needs of low-latency, high-volume data transmission, while physical I / O interfaces are compatible with the access and control of traditional power equipment.

[0003] Traditional controllers typically support only a single type of interface and have relatively fixed configurations, making parameter adjustments difficult and necessitating hardware replacement or redesign for different application scenarios. Therefore, designing a controller compatible with both fiber optic and physical I / O interfaces to improve its applicability and data processing efficiency has become a crucial direction for technological development in the industry. Utility Model Content

[0004] The purpose of this invention is to overcome the defects of the existing technology and provide a controller that is compatible with both fiber optic and physical I / O interfaces.

[0005] The objective of this utility model can be achieved through the following technical solutions:

[0006] A controller compatible with fiber optic and physical I / O interfaces, wherein the controller housing is provided with multiple fiber optic interfaces SFP, physical I / O interfaces and Ethernet interfaces, and the controller internally is provided with a CPU and an FPGA;

[0007] The FPGA is connected to the multi-channel fiber optic interface SFP and the physical I / O interface respectively, and is used to receive data transmitted from the physical I / O interface or the fiber optic interface SFP, and is connected to the CPU signal; the FPGA and the physical I / O interface are respectively provided with analog signal and digital signal input and output circuits; the CPU is connected to the host computer through the Ethernet interface signal.

[0008] As a preferred technical solution, the CPU and FPGA are connected via an AXI high-speed bus signal.

[0009] As a preferred technical solution, the fiber optic interface SFP includes multiple SFP+10 Gigabit fiber optic interfaces; the physical I / O interface includes multiple DO interfaces, AI interfaces, DI interfaces and AO interfaces.

[0010] As a preferred technical solution, the digital input circuit between the FPGA and the physical I / O interface is specifically as follows: the positive and negative digital input ports of the physical I / O interface are respectively connected to one end of the constant current power supply through an anti-reverse diode; the other end of the constant current power supply is connected to the positive input of the optocoupler isolation, and the negative input of the optocoupler isolation is connected to the negative terminal of the digital input of the physical I / O interface; the output terminal of the optocoupler isolation is connected to the digital input I / O port of the FPGA through a digital buffer.

[0011] As a preferred technical solution, the digital output circuit between the FPGA and the physical I / O interface is specifically as follows: the digital output I / O port of the FPGA is connected to a push-pull structure through a digital buffer. The push-pull structure includes an NMOS and a PMOS. The gate terminals of the NMOS and PMOS are connected as input terminals and connected to the output terminal of the digital buffer. The drain terminals are connected and connected to the digital output port of the physical I / O interface. The source terminal of the PMOS is connected to the power supply VDD, and the source terminal of the NMOS is grounded.

[0012] As a preferred technical solution, the analog output circuit between the FPGA and the physical I / O interface is specifically as follows: the analog output I / O port of the FPGA is connected to the input terminal of the digital-to-analog converter, and the positive and negative output terminals of the digital-to-analog converter are connected to the positive and negative analog output ports of the physical I / O interface after passing through the output signal conditioning circuit. The output signal conditioning circuit includes a signal amplification circuit and a filtering circuit.

[0013] As a preferred technical solution, the output signal conditioning circuit is specifically as follows: the output terminal of the digital-to-analog converter and the reference voltage are respectively input to the negative input terminal of the first operational amplifier through a resistor. The positive input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is fed back to the negative input terminal of the first operational amplifier through a resistor. The output terminal of the first operational amplifier is also input to the positive input terminal of the second operational amplifier through a resistor. The output terminal of the second operational amplifier is fed back to the negative input terminal of the second operational amplifier through a parallel resistor and capacitor, and the other path is connected to the positive and negative analog output ports of the corresponding physical IO interface.

[0014] As a preferred technical solution, the analog input circuit between the FPGA and the physical I / O interface is specifically as follows: the positive and negative analog input ports of the physical I / O interface are connected to the analog-to-digital converter via an input signal conditioning circuit, the input signal conditioning circuit including a signal scaling circuit and a filtering circuit; the output terminal of the analog-to-digital converter is connected to the analog input I / O port of the FPGA.

[0015] As a preferred technical solution, the input signal conditioning circuit is specifically as follows: the positive and negative analog input ports of the physical I / O interface are respectively connected to the positive and negative inputs of the third operational amplifier via a resistor; the positive input terminal of the third operational amplifier is grounded through a resistor, and the output terminal of the third operational amplifier is fed back to the negative input terminal of the third operational amplifier through a resistor; the output terminal of the third operational amplifier and the reference voltage are respectively connected to the positive input terminal of the fourth operational amplifier through a resistor, the positive input terminal of the fourth operational amplifier is also grounded through a capacitor, the negative input terminal of the fourth operational amplifier is grounded through a resistor, and the output terminal of the fourth operational amplifier is fed back to the negative input terminal of the fourth operational amplifier through a resistor; the output terminal of the fourth operational amplifier is connected to the analog-to-digital converter.

[0016] As a preferred technical solution, an input overvoltage protection detector is also provided between the positive and negative analog input ports of the physical I / O interface and the third operational amplifier.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1) The controller provided by this utility model supports both fiber optic interfaces and physical I / O interfaces, adapting to diverse controller application scenarios. The controller is equipped with 64 DO interfaces, 32 AI interfaces, 16 DI interfaces, and 8 AO interfaces, providing abundant physical I / O interface resources, a wide range of digital level inputs, and 8 SFP+ 10 Gigabit fiber optic interfaces, enabling high-speed data transmission of massive electrical quantities and meeting the requirements for low-latency, interference-resistant, and high-volume data transmission. It is compatible with the access and control of traditional power equipment and is suitable for control applications of large-scale power electronic systems such as parallel inverters and multilevel converters. Attached Figure Description

[0019] Figure 1 The following are perspective views of the rapid prototyping controller device compatible with both fiber optic and physical I / O interfaces of this utility model: 1a) first perspective view, 1b) second perspective view, 1c) third perspective view, and 1d) fourth perspective view.

[0020] Figure 2 The following are structural diagrams of the rapid prototyping controller device compatible with both fiber optic and physical I / O interfaces of this utility model: 2a) front view, 2b) top view, 2c) left view, and 2d) rear view.

[0021] Figure 3 This is a schematic diagram of the controller architecture in an embodiment of the present utility model;

[0022] Figure 4 This is a circuit diagram of the digital input interface of the physical I / O interface in this embodiment of the present invention;

[0023] Figure 5 This is a circuit diagram of the digital output interface of the physical I / O interface in this embodiment of the present invention;

[0024] Figure 6 This is a circuit diagram of the analog output interface of the physical I / O interface in this embodiment of the present invention;

[0025] Figure 7 This is a circuit diagram of the analog input interface of the physical I / O interface in this embodiment of the present invention. Detailed Implementation

[0026] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. This embodiment is based on the technical solution of the present invention and provides detailed implementation methods and specific operating procedures; however, the scope of protection of the present invention is not limited to the following embodiments.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0028] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] Example 1

[0030] This invention provides a rapid prototyping controller compatible with both fiber optic and physical I / O interfaces. This device can solve the problems of traditional controllers having a single interface, low data transmission efficiency, and insufficient adaptability.

[0031] like Figure 1 , 2 As shown, the controller is equipped with multiple fiber optic SFP interfaces, physical I / O interfaces, and Ethernet interfaces. The controller communicates with the host computer via Ethernet and can receive configuration commands from the user through the host computer. The controller adopts a CPU+FPGA architecture. The FPGA is connected to the fiber optic SFP interfaces and multiple physical I / O interfaces, responsible for receiving data from the physical I / O interfaces or fiber optic SFP interfaces and uploading the processed data to the CPU. High-speed communication between the controller's CPU and FPGA is achieved through the AXI high-speed bus, ensuring real-time and efficient data processing. It supports both fiber optic and physical I / O operating modes under the same real-time architecture, adapting to diverse controller application scenarios.

[0032] The FPGA module is responsible for data reception, analysis, processing, calculation, and transmission, such as... Figure 3As shown, its internal components include an optical fiber data receiving unit, an optical fiber data transmitting unit, an I / O interface unit, an AXI bus interface logic unit, a data uploading unit, a data downloading unit, and a signal transmitting unit (transmitting IP core).

[0033] In this embodiment, the controller is equipped with fiber optic interfaces including 8 SFP+ 10 Gigabit fiber optic interfaces, which enables high-speed data transmission of massive electrical quantities and can meet the requirements of low latency and interference resistance for large-volume data transmission.

[0034] In this embodiment, the controller is equipped with physical I / O interfaces including 64 DO interfaces, 32 AI interfaces, 16 DI interfaces, and 8 AO interfaces. This abundant physical I / O interface resource and wide range of digital level inputs enable compatibility with the connection and control of traditional power equipment, making it suitable for control applications in large-scale power electronic systems such as parallel inverters and multilevel converters. In physical I / O interface mode, the controller interacts with the actual controlled object through its external physical I / O interface circuitry.

[0035] The digital input circuit of the I / O interface supports a wide voltage input range of -25V to +25V; its main features are high speed, optocoupler isolation, and constant current drive. For example... Figure 4 As shown, the positive and negative digital input ports of the physical I / O interface are each connected to one end of a constant current power supply via a reverse protection diode; the other end of the constant current power supply is connected to the positive input of the optocoupler isolation, and the negative input of the optocoupler isolation is connected to the negative terminal of the digital input of the physical I / O interface; the output of the optocoupler isolation is connected to the digital input I / O port of the FPGA via a digital buffer. Optocoupler isolation effectively isolates interference signals, and the 4mA constant current power supply allows the secondary winding of the optocoupler to be fully turned on / off. The reverse protection diodes at the front end of the circuit effectively prevent permanent damage to the circuit due to operational errors; after passing through the optocoupler, the signal passes through a digital buffer before reaching the FPGA's I / O port.

[0036] The digital output circuit of the I / O interface supports high-speed 5VTTL level output. For example... Figure 5As shown, the FPGA's digital output I / O ports are connected to a push-pull structure via digital buffers. The push-pull structure includes an NMOS and a PMOS transistor. The gates of the NMOS and PMOS are connected as inputs to the output of the digital buffer, and their drains are connected to the digital output of the physical I / O interface. The source of the PMOS is connected to the power supply VDD, and the source of the NMOS is grounded. Signals from the FPGA first pass through several digital buffers, which protect the FPGA I / O ports. The main feature of the digital output circuit is its push-pull structure, including an NMOS and a PMOS transistor. This structure supports high-speed digital signal output, ±20mA drive capability, and low output impedance. Furthermore, the push-pull structure supports both pull-up and pull-down inputs at the user end.

[0037] The analog output circuit of the I / O interface supports an output range of -10V to +10V, 16-bit resolution, and a data update rate of 1MSPS. Its main features are fast data updates, high accuracy, and good synchronization performance between different channels. For example... Figure 6 As shown, the output of the digital-to-analog converter (DAC) and the reference voltage are respectively input to the negative input of the first operational amplifier via a resistor. The positive input of the first operational amplifier is grounded, and its output is fed back to its negative input via a resistor. The output of the first operational amplifier is also fed back to the positive input of the second operational amplifier via a resistor. The output of the second operational amplifier is fed back to its negative input via a parallel resistor and capacitor, and connected to the corresponding positive and negative analog output ports of the physical I / O interface. This circuit uses a high-performance DAC to convert the digital signal output from the FPGA into an analog signal. The operational amplifier then conditions the signal output from the DAC, including amplification and filtering, ultimately outputting the required analog signal. The FPGA's analog output I / O ports are connected to the DAC's input. The DAC's positive and negative outputs are connected to the physical I / O interface's positive and negative analog output ports after passing through an output signal conditioning circuit, which includes a signal amplification and filtering circuits.

[0038] The analog input circuit of the IO interface supports an input range of -10V to +10V, 16-bit resolution, and a data sampling rate of 1MSPS. Its main features are high accuracy, good synchronization performance, and the ability to acquire more data points with a fixed signal frequency, thus enabling a more accurate reconstruction of the input analog signal. For example... Figure 7As shown, the input signal conditioning circuit is as follows: the positive and negative analog input ports of the physical I / O interface are connected to the positive and negative inputs of the third operational amplifier via resistors, respectively; the positive input of the third operational amplifier is grounded through a resistor, and the output of the third operational amplifier is fed back to the negative input through a resistor; the output of the third operational amplifier and the reference voltage are connected to the positive input of the fourth operational amplifier via resistors, the positive input of the fourth operational amplifier is also grounded through a capacitor, the negative input of the fourth operational amplifier is grounded through a resistor, and the output of the fourth operational amplifier is fed back to the negative input through a resistor; the output of the fourth operational amplifier is connected to the analog-to-digital converter. This circuit uses a high-performance analog-to-digital converter to convert the input analog signal into a digital signal, and finally transmit the data to the FPGA. Before the signal enters the analog-to-digital converter, it needs to be conditioned, including signal scaling and filtering. This circuit also supports input overvoltage protection detection; when the input signal amplitude exceeds a certain threshold, the overvoltage protector will automatically cut off the signal link.

[0039] The working principle of the above controller is as follows:

[0040] Users configure and map the controller on a host computer, and download the control algorithm model written in Simulink or LabVIEW to the controller CPU for real-time execution via Ethernet. The controller receives sampled signals through the FPGA via a physical I / O interface or a fiber optic interface, and uploads the sampled signals to the CPU via the AXI high-speed bus. The CPU generates corresponding control signals based on the sampled data and sends the control signals down to the FPGA, which then outputs them through the fiber optic interface or physical I / O interface. Data interaction between the controller and the actual controlled object can be achieved through the physical I / O interface or fiber optic interface according to user configuration, thereby helping users quickly verify and test control strategies and adapt to the needs of different application scenarios. It should be noted that the control algorithm running on the CPU in this application can be customized and loaded by the user according to specific project requirements. The purpose of this application is only to provide a rapid prototyping controller hardware compatible with both fiber optic and physical I / O interfaces, and does not involve any improvement to the specific control algorithm.

[0041] The preferred embodiments of this utility model have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of this utility model without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of this utility model through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A controller compatible with both fiber optic and physical I / O interfaces, characterized in that, The controller housing is equipped with multiple fiber optic interfaces (SFP), physical I / O interfaces, and Ethernet interfaces. The controller internally contains a CPU and an FPGA. The FPGA is connected to the multi-channel fiber optic interface SFP and the physical I / O interface respectively, and is used to receive data transmitted from the physical I / O interface or the fiber optic interface SFP, and is connected to the CPU signal; the FPGA and the physical I / O interface are respectively provided with analog signal and digital signal input and output circuits; the CPU is connected to the host computer through the Ethernet interface signal.

2. The controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The CPU and FPGA are connected via an AXI high-speed bus signal.

3. A controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The fiber optic interface SFP includes multiple SFP+ 10 Gigabit fiber optic interfaces; the physical I / O interface includes multiple DO interfaces, AI interfaces, DI interfaces, and AO interfaces.

4. A controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The digital input circuit between the FPGA and the physical I / O interface is as follows: The positive and negative digital input ports of the physical I / O interface are connected to one end of a constant current power supply through a reverse protection diode; the other end of the constant current power supply is connected to the positive input of the optocoupler isolation, and the negative input of the optocoupler isolation is connected to the negative terminal of the digital input of the physical I / O interface; the output of the optocoupler isolation is connected to the digital input I / O port of the FPGA through a digital buffer.

5. A controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The digital output circuit between the FPGA and the physical I / O interface is as follows: The FPGA's digital output I / O port is connected to a push-pull structure via a digital buffer. The push-pull structure includes an NMOS and a PMOS. The gate terminals of the NMOS and PMOS are connected as input terminals to the output terminal of the digital buffer, and their drain terminals are connected to the digital output port of the physical I / O interface. The source terminal of the PMOS is connected to the power supply VDD, and the source terminal of the NMOS is grounded.

6. A controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The analog output circuit between the FPGA and the physical I / O interface is as follows: The analog output I / O port of the FPGA is connected to the input terminal of the digital-to-analog converter. The positive and negative output terminals of the digital-to-analog converter are connected to the positive and negative analog output ports of the physical I / O interface after passing through the output signal conditioning circuit. The output signal conditioning circuit includes a signal amplification circuit and a filtering circuit.

7. A controller compatible with both fiber optic and physical I / O interfaces according to claim 6, characterized in that, The output signal conditioning circuit is specifically as follows: The output of the digital-to-analog converter and the reference voltage are respectively input to the negative input of the first operational amplifier through a resistor. The positive input of the first operational amplifier is grounded. The output of the first operational amplifier is fed back to the negative input of the first operational amplifier through a resistor. The output of the first operational amplifier is also input to the positive input of the second operational amplifier through a resistor. The output of the second operational amplifier is fed back to the negative input of the second operational amplifier through a parallel resistor and capacitor, and the other path is connected to the positive and negative analog output ports of the corresponding physical I / O interface.

8. A controller compatible with both fiber optic and physical I / O interfaces according to claim 1, characterized in that, The analog input circuit between the FPGA and the physical I / O interface is as follows: The positive and negative analog input ports of the physical I / O interface are connected to the analog-to-digital converter via an input signal conditioning circuit, which includes a signal scaling circuit and a filtering circuit; the output of the analog-to-digital converter is connected to the analog input I / O port of the FPGA.

9. A controller compatible with both fiber optic and physical I / O interfaces according to claim 8, characterized in that, The input signal conditioning circuit is specifically as follows: The positive and negative analog input ports of the physical I / O interface are respectively connected to the positive and negative inputs of the third operational amplifier via a resistor; the positive input terminal of the third operational amplifier is grounded through a resistor, and the output terminal of the third operational amplifier is fed back to the negative input terminal of the third operational amplifier through a resistor; the output terminal of the third operational amplifier and the reference voltage are respectively connected to the positive input terminal of the fourth operational amplifier through a resistor, the positive input terminal of the fourth operational amplifier is also grounded through a capacitor, the negative input terminal of the fourth operational amplifier is grounded through a resistor, and the output terminal of the fourth operational amplifier is fed back to the negative input terminal of the fourth operational amplifier through a resistor; the output terminal of the fourth operational amplifier is connected to the analog-to-digital converter.

10. A controller compatible with both fiber optic and physical I / O interfaces according to claim 9, characterized in that, An input overvoltage protection detector is also provided between the positive and negative analog input ports of the physical I / O interface and the third operational amplifier.

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