Silicon wafer carrier plate

Abstract

The utility model provides a silicon wafer carrier plate, and relates to the field of photovoltaic production equipment. The silicon wafer carrier plate comprises a carrier plate and a cover plate. One or more hollow silicon wafer placing frames are arranged on the carrier plate; one or more silicon wafer covering frames are arranged on the cover plate; the silicon wafer placing frame corresponds to the silicon wafer covering frame; the cover plate is detachably connected with the carrier plate; the silicon wafer placing frame is used for placing silicon wafers; one side surface of a silicon wafer in the silicon wafer placing frame is close to the carrier plate, and the other side surface is close to the cover plate; silicon wafers in the silicon wafer placing frame are fixed in the silicon wafer placing frame through the carrier plate and the cover plate. Through the up-down supporting effect of the carrier plate and the cover plate, the silicon wafer is fixed in the silicon wafer placing frame, the silicon wafer in the silicon wafer placing frame does not fall off when the silicon wafer is reversed up and down, the silicon wafer carrier plate can be directly overturned and then conveyed into RPD equipment to be coated, and the silicon wafer does not need to be manually contacted when being overturned, so that the production efficiency is improved. Therefore, scratch and pollution to the silicon wafer caused by manual overturning of the silicon wafer are reduced.

Description

Technical Field

[0001] This application relates to the field of photovoltaic production equipment technology, specifically to silicon wafer carriers. Background Technology

[0002] Heterojunction (HJT) solar cells are a type of N-type bifacial cell with numerous advantages, including simple manufacturing process, high efficiency, low temperature coefficient, energy-saving low-temperature process throughout, suitability for thin-film fabrication due to their naturally bifacial nature, and good low-light response. In the photovoltaic industry, RPD (Reactive Plasma Deposition) equipment is primarily used for depositing transparent conductive oxide (TCO) thin films for HJT solar cells. Silicon wafer carriers are specialized consumables used in HJT solar cell production to support the silicon wafers.

[0003] In the production process of heterojunction (HJT) solar cells, because the RPD equipment is a single-sided coating device, the silicon wafers need to be manually flipped during coating when using a carrier plate to support them. However, existing carrier plates require manual contact with the silicon wafers during flipping, which can easily cause scratches and contamination, affecting product quality.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a silicon wafer carrier that does not require human contact with the silicon wafer during silicon wafer flipping and is less likely to cause scratches and contamination to the silicon wafer.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] A silicon wafer carrier, comprising:

[0008] A carrier board, wherein one or more hollowed-out silicon wafer placement frames are provided on the carrier board;

[0009] A cover plate, wherein one or more hollowed-out silicon wafer cover frames are provided on the cover plate; the silicon wafer placement frame corresponds to the silicon wafer cover frames; the cover plate is detachably connected to the carrier plate;

[0010] The silicon wafer placement frame is used to place silicon wafers; one side of the silicon wafer in the silicon wafer placement frame is close to the carrier plate, and the other side is close to the cover plate; the silicon wafer in the silicon wafer placement frame is fixed in the silicon wafer placement frame by the carrier plate and the cover plate.

[0011] In some embodiments, a plurality of first support members are spaced apart on the silicon wafer placement frame;

[0012] The silicon wafer cover frame is provided with multiple second support members at intervals;

[0013] In this configuration, one side of the silicon wafer within the silicon wafer placement frame is close to the first support member, and the other side is close to the second support member.

[0014] In some embodiments, a carrier frame is also included, on which the carrier plate is disposed; the carrier frame is a perforated carrier frame.

[0015] In some embodiments, the thickness of the carrier plate is 3.5-4.5 mm;

[0016] And / or, the thickness of the cover plate is 2.5-3.5 mm.

[0017] In some embodiments, the carrier board is provided with 4-10 silicon wafer placement frames; the silicon wafer placement frames are arranged in an array.

[0018] In some embodiments, the silicon wafer placement frame is provided with 4-10 first support members;

[0019] And / or, the silicon wafer cover frame is provided with 4-10 second support members.

[0020] In some embodiments, the carrier plate is provided with a first positioning hole, and the cover plate is provided with a matching second positioning hole. The carrier plate and the cover plate are detachably connected through the first positioning hole, the second positioning hole, and a connector.

[0021] In some embodiments, the surface roughness of the carrier plate near the silicon wafer is ≤0.6μm;

[0022] And / or, the surface roughness of the cover plate near the silicon wafer side is ≤0.6μm.

[0023] In some embodiments, the length of the first support member is 1.8-2.2 mm, and the width of the first support member is 0.7-1.2 mm;

[0024] And / or, the length of the second support member is 1.8-2.2 mm, and the width of the second support member is 0.7-1.2 mm.

[0025] In some embodiments, the surface roughness of the first support member near the silicon wafer side is ≤0.2μm;

[0026] And / or, the surface roughness of the second support member near the silicon wafer side is ≤0.2μm.

[0027] In the technical solution of this application, the silicon wafer is fixed in the silicon wafer placement frame by the upper and lower support of the carrier plate and the cover plate. The silicon wafer in the silicon wafer placement frame will not fall off when the wafer is reversed. The silicon wafer carrier plate can be directly flipped and then conveyed into the RPD equipment for coating. There is no need for human contact with the silicon wafer when flipping the silicon wafer, thereby reducing the scratches and contamination caused by manually flipping the silicon wafer. Attached Figure Description

[0028] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0029] Figure 1 This is a plan view of one side of the silicon wafer carrier according to an embodiment of this application.

[0030] Figure 2 This is a plan view of the other side of the silicon wafer carrier in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram of the silicon wafer placement frame in an embodiment of this application.

[0032] Figure 4 This is a side view of the silicon wafer carrier according to an embodiment of this application.

[0033] Figure 5 This is a side view of another silicon wafer carrier according to an embodiment of this application.

[0034] The following are the labels in the diagram: 1. Carrier plate; 2. Cover plate; 21. Second support member; 22. Silicon wafer cover frame; 11. Silicon wafer placement frame; 12. First support member; 3. Silicon wafer; 4. Carrier plate frame; 5. First positioning hole; 5'. Second positioning hole. Detailed Implementation

[0035] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0037] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] This application provides a silicon wafer carrier. Through the upper and lower support of the carrier 1 and the cover plate 2, the silicon wafer 3 is fixed in the silicon wafer placement frame 11. When the wafer is reversed, the silicon wafer 3 in the silicon wafer placement frame 11 will not fall off. The silicon wafer carrier can be directly flipped and then conveyed into the RPD equipment for coating. There is no need for human contact with the silicon wafer when flipping the silicon wafer, thereby reducing the scratches and contamination caused by manually flipping the silicon wafer.

[0040] This application provides a silicon wafer carrier, comprising:

[0041] Carrier plate 1, wherein one or more hollowed-out silicon wafer placement frames 11 are provided on the carrier plate 1;

[0042] The cover plate 2 has one or more hollowed-out silicon wafer cover frames 22; the silicon wafer placement frame 11 corresponds to the silicon wafer cover frame 22; the cover plate 2 is detachably connected to the carrier plate 1;

[0043] The silicon wafer placement frame 11 is used to place silicon wafers; one side of the silicon wafer in the silicon wafer placement frame 11 is close to the carrier plate 1, and the other side is close to the cover plate 2; the silicon wafer in the silicon wafer placement frame 11 is fixed in the silicon wafer placement frame 11 by the carrier plate 1 and the cover plate 2.

[0044] In this embodiment, the carrier plate 1 and the cover plate 2 can be made of 316 stainless steel. The materials of the carrier plate 1 and the cover plate 2 can also be selected according to actual needs, ensuring sufficient mechanical strength to support the carrier plate 1. Using 316 stainless steel as the material for the carrier plate 1 and the cover plate 2 ensures sufficient mechanical strength for the silicon wafer carrier. Furthermore, during double-sided coating, the coating material loaded on the silicon wafer carrier is less likely to fall onto the silicon wafer, resulting in a better coating effect.

[0045] In this embodiment, one or more perforated silicon wafer placement frames 11 are provided on the carrier plate 1, and the cover plate 2 is a perforated cover plate. The purpose of the cover plate 2 is to prevent the silicon wafers 3 within the silicon wafer placement frames 11 from being obstructed, and to ensure that the flipping and coating of the silicon wafers 3 within the silicon wafer placement frames 11 is not affected. It should be noted that the shape of the cover plate 2 is set according to the placement of the silicon wafer placement frames 11 on the carrier plate 1, and it only needs to not affect the flipping and coating of the silicon wafers 3 within the silicon wafer placement frames 11. For example, when the carrier plate 1 is provided with six silicon wafer placement frames 11 arranged in an array, the shape of the cover plate 2 is exactly the same as that of the carrier plate 1. When the cover plate 2 is connected and fixed to the carrier plate 1 by a connector, the carrier plate 1 and the cover plate 2 completely overlap, and the six silicon wafer placement frames 11 correspond to the six silicon wafer cover frames 22, without affecting the flipping and coating of the silicon wafers 3 within the silicon wafer placement frames 11. Wherein, a single silicon wafer placement frame 11 is as follows: Figure 3 As shown.

[0046] In this embodiment, the cover plate 2 can be detachably connected to the carrier plate 1 via bolt and nut assemblies, positioning pins, and other suitable connectors. The process of front and back coating using the silicon wafer carrier plate can be as follows: mounting the cover plate 2 and carrier plate 1 to fix the silicon wafer 3, front coating, first flipping of the silicon wafer carrier plate (flipping the silicon wafer 3), back coating, second flipping of the silicon wafer carrier plate (this step is optional), and removing the cover plate 2 and carrier plate 1 to remove the silicon wafer 3. Specifically, when the silicon wafer 3 is undergoing back-side transfer coating on the carrier plate 1, the silicon wafer 3 can be flipped by manually touching the cover plate 2, without the need for manual contact with the silicon wafer 3. The cover plate 2 acts as a dustproof plate (preventing manual contact with the silicon wafer 3) to ensure the cleanliness of the silicon wafer. After the coating is completed, flip the carrier plate 1 and the cover plate 2, then unscrew the connecting parts (such as positioning pins, bolt and nut assemblies, etc.) between the carrier plate 1 and the cover plate 2, remove the cover plate 2, and the coating is complete. The silicon wafer 3 can then be removed and replaced with the next set of silicon wafers 3 for coating. This can effectively reduce human contact with the silicon wafer 3 and improve the process yield.

[0047] In this embodiment, one side (front or back) of the silicon wafer 3 within the wafer placement frame 11 is close to the carrier plate 1, and the other side (back or front) is close to the cover plate 2. The silicon wafer 3 within the wafer placement frame 11 is fixed within the frame by the carrier plate 1 and the cover plate 2. That is, the carrier plate 1 and the cover plate 2 support the front and back sides of the silicon wafer 3, thus providing support and bearing. This double-sided support of the front and back sides ensures good support and bearing effect for the silicon wafer 3, reduces the risk of the wafer falling, and does not affect production efficiency. Furthermore, due to the double-sided support of the carrier plate 1 and the cover plate 2, the silicon wafer is less prone to bending, effectively preventing uneven heating and uneven coating caused by wafer bending.

[0048] In this embodiment, the silicon wafer 3 is fixed within the wafer placement frame 11 by the upper and lower support of the carrier plate 1 and the cover plate 2. The silicon wafer 3 will not fall out of the wafer placement frame 11 when the wafer is reversed. The silicon wafer carrier plate can be directly flipped and conveyed into the RPD equipment for coating. No manual contact with the silicon wafer is required during flipping, thus reducing scratches and contamination caused by manual wafer flipping. The upper and lower support of the carrier plate 1 and the cover plate 2 ensures the silicon wafer is fixed within the wafer placement frame 11, providing good support, low risk of wafer falling, and no impact on production efficiency.

[0049] In some embodiments, a plurality of first support members 12 are spaced apart on the silicon wafer placement frame 11;

[0050] The silicon wafer cover frame 22 is provided with a plurality of second support members 21 at intervals;

[0051] In the silicon wafer placement frame 11, one side of the silicon wafer is close to the first support member 12, and the other side is close to the second support member 21.

[0052] In this embodiment, the first support member 12 can be disposed at the bottom end of the inner sidewall of the silicon wafer placement frame 11, and the first support member 12 extends horizontally towards the inner side of the silicon wafer placement frame 11; the second support member 21 can be disposed at the top end of the inner sidewall of the silicon wafer cover frame 22, and the second support member 21 extends horizontally towards the inner side of the silicon wafer cover frame 22, specifically as follows: Figure 4 and Figure 5 As shown. Furthermore, the width of the first support member 12 refers to the length by which the first support member 12 extends horizontally inward towards the inner side of the silicon wafer placement frame 11, and the length of the first support member 12 refers to the length of the connecting edge formed at the connection between the first support member 12 and the sidewall; similarly, the width of the second support member 21 refers to the length by which the second support member 21 extends horizontally inward towards the inner side of the silicon wafer cover frame 22, and the length of the second support member 21 refers to the length of the connecting edge formed at the connection between the second support member 21 and the sidewall. Through the upper and lower support of the first support member 12 and the second support member 21, the silicon wafer is fixed within the silicon wafer placement frame 11, ensuring that the silicon wafer has sufficient placement space within the silicon wafer placement frame 11 and does not fall off. The first support member 12 and the second support member 21 also do not form excessively large mask areas, which could lead to uncoated areas and affect process efficiency.

[0053] In this embodiment, one side (front or back) of the silicon wafer 3 within the wafer placement frame 11 is close to the first support member 12, and the other side (back or front) is close to the second support member 21. The silicon wafer 3 within the wafer placement frame 11 is fixed within the frame by the first support member 12 and the second support member 21. That is, the first support member 12 and the second support member 21 support the front and back sides of the silicon wafer 3, thus providing support and load-bearing capacity. This double-sided support on both the front and back sides effectively supports and loads the silicon wafer 3, resulting in good support and load-bearing performance. Furthermore, due to the double-sided support of the first support member 12 and the second support member 21, the silicon wafer is less prone to bending, effectively preventing uneven heating and uneven coating caused by wafer bending.

[0054] In this embodiment, the silicon wafer is fixed within the silicon wafer placement frame 11 by the upper and lower support of the first support member 12 and the second support member 21. This provides good support, reduces the risk of the silicon wafer falling, and does not affect production efficiency. The first support member 12 and the second support member 21 are arranged at intervals, meaning the contact area between the first support member 12, the second support member 21 and the silicon wafer is small, and the contact points are distributed in a dotted pattern (see...). Figure 3It can be seen that the contact area between the first support member 12 and the silicon wafer 3 is small, and the first support member 12 can be seen to be distributed in a dotted manner on the silicon wafer 3. Then, the silicon wafer is sent into the RPD equipment for coating, and the silicon wafer will not have black edges / black corners.

[0055] In some embodiments, a carrier frame 4 is also included, on which the carrier plate 1 is disposed; the carrier frame 4 is a perforated carrier frame. In this embodiment, the carrier frame 4 serves to support, fix, and carry the carrier plate 1 at the bottom. The carrier frame 4 can drive the carrier plate 1 to complete roller transport within the inner cavity of the RPD equipment, ensuring stable transport of the silicon wafer 3 within the inner cavity of the RPD equipment. The carrier frame 4 is specifically as follows... Figure 5 As shown.

[0056] In this embodiment, the shape of the carrier frame 4 is set according to the placement of the silicon wafer placement frame 11 on the carrier 1, and it does not affect the flipping and coating of the silicon wafer 3 within the silicon wafer placement frame 11. The carrier frame 4 does not affect the flipping and coating of the silicon wafer 3 within the silicon wafer placement frame 11.

[0057] In some embodiments, the thickness of the carrier plate 1 is 3.5-4.5 mm (e.g., 3.5 mm, 4.0 mm, 4.5 mm).

[0058] And / or, the thickness of the cover plate 2 is 2.5-3.5mm (e.g., 2.5mm, 3.0mm, 3.5mm). In this embodiment, controlling the thickness of the carrier plate 1 and the cover plate 2 can ensure that the carrier plate 1 and the cover plate 2 have a certain support capacity, while reducing the material consumption of the carrier plate 1 and the cover plate 2.

[0059] In some embodiments, 4-10 silicon wafer placement frames 11 are provided on the carrier 1; the silicon wafer placement frames 11 are arranged in an array. In this embodiment, the silicon wafer placement frames 11 can be arranged in an array in a 2*2, 3*3, 2*3, 3*2, etc., depending on actual needs. The number of silicon wafer placement frames 11 on the carrier 1 should not be too large to avoid poor load-bearing effect of the carrier 1, and the number of silicon wafer placement frames 11 on the carrier 1 should not be too small to avoid low operating efficiency. An image showing the silicon wafer placement frames 11 arranged in a 3*2 array is shown below. Figure 1 , Figure 2 As shown.

[0060] In some embodiments, the silicon wafer placement frame 11 is provided with 4-10 first support members 12;

[0061] And / or, the silicon wafer cover frame 22 is provided with 4-10 second support members 21. In this embodiment, the number of first support members 12 and second support members 21 is set according to actual needs, as long as it can ensure the supporting effect of the silicon wafer 3.

[0062] In some embodiments, the carrier plate 1 is provided with a first positioning hole 5, and the cover plate 2 is provided with a matching second positioning hole 5'. The carrier plate 1 and the cover plate 2 are detachably connected through the first positioning hole 5, the second positioning hole 5', and a connector. In this embodiment, the first positioning hole 5 on the carrier plate 1 and the second positioning hole 5' on the cover plate 2 are correspondingly provided, facilitating the detachable connection between the carrier plate 1 and the cover plate 2 through connectors such as bolt and nut assemblies. The number and arrangement of the first positioning hole 5 and the second positioning hole 5' can be set according to actual needs.

[0063] In some embodiments, the surface roughness of the carrier plate 1 near the silicon wafer is ≤0.6μm;

[0064] And / or, the surface roughness of the cover plate 2 near the silicon wafer is ≤0.6μm. In this embodiment, the surface roughness of the carrier plate 1 and the cover plate 2 can be controlled and guaranteed by operations such as spraying 32-mesh diamond abrasive on the carrier plate 1 and the cover plate 2. Controlling the surface roughness of the carrier plate 1 and the cover plate 2 can prevent the burrs on the surface of the carrier plate 1 and the cover plate 2 from scratching the silicon wafer 3.

[0065] In some embodiments, the length of the first support member 12 is 1.8-2.2 mm (e.g., 1.8 mm, 2.0 mm, 2.2 mm), and the width of the first support member 12 is 0.7-1.2 mm (e.g., 0.7 mm, 0.9 mm, 1.2 mm).

[0066] And / or, the length of the second support member 21 is 1.8-2.2 mm (e.g., 1.8 mm, 2.0 mm, 2.2 mm), and the width of the second support member 21 is 0.7-1.2 mm (e.g., 0.7 mm, 0.9 mm, 1.2 mm).

[0067] In this embodiment, controlling the dimensions of the first support member 12 and the second support member 21 improves the support effect of the silicon wafer 3, reduces the risk of the silicon wafer 3 falling off, does not affect production efficiency, and prevents the phenomenon of black edges / black corners. Controlling the dimensions of the first support member 12 and the second support member 21 can further prevent uneven heating and uneven coating caused by the bending of the silicon wafer 3.

[0068] In some embodiments, the surface roughness of the first support 12 near the silicon wafer side is ≤0.2μm;

[0069] And / or, the surface roughness of the second support 21 near the silicon wafer side is ≤0.2μm.

[0070] In this embodiment, controlling the surface roughness of the first support member 12 and the second support member 21 can prevent burrs on the surface of the first support member 12 and the second support member 21 from scratching the silicon wafer 3 and prevent the appearance of various marks and scratches.

[0071] The following specific embodiments provide a more detailed description of this application, but should not be construed as limiting the application. Any modifications or substitutions made to the methods, steps, or conditions of this application without departing from the spirit and substance of this application are within the scope of this application. Specific Implementation

[0073] Example 1

[0074] A silicon wafer carrier, such as Figures 1-4 As shown, it includes:

[0075] A carrier plate 1 has six hollowed-out silicon wafer placement frames 11, each frame being 210.6 mm long and 105.6 mm wide. Multiple first support members 12 are spaced apart on each frame. The carrier plate 1 has a thickness of 4 mm and a surface roughness ≤ 0.6 μm. Each first support member 12 has a length of 2 mm and a width of 1 mm, and a surface roughness ≤ 0.2 μm. Specifically, as shown... Figure 3 As shown, two first support members 12 are respectively provided on the two long sides of any silicon wafer placement frame 11, and one first support member 12 is respectively provided on the two short sides of any silicon wafer placement frame 11.

[0076] A cover plate 2 has six silicon wafer cover frames 22, each 210.6 mm long and 105.6 mm wide. Multiple second support members 21 are spaced apart on each silicon wafer cover frame 22. The cover plate 2 is detachably connected to the carrier plate 1 via connectors. The cover plate 2 has a thickness of 3 mm and a surface roughness ≤ 0.6 μm. The second support members 21 have a length of 2 mm and a width of 1 mm and a surface roughness ≤ 0.2 μm. Specifically, as shown... Figure 1 As shown, the cover plate 2 is provided with 36 second support members 21, such as... Figures 1-2 As shown, the arrangement of the first support member 12 is the same as that of the second support member 21; in addition, as Figures 1-2As shown, the carrier plate 1 is provided with 5 first positioning holes 5, and the cover plate 2 is provided with 5 second positioning holes 5'. The first positioning holes 5 on the carrier plate 1 and the second positioning holes 5' on the cover plate 2 are provided in correspondence. The carrier plate 1 and the cover plate 2 are detachably connected by bolt and nut assembly.

[0077] The silicon wafer placement frame 11 is used to place silicon wafers 3; one side of the silicon wafer 3 inside the silicon wafer placement frame 11 is close to the first support member 12, and the other side is close to the second support member 21; the silicon wafer 3 inside the silicon wafer placement frame 11 is fixed to the silicon wafer placement frame 11 by the first support member 12 and the second support member 21; the cover plate 2 is a perforated cover plate; specifically as follows... Figures 1-2 As shown, the silicon wafer placement frame 11 is provided with 6 hollowed-out silicon wafer placement frames 11 arranged in a 3*2 array. The cover plate 2 has the same shape as the carrier plate 1. When the cover plate 2 is connected and fixed to the carrier plate 1 through the connector, the carrier plate 1 and the cover plate 2 completely overlap, which does not affect the flipping and coating of the silicon wafer 3 inside the silicon wafer placement frame 11.

[0078] Both the carrier plate 1 and the cover plate 2 are made of 316 stainless steel.

[0079] The method of using the silicon wafer carrier is as follows: Place the silicon wafer 3 in the silicon wafer placement frame 11, and place the cover plate 2 on the carrier 1. Use connectors to connect and fix the cover plate 2 to the carrier 1. The silicon wafer 3 in the silicon wafer placement frame 11 is fixed in the silicon wafer placement frame 11 by the first support member 12 and the second support member 21. When the silicon wafer 3 is back-side transferred for coating on the carrier 1, the cover plate 2 can act as a dustproof plate to ensure the cleanliness of the silicon wafer. After the coating is completed, flip the carrier 1 and the cover plate 2, then unscrew the connector between the carrier 1 and the cover plate 2, remove the cover plate 2, and the coating is complete. Finally, remove the silicon wafer 3 and replace it with the next set of silicon wafers 3 for coating.

[0080] In summary, the technical solution of this application utilizes the upper and lower support of the first support member 12 and the second support member 21 to fix the silicon wafer within the silicon wafer placement frame 11. This provides good support, reduces the risk of the silicon wafer falling, does not affect production efficiency, and prevents the appearance of black edges / corners. The upper and lower support of the first support member 12 and the second support member 21 also prevents uneven heating and uneven coating caused by silicon wafer bending. The cover plate 2 ensures that the silicon wafer within the silicon wafer placement frame 11 will not fall out during vertical rotation. The silicon wafer carrier can be directly flipped and conveyed into the RPD equipment for coating. No manual contact with the silicon wafer is required during rotation, thus reducing scratches and contamination caused by manual wafer rotation.

[0081] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0082] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A silicon wafer carrier, characterized by, The utility model relates to a silicon wafer carrier plate, comprising: a carrier plate provided with one or more hollow silicon wafer placement frames; a cover plate provided with one or more hollow silicon wafer cover frames; the silicon wafer placement frames correspond to the silicon wafer cover frames; the cover plate and the carrier plate are detachably connected; wherein the silicon wafer placement frames are used to place silicon wafers; one side of the silicon wafer in the silicon wafer placement frame is close to the carrier plate, and the other side is close to the cover plate; the silicon wafer in the silicon wafer placement frame is fixed in the silicon wafer placement frame through the carrier plate and the cover plate.

2. The silicon wafer carrier plate according to claim 1, wherein: a plurality of first support members are arranged on the silicon wafer placement frames at intervals; a plurality of second support members are arranged on the silicon wafer cover frames at intervals; wherein one side of the silicon wafer in the silicon wafer placement frame is close to the first support members, and the other side is close to the second support members.

3. The silicon wafer carrier of claim 1, wherein, The carrier plate is arranged on a carrier plate frame; the carrier plate frame is a hollow carrier plate frame.

4. The silicon wafer carrier of claim 1, wherein The thickness of the carrier plate is 3.5-4.5 mm; and / or, the thickness of the cover plate is 2.5-3.5 mm.

5. The silicon wafer carrier of claim 1, wherein 4-10 silicon wafer placement frames are arranged on the carrier plate; the silicon wafer placement frames are arranged in an array.

6. The silicon wafer carrier of claim 2, wherein, 4-10 first support members are arranged on the silicon wafer placement frames; and / or, 4-10 second support members are arranged on the silicon wafer cover frames.

7. The silicon wafer carrier of claim 1, wherein First positioning holes are arranged on the carrier plate, and second positioning holes are arranged on the cover plate in a matching manner; the carrier plate and the cover plate are detachably connected through the first positioning holes, the second positioning holes, and connecting members.

8. The silicon wafer carrier of claim 1, wherein, The roughness of the surface of the side of the carrier plate close to the silicon wafer is ≤0.6 μm; and / or, the roughness of the surface of the side of the cover plate close to the silicon wafer is ≤0.6 μm.

9. The silicon wafer carrier of claim 2 wherein, The length of the first support members is 1.8-2.2 mm, and the width of the first support members is 0.7-1.2 mm; and / or, the length of the second support members is 1.8-2.2 mm, and the width of the second support members is 0.7-1.2 mm.

10. The silicon wafer carrier of claim 2, wherein, The roughness of the surface of the side of the first support members close to the silicon wafer is ≤0.2 μm; and / or, the roughness of the surface of the side of the second support members close to the silicon wafer is ≤0.2 μm.

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