Main control unit reset circuit and test machine

Abstract

The utility model relates to a main control unit reset circuit and a test machine, the main control unit reset circuit comprises a reset output module and more than two reset operation modules, and the reset output module is connected with each reset operation module and a main control unit; each reset operation module sends corresponding level signals to the reset output module through different types of operation modes, and the reset output module outputs a reset signal to the main control unit when at least one of the received level signals is a preset type of level, and performs reset operation on the main control unit. And a plurality of different operation modes can be supported for resetting the main control unit in a matched manner, so that the convenience of resetting operation is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a master control unit reset circuit and a test machine. BACKGROUND

[0002] Semiconductor automatic testing refers to detecting various parameter indexes of a chip by using an automatic test equipment (ATE) to eliminate defective products to control the quality of semiconductor products. A master control unit for testing control is arranged in a board of a test machine, and the master control unit needs to be reset in some scenarios. In a conventional master control reset circuit design, a hardware reset mode is used for the reset operation of the master control unit, and the reset operation can only be manually performed in a single board or a board bare leakage situation. The control mode is single, and the reset operation has the disadvantage of low convenience. CONTENT OF THE UTILITY MODEL

[0003] Therefore, it is necessary to provide a master control unit reset circuit and a test machine which can improve the convenience of reset operation in view of the above problems.

[0004] The first aspect of the present application provides a master control unit reset circuit, comprising a reset output module and two or more reset operation modules, the reset output module being connected to each reset operation module and a master control unit; each reset operation module sends a corresponding level signal to the reset output module through a different type of operation mode, and the reset output module outputs a reset signal to the master control unit when at least one of the received level signals is a preset type level, thereby performing a reset operation on the master control unit.

[0005] In one embodiment, the reset operation module includes at least two of an instruction reset operation module, a hardware reset operation module, and a self-reset operation module; the reset output module outputs a first type level to the master control unit when each reset operation module outputs the first type level, and outputs a second type level to the master control unit when at least one reset operation module outputs the second type level; the preset type level and the reset signal are both the second type level.

[0006] In one embodiment, the reset operation module includes an instruction reset operation module, the instruction reset operation module includes a first switch unit and a second switch unit, the first switch unit is connected to a control module and the second switch unit, and the second switch unit is connected to a power supply end and the reset output module.

[0007] The first switch unit is turned on when receiving the first type level output by the control module, and the second switch unit is turned off and sends the first type level to the reset output module.

[0008] The first switch unit is turned off when receiving the second type level output by the control module, and the second switch unit is turned on and transmits the second type level to the reset output module.

[0009] In one of the embodiments, the first switch unit comprises switch T2 and resistor R3, and the second switch unit comprises switch T1 and resistor R1; the control end of the switch T2 is connected to the control module, the first end of the switch T2 is connected to the first end of the resistor R3 and the control end of the switch T1, the second end of the switch T2 is grounded, the second end of the resistor R3 is connected to the power supply end, the first end of the switch T1 is connected to the first end of the resistor R1 and the reset output module, the second end of the resistor R1 is connected to the power supply end, and the second end of the switch T1 is grounded.

[0010] In one of the embodiments, the reset operation module comprises a hardware reset operation module, which comprises a button S1 and a resistor R10; the first side of the button S1 is connected to the first end of the resistor R10 and the reset output module, the second side of the button S1 is grounded, and the second end of the resistor R10 is connected to the power supply end.

[0011] In one of the embodiments, the reset operation module comprises a self-reset operation module, which is connected to the main control unit and the reset output module; when the self-reset signal output by the main control unit is the second type level, the second type level is output to the reset output module.

[0012] In one of the embodiments, the self-reset operation module comprises a delay chip, a resistor R6, a resistor R9 and a capacitor C5; the VIN pin of the delay chip is connected to the first end of the resistor R6 and the first end of the resistor R9, the second end of the resistor R6 is connected to the main control unit, the second end of the resistor R9 is connected to the power supply end, the GND pin of the delay chip is grounded, the ENIN pin and the VCC pin of the delay chip are connected to the power supply end, the CEXT pin of the delay chip is connected to the first end of the capacitor C5, the second end of the capacitor C5 is grounded, and the ENOUT pin of the delay chip is connected to the reset output module.

[0013] In one embodiment, the reset output module comprises an AND gate U1, a resistor R4 and a resistor R5, an input end A of the AND gate U1 is connected to a first end of the resistor R5, a second end of the resistor R5 is connected to a corresponding reset operation module, an input end B of the AND gate U1 is connected to a first end of the resistor R4, a second end of the resistor R4 is connected to a corresponding reset operation module; the AND gate U1 outputs a first type level from an output end Y when the input end A and the input end B both receive the first type level, and outputs a second type level from the output end Y when the input end A and / or the input end B receive the second type level.

[0014] In one embodiment, the reset output module further comprises an AND gate U2 and a resistor R8, an input end A of the AND gate U2 is connected to a corresponding reset operation module, an input end B of the AND gate U2 is connected to the output end Y of the AND gate U1; the AND gate U2 outputs a first type level from an output end Y when the input end A and the input end B both receive the first type level, and outputs a second type level from the output end Y when the input end A and / or the input end B receive the second type level.

[0015] The second aspect of the present application provides a test machine, comprising a master control unit and the master control unit reset circuit.

[0016] The master control unit reset circuit and the test machine, the master control unit reset circuit comprises a reset output module and two or more reset operation modules, the reset output module is connected with each reset operation module and the master control unit; each reset operation module sends a corresponding level signal to the reset output module through different types of operation modes, and the reset output module outputs a reset signal to the master control unit when at least one of the received level signals is a preset type level, so that the master control unit is reset, and multiple different operation modes can be supported to reset the master control unit, thereby improving the convenience of reset operation. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a structural block diagram of the master control unit reset circuit in one embodiment;

[0018] Figure 2 It is a structural schematic diagram of the master control unit reset circuit in one embodiment;

[0019] Figure 3 And Figure 4 It is a structural schematic diagram of the ADM1085 chip in one embodiment. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting of the application.

[0022] It can be understood that, in the following embodiments, "connection" should be understood as "electrical connection", "communication connection" and the like if the circuits, modules, units and the like connected with each other have the transmission of electrical signals or data.

[0023] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "including" or "having" and the like, designate the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

[0024] In one embodiment, as shown in Figure 1 A master unit reset circuit is provided, including reset operation modules 110 and a reset output module 200. The number of reset operation modules 110 is two or more. The reset output module 200 is connected to each reset operation module 100 and a master unit 300. Each reset operation module 100 sends a corresponding level signal to the reset output module 200 through different types of operation modes. When at least one of the received level signals is a preset type level, the reset output module 200 outputs a reset signal to the master unit 300 to perform a reset operation on the master unit 300.

[0025] The master unit 300 can be an FPGA, CPU, CPLD or other master control chip. The specific type and number of reset operation modules 100 are not unique. According to the corresponding operation, a first type level or a second type level is output to the reset output module 200. The preset type level can be the first type level or the second type level, which can be set according to actual needs. The reset signal can also be the first type level or the second type level, which is determined according to the reset mode of the master unit 300. The type of the reset signal and the preset type level can be the same or different. Specifically, the first type level is a high / low level, and the second type level is a low / high level. In this embodiment, the first type level is a high level, and the second type level is a low level.

[0026] Specifically, as shown in Figure 2 the preset type level and the reset signal are both the second type level. The reset operation module 100 includes at least two of the instruction reset operation module 110, the hardware reset operation module 120, and the self-reset operation module 130; the reset output module 200 outputs the first type level to the master control unit 300 when each reset operation module 100 outputs the first type level, and does not reset the master control unit 300; the reset output module 200 outputs the second type level to the master control unit 300 when at least one reset operation module 100 outputs the second type level, and resets the master control unit 300. The corresponding reset operation mode can be selected according to actual needs, and the reset operation of the master control unit 300 is realized by combining the logic of the instruction reset, the hardware reset, and the self-reset.

[0027] In one embodiment, the reset operation module 100 includes the instruction reset operation module 110, as shown in Figure 2 the instruction reset operation module 110 includes the first switch unit 112 and the second switch unit 114, the first switch unit 112 is connected to the control module and the second switch unit 114, and the second switch unit 114 is connected to the power supply end P3V3 and the reset output module 200. The first switch unit 112 is turned on when receiving the first type level output by the control module, the second switch unit 114 is turned off and transmits the first type level to the reset output module 200; the first switch unit 112 is turned off when receiving the second type level output by the control module, and the second switch unit 114 is turned on and transmits the second type level to the reset output module 200.

[0028] The control module can also be an FPGA, a CPU, a CPLD, or the like. The first switch unit 112 includes a switch T2 and a resistor R3, and the second switch unit 114 includes a switch T1 and a resistor R1; the control end of the switch T2 is connected to the control module, the first end of the switch T2 is connected to the first end of the resistor R3 and the control end of the switch T1, the second end of the switch T2 is grounded, the second end of the resistor R3 is connected to the power supply end P3V3, the first end of the switch T1 is connected to the first end of the resistor R1 and the reset output module 200, the second end of the resistor R1 is connected to the power supply end P3V3, and the second end of the switch T1 is grounded. In addition, the instruction reset operation module 110 can also include a resistor R7, and the control end of the switch T2 is connected to the control module through the resistor R7. The switch T1 and the switch T2 can be controlled switches such as transistors and MOS tubes. In this embodiment, the switch T1 and the switch T2 are both transistors, the base B is the control end, the collector C is the first end, and the emitter E is the second end.

[0029] In one embodiment, the reset operation module 100 includes a hardware reset operation module 120. The hardware reset operation module 120 includes a button S1 and a resistor R10. A first side of the button S1 is connected to a first terminal of the resistor R10 and a reset output module 200. A second side of the button S1 is grounded, and a second terminal of the resistor R10 is connected to a power supply terminal P3V3. Further, the hardware reset operation module 120 also includes a capacitor C3, which is connected in parallel with the button S1.

[0030] In one embodiment, the reset operation module 100 includes a self-reset operation module 130. The self-reset operation module 130 is connected to the main control unit 300 and the reset output module 200. When the self-reset signal output by the main control unit 300 is a second-type level, it outputs a second-type level to the reset output module 200, thereby achieving self-reset of the main control unit 300. Alternatively, when the self-reset operation module 130 outputs a first-type level to the reset output module 200, and the reset output module 200 outputs a first-type level to the main control unit 300, the main control unit 300 terminates the reset upon receiving the first-type level.

[0031] Specifically, such as Figure 2 As shown, the self-reset operation module 130 includes a delay chip U4, resistors R6 and R9, and capacitor C5. The VIN pin of the delay chip U4 is connected to the first terminals of resistors R6 and R9. The second terminal of resistor R6 is connected to the main control unit 300, and the second terminal of resistor R9 is connected to the power supply terminal P3V3. The GND pin of the delay chip U4 is grounded. The ENIN and VCC pins of the delay chip U4 are connected to the power supply terminal P3V3. The CEXT pin of the delay chip U4 is connected to the first terminal of capacitor C5, and the second terminal of capacitor C5 is grounded. The ENOUT pin of the delay chip U4 is connected to the reset output module 200. Alternatively, the self-reset operation module 130 may also include capacitors C4 and C7. The first terminal of capacitor C4 is connected to the ENIN pin of the delay chip U4, and the second terminal of capacitor C4 is grounded. The first terminal of capacitor C7 is connected to the VCC pin of the delay chip U4, and the second terminal of capacitor C7 is grounded.

[0032] It is understandable that the specific structure of the reset output module 200 will vary depending on the number of reset operation modules 100. In one embodiment, such as... Figure 2As shown, the reset output module 200 includes an AND gate U1, resistors R4 and R5. Input A of AND gate U1 is connected to the first end of resistor R5, and the second end of resistor R5 is connected to a corresponding reset operation module 100. Input B of AND gate U1 is connected to the first end of resistor R4, and the second end of resistor R4 is connected to a corresponding reset operation module 100. The power supply pin VCC of AND gate U1 is connected to the power supply terminal P3V3, and the ground pin GND of AND gate U1 is grounded. When both input A and input B receive a first-type level, AND gate U1 outputs a first-type level from its output terminal Y. When input A and / or input B receive a second-type level, AND gate U1 outputs a second-type level from its output terminal Y. Furthermore, the reset output module 200 may also include a capacitor C1. The first end of capacitor C1 is connected to the power supply pin VCC of AND gate U1, and the other end of capacitor C1 is grounded. In this embodiment, when there are two reset output modules 200, the output terminal Y of AND gate U1 can be directly connected to the main control unit 300 to output a corresponding reset signal.

[0033] Furthermore, the reset output module 200 also includes an AND gate U2 and a resistor R8. Input A of AND gate U2 is connected to a corresponding reset operation module 100, input B of AND gate U2 is connected to the output Y of AND gate U1, the power supply pin VCC of AND gate U2 is connected to the power supply pin P3V3, and the ground pin GND of AND gate U2 is grounded. When both input A and input B receive a first-type level, AND gate U2 outputs a first-type level from its output Y. When input A and / or input B receive a second-type level, AND gate U2 outputs a second-type level from its output Y. Additionally, the reset output module 200 may also include a capacitor C2. One end of capacitor C2 is connected to the power supply pin VCC of AND gate U2, and the other end of capacitor C2 is grounded. In this embodiment, the output Y of AND gate U2 can be connected to the main control unit 300. The reset output module 200, by combining the two AND gates, can receive and process the level signals output by the three reset operation modules 100, and output the corresponding reset signal RESET.

[0034] It is understandable that when there are more reset operation modules 100, the output terminal Y of AND gate U2 can be cascaded with more AND gates to support more reset operation modules 100 with different operation modes to perform reset operations on the main control unit 300.

[0035] by Figure 2For example, the reset operation module 100 includes an instruction reset operation module 110, a hardware reset operation module 120 and a self-reset operation module 130. In the reset output module 200, the second end of the resistor R4 is connected to the instruction reset operation module 110, specifically connected to the first end of the switch T1, the second end of the resistor R5 is connected to the hardware reset operation module 120, specifically connected to the first side of the key S1 and the first end of the resistor R10, the input end A of the AND gate U2 is connected to the self-reset operation module 130, specifically connected to the ENOUT pin of the delay chip U4, the output end Y of the AND gate U2 is connected to the reset pin of the master control unit 300, and the reset signal RESET is output. The second end of the resistor R6 in the self-reset operation module 130 is connected to the self-reset control pin of the master control unit 300, and receives the self-reset signal RESET_CTRL.

[0036] The master control unit reset circuit provided by the application has three reset modes to realize reset. The three reset modes are combined by two AND gates. Among them, the SIG1 signal and the SIG2 signal are connected to the input pins B and A of the AND gate U1 respectively, the output signal of the AND gate U1 and the SIG3 signal are connected to the input pins B and A of the AND gate U2 respectively, and the output pin Y of the AND gate U2 is connected to the reset pin of the master control unit 300, and the reset signal RESET is output. When the SIG1 signal, the SIG2 signal and the SIG3 signal are all high, the reset signal RESET received by the reset pin of the master control unit 300 is high, and no reset is performed; when one of the SIG1 signal, the SIG2 signal and the SIG3 signal is low, due to the characteristics of the AND gate, the reset signal RESET received by the master control unit 300 will become low, and the reset operation is performed.

[0037] The first reset mode is RST1 signal, one end of RST1 signal is connected to the control module, and the other end of RST1 signal is connected to the B pole of switch T2. When RST1 signal is high, the voltage between BE poles of switch T2 reaches the start voltage, the switch T2 is turned on between BE poles, so that the switch T2 is turned on between CE poles, and the C pole of switch T2 is grounded to low. Because the C pole of switch T2 is grounded to low, the voltage between BE poles of switch T1 cannot reach the start voltage, and the switch T1 is not started. The C pole of switch T1 is pulled up by the power supply end P3V3 (connected to P3V3 power supply through resistor R1), and SIG1 signal is high. When RST1 is low, the BE pole of switch T2 is not turned on, and the C pole of switch T2 is pulled up by P3V3 power supply (connected to P3V3 power supply through R3 resistor), so that the voltage between BE poles of switch T1 reaches the start voltage, the switch T1 is turned on, the C pole of switch T1 is grounded to low, and SIG1 signal is also low. This reset mode is used for other module control main control unit 300 reset operation, and the SIG1 signal and RST1 signal are controlled by the combination of triode, without considering the level matching problem between the control module and the main control unit 300.

[0038] The second reset mode is the key S1 in Figure 2 , which is a hardware reset mode. The first side of key S1 is connected to SIG2 signal, and SIG2 signal is pulled up by resistor R10 to ensure the steady state of SIG2 signal. When the key S1 is pressed, SIG2 signal is connected to ground, SIG2 signal is pulled down, and hard reset is realized.

[0039] The third reset mode is self-reset, that is Figure 2The self-reset signal RESET_CTRL is used in the delay chip U4. Specifically, the delay chip U4 can be an ADM1085 chip. One end of the RESET_CTRL signal is connected to the self-reset control pin of the main control unit 300, and the other end is connected to the VIN pin of the delay chip U4. The ENIN pin of the delay chip U4 is connected to the power supply P3V3. When the RESET_CTRL signal is pulled low, the VIN pin of the delay chip U4 is pulled low, which momentarily pulls the ENOUT pin of the delay chip U4 low, causing the SIG3 signal to go low. This, in turn, pulls down the reset pin of the main control unit 300, thus resetting the main control unit 300. When the main control unit 300 is reset, its self-reset control pin is released. Under the pull-up effect of resistor R9, the self-reset signal RESET_CTRL goes high. Due to the characteristics of the ADM1085 chip, when the VIN pin is greater than 0.6V, a delay is applied based on the capacitor C5 connected to the CEXT pin. After the delay, the ENOUT pin goes high, which in turn pulls up the reset pin of the main control unit 300, thus ending the reset of the main control unit 300. The reset time can be controlled by changing the value of capacitor C5 on the CEXT pin of the delay chip U4.

[0040] The internal delay mechanism of the ADM1085 chip is as follows: Figure 3 As shown, the voltage level connected to the VIN pin of the ADM1085 chip is compared with an internal set voltage value (e.g., 0.6V). When the VIN pin voltage level is higher than the set voltage value, it is delayed by an adjustable delay capacitor inside the chip. After the delay, when the ENIN pin is high, the ENOUT pin of the AND gate will output a high level. The delay mechanism is as follows. Figure 4 As shown, when the VIN pin is pulled high (from low to high, greater than 0.6V, and the ENIN pin remains high), the transistor inside the ADM1085 chip conducts. At this time, the internal current source of the chip (specifically, a 250nA current source) will affect the internal capacitor C. INT During charging, once the voltage level exceeds a threshold voltage (e.g., 1.2V), the ENOUT pin will be pulled high. The charging delay time can be increased by connecting an external capacitor C5 to the CEXT pin of the ADM1085 chip; the specific delay time can be determined by changing the capacitance value of C5.

[0041] In one embodiment, a test machine is also provided, comprising a master control unit and the master control unit reset circuit described above. The master control unit can be a master control chip such as FPGA, CPU, CPLD, etc. The master control unit and the master control unit reset circuit described above can be arranged on a resource board card of the test machine. Through reset control in multiple ways in the test machine, long-time operation and stability of the master control unit can be ensured, and the risk of unnecessary power-off of the board card can be reduced.

[0042] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as falling within the scope of the present disclosure.

[0043] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the utility model patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A main control unit reset circuit, characterized in that, The reset output module is connected with each reset operation module and a master control unit; each reset operation module sends a corresponding level signal to the reset output module through a different type of operation mode; when at least one of the received level signals is a preset type level, the reset output module outputs a reset signal to the master control unit to perform a reset operation on the master control unit.

2. The master unit reset circuit of claim 1, wherein, The reset operation module includes at least two of an instruction reset operation module, a hardware reset operation module and a self-reset operation module; when each reset operation module outputs a first type level, the reset output module outputs the first type level to the master control unit; when at least one reset operation module outputs a second type level, the reset output module outputs the second type level to the master control unit; the preset type level and the reset signal are both the second type level.

3. The master reset circuit of claim 2, wherein, The reset operation module includes an instruction reset operation module, the instruction reset operation module includes a first switch unit and a second switch unit, the first switch unit is connected with a control module and the second switch unit, and the second switch unit is connected with a power supply end and the reset output module. When the first switch unit receives a first type level output by the control module, the first switch unit is turned on, and the second switch unit is turned off and transmits the first type level to the reset output module. When the first switch unit receives a second type level output by the control module, the first switch unit is turned off, and the second switch unit is turned on and transmits the second type level to the reset output module.

4. The master reset circuit of claim 3, wherein, The first switch unit includes a switch T2 and a resistor R3, and the second switch unit includes a switch T1 and a resistor R1; a control end of the switch T2 is connected with the control module, a first end of the switch T2 is connected with a first end of the resistor R3 and a control end of the switch T1, a second end of the switch T2 is grounded, a second end of the resistor R3 is connected with a power supply end, a first end of the switch T1 is connected with a first end of the resistor R1 and the reset output module, a second end of the resistor R1 is connected with the power supply end, and a second end of the switch T1 is grounded.

5. The master reset circuit of claim 2, wherein, The reset operation module includes a hardware reset operation module, the hardware reset operation module includes a key S1 and a resistor R10, a first side of the key S1 is connected with a first end of the resistor R10 and the reset output module, a second side of the key S1 is grounded, and a second end of the resistor R10 is connected with a power supply end.

6. The master reset circuit of claim 2, wherein, The reset operation module includes a self-reset operation module, the self-reset operation module is connected with the master control unit and the reset output module, and outputs a second type level to the reset output module when a self-reset signal output by the master control unit is the second type level.

7. The master unit reset circuit of claim 6, wherein, The self-resetting operation module comprises a delay chip, a resistor R6, a resistor R9 and a capacitor C5, a VIN pin of the delay chip is connected with a first end of the resistor R6 and a first end of the resistor R9, a second end of the resistor R6 is connected with the master control unit, a second end of the resistor R9 is connected with a power supply end, a GND pin of the delay chip is grounded, an ENIN pin and a VCC pin of the delay chip are connected with the power supply end, a CEXT pin of the delay chip is connected with a first end of the capacitor C5, a second end of the capacitor C5 is grounded, and an ENOUT pin of the delay chip is connected with the reset output module.

8. The master reset circuit of any one of claims 1-7, wherein, The reset output module comprises an AND gate U1, a resistor R4 and a resistor R5, an input end A of the AND gate U1 is connected with a first end of the resistor R5, a second end of the resistor R5 is connected with a corresponding reset operation module, an input end B of the AND gate U1 is connected with a first end of the resistor R4, and a second end of the resistor R4 is connected with a corresponding reset operation module; when the AND gate U1 receives the first type level at the input end A and the input end B, the AND gate U1 outputs the first type level from an output end Y, and when the AND gate U1 receives the second type level at the input end A and / or the input end B, the AND gate U1 outputs the second type level from the output end Y.

9. The master unit reset circuit of claim 8, wherein, The reset output module further comprises an AND gate U2 and a resistor R8, an input end A of the AND gate U2 is connected with a corresponding reset operation module, an input end B of the AND gate U2 is connected with the output end Y of the AND gate U1; when the AND gate U2 receives the first type level at the input end A and the input end B, the AND gate U2 outputs the first type level from an output end Y, and when the AND gate U2 receives the second type level at the input end A and / or the input end B, the AND gate U2 outputs the second type level from the output end Y.

10. A testing machine characterized by, The master control unit reset circuit comprises a master control unit and the master control unit reset circuit according to any one of claims 1-9.

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