Filtering compensation device of three-level topology

Abstract

The utility model discloses a three-level topological filtering compensation device, which relates to the technical field of filtering compensation and comprises a controller and a three-level topological filtering compensation circuit. The three-level topology filtering compensation circuit comprises a direct current side equalization circuit, a three-level topology first circuit, a three-level topology second circuit and an alternating current side filtering circuit. The direct current side equalization circuit comprises capacitors C1 and C2 which are connected in series, and the capacitors C1 and C2 are respectively connected with a first bidirectional switch tube and a second bidirectional switch tube in parallel; a series circuit formed by the capacitor C1 and the capacitor C2 is respectively connected in parallel with the three-level topology first circuit and the three-level topology second circuit; the controller is connected with the first bidirectional switch tube and the second bidirectional switch tube. According to the invention, the DC side equalization circuit is designed, and the two capacitors are respectively connected in parallel with the bidirectional switch tubes, so that the system efficiency is improved, and load fluctuation can be adapted.

Description

Technical Field

[0001] This application relates to the field of filtering compensation technology, and in particular to a filtering compensation device with a three-level topology. Background Technology

[0002] With the increasing electricity demand from industry and residents, the number of nonlinear loads in the power system is increasing, leading to harmonic pollution and reactive power deficit, which threaten the stability of the power grid and power quality. Therefore, research on filtering and compensation technologies is necessary.

[0003] In the prior art, Chinese patent CN222052895U discloses a dualized three-level topology circuit structure for an active filter, including two sets of dualized three-level topology circuits; the two sets of three-level topology circuits are connected in parallel through two sets of reactors, and the DC side of the two sets of dualized three-level topology circuits is supported by two capacitor banks connected in series to support the DC side voltage, and the DC side voltage is balanced through two voltage stabilizing resistors; the two sets of three-level topology circuits are also connected to a switching module through two sets of reactors respectively, and the phase voltage output of three levels is realized on the AC side through the logic control of the switching module.

[0004] However, the aforementioned existing technology achieves balanced DC-side voltage through two voltage-regulating resistors, resulting in high resistance losses and low system efficiency; moreover, the dynamic response speed is slow, making it difficult to adapt to load fluctuations. Utility Model Content

[0005] This application provides a three-level topology filtering compensation device to solve the problems of high resistance loss, low system efficiency, slow dynamic response speed, and difficulty in adapting to load fluctuations in existing three-level topology filtering technology.

[0006] On the one hand, this application provides a three-level topology filtering compensation device, including: a controller and a three-level topology filtering compensation circuit.

[0007] The three-level topology filter compensation circuit includes: a DC-side equalization circuit, a three-level topology first circuit, a three-level topology second circuit, and an AC-side filter circuit.

[0008] The DC-side equalization circuit includes capacitors C1 and C2 connected in series, with a first bidirectional switch and a second bidirectional switch connected in parallel to each of capacitors C1 and C2.

[0009] The series circuit formed by capacitors C1 and C2 is connected in parallel with the first three-level topology circuit and the second three-level topology circuit, respectively.

[0010] Both the first circuit of the three-level topology and the second circuit of the three-level topology output phase voltage through the AC side filter circuit.

[0011] The controller is connected to the first bidirectional switch and the second bidirectional switch, respectively.

[0012] In one possible implementation, the first bidirectional switching transistor includes MOSFETs Mos1 and Mos2.

[0013] The source of MOSFET Mos1 is connected to the midpoint of capacitors C1 and C2, and the drain is connected to the other end of capacitor C1.

[0014] The drain of MOSFET Mos2 is connected to the midpoint of capacitors C1 and C2, and the source is connected to the other end of capacitor C1.

[0015] The second bidirectional switching transistor includes MOSFETs Mos3 and Mos4.

[0016] The source of MOSFET Mos3 is connected to the midpoint of capacitors C1 and C2, and the drain is connected to the other end of capacitor C2.

[0017] The drain of MOSFET Mos4 is connected to the midpoint of capacitors C1 and C2, and the source is connected to the other end of capacitor C2.

[0018] The controller is connected to the gates of MOSFETs Mos1, Mos2, Mos3, and Mos4, respectively.

[0019] In one possible implementation, the three-level topology first circuit includes: a first three-phase bridge arm and a first parallel clamping circuit.

[0020] The first phase arm of the first three-phase bridge arm includes: IGBT switching transistors Q1, Q4, Q7, and Q10 connected in series.

[0021] The second phase of the first three-phase bridge arm includes: IGBT switches Q2, Q5, Q8, and Q11 connected in series.

[0022] The third phase of the first three-phase bridge arm includes: IGBT switching transistors Q3, Q6, Q9, and Q12 connected in series.

[0023] The first parallel clamping circuit includes clamping diodes D1, D2, D3, D4, D5, and D6.

[0024] Clamping diodes D1 and D2 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q4 and the emitter of IGBT switch Q7.

[0025] Clamping diodes D3 and D4 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q5 and the emitter of IGBT switch Q8.

[0026] Clamping diodes D5 and D6 are connected in parallel, and both are connected in parallel with the collector of IGBT switch Q6 and the emitter of IGBT switch Q9.

[0027] In one possible implementation, each of the IGBT switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, and Q12 has a freewheeling diode inside.

[0028] In one possible implementation, the three-level topology second circuit includes: a second three-phase bridge arm and a second parallel clamping circuit.

[0029] The first phase of the second three-phase bridge arm includes: IGBT switching transistors Q13, Q16, Q19, and Q22 connected in series.

[0030] The second phase of the second three-phase bridge arm includes: IGBT switching transistors Q14, Q17, Q20, and Q23 connected in series.

[0031] The third phase of the second three-phase bridge arm includes: IGBT switching transistors Q15, Q18, Q21, and Q24 connected in series.

[0032] The second parallel clamping circuit includes clamping diodes D7, D8, D9, D10, D11, and D12.

[0033] Clamping diodes D7 and D8 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q16 and the emitter of IGBT switch Q19.

[0034] Clamping diodes D9 and D10 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q17 and the emitter of IGBT switch Q20.

[0035] Clamping diodes D11 and D12 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q18 and the emitter of IGBT switch Q21.

[0036] In one possible implementation, each of the IGBT switching transistors Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, and Q24 has a freewheeling diode inside.

[0037] In one possible implementation, the AC side filter circuit includes: reactors L1, L2, L3, L4, L5, L6, and switches S1, S2, S3.

[0038] One end of reactor L1 is connected to IGBT switching transistors Q4 and Q7, and the other end is connected to switch S1.

[0039] One end of reactor L2 is connected to IGBT switching transistors Q5 and Q8, and the other end is connected to switch S2.

[0040] One end of reactor L3 is connected to IGBT switching transistors Q6 and Q9, and the other end is connected to switch S3.

[0041] One end of reactor L4 is connected to IGBT switching transistors Q16 and Q19, and the other end is connected to switch S1.

[0042] One end of reactor L5 is connected to IGBT switching transistors Q17 and Q20, and the other end is connected to switch S2.

[0043] One end of reactor L6 is connected to IGBT switching transistors Q18 and Q21, and the other end is connected to switch S3.

[0044] Switches S1, S2, and S3 are connected to phase A, phase B, and phase C outputs respectively through an LC filter circuit.

[0045] In one possible implementation, the LC filter circuit connected to switch S1 includes a reactor Lf1 and a capacitor Cf1. The reactor Lf1 is connected in series between switch S1 and the A-phase output, and one end of the capacitor Cf1 is connected between the reactor Lf1 and the A-phase output, while the other end is grounded.

[0046] The LC filter circuit connected to switch S2 includes reactor Lf2 and capacitor Cf2. Reactor Lf2 is connected in series between switch S2 and the output of phase B. One end of capacitor Cf2 is connected between reactor Lf2 and the output of phase B, and the other end is grounded.

[0047] The LC filter circuit connected to switch S3 includes reactor Lf3 and capacitor Cf3. Reactor Lf3 is connected in series between switch S3 and the C-phase output. One end of capacitor Cf3 is connected between reactor Lf3 and the C-phase output, and the other end is grounded.

[0048] In one possible implementation, reactors Ld1 and Ld2 are connected in series between capacitors C1 and C2; reactor Ld1 is located between the midpoint of capacitors C1 and C2 and capacitor C1, and reactor Ld2 is located between the midpoint of capacitors C1 and C2 and capacitor C2.

[0049] The three-level topology filtering compensation device in this application has the following advantages:

[0050] By designing a DC-side equalization circuit and connecting bidirectional switching transistors in parallel to the two capacitors, resistance loss is reduced, system efficiency is improved, and the system has a faster dynamic response speed, enabling it to adapt to load fluctuations.

[0051] The proposed specific structure of the two bidirectional switching transistors is as follows: the controller is connected to the gates of MOSFETs Mos1, Mos2, Mos3, and Mos4 respectively, and the current is dynamically adjusted by detecting the voltage difference between capacitors C1 and C2 to achieve DC-side voltage balance.

[0052] The specific structures of the proposed three-level topology first circuit and three-level topology second circuit reduce the withstand voltage requirement, improve potential stability, and reduce waveform distortion while keeping the circuit structure less complex by connecting two clamping diodes in parallel and in parallel with a bridge arm.

[0053] The proposed switches S1, S2, and S3 are connected to the A-phase output, B-phase output, and C-phase output respectively through an LC filter circuit, further filtering out high-frequency harmonics, improving the output voltage waveform, and reducing electromagnetic interference.

[0054] The proposed DC-side equalization circuit incorporates reactors Ld1 and Ld2 connected in series between capacitors C1 and C2, which suppresses DC-side current spikes and high-frequency ripples, thereby improving system stability. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the structure of a three-level topology filter compensation circuit provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] like Figure 1 As shown in the figure, this application provides a three-level topology filtering compensation device, including: a controller and a three-level topology filtering compensation circuit.

[0059] The three-level topology filter compensation circuit includes: a DC-side equalization circuit, a three-level topology first circuit, a three-level topology second circuit, and an AC-side filter circuit.

[0060] The DC-side equalization circuit includes capacitors C1 and C2 connected in series, with a first bidirectional switch and a second bidirectional switch connected in parallel to each of capacitors C1 and C2.

[0061] The series circuit formed by capacitors C1 and C2 is connected in parallel with the first three-level topology circuit and the second three-level topology circuit, respectively.

[0062] Both the first circuit of the three-level topology and the second circuit of the three-level topology output phase voltage through the AC side filter circuit.

[0063] The controller is connected to the first bidirectional switch and the second bidirectional switch, respectively.

[0064] Specifically, the DC-side equalization circuit is used to realize DC-side energy management, the three-level topology first circuit and the three-level topology second circuit are used to complete the inverter function, and the AC-side filter circuit is used to realize the AC-side filter function.

[0065] For example, the first bidirectional switching transistor includes: MOSFETs Mos1 and Mos2.

[0066] The source of MOSFET Mos1 is connected to the midpoint of capacitors C1 and C2, and the drain is connected to the other end of capacitor C1.

[0067] The drain of MOSFET Mos2 is connected to the midpoint of capacitors C1 and C2, and the source is connected to the other end of capacitor C1.

[0068] The second bidirectional switching transistor includes MOSFETs Mos3 and Mos4.

[0069] The source of MOSFET Mos3 is connected to the midpoint of capacitors C1 and C2, and the drain is connected to the other end of capacitor C2.

[0070] The drain of MOSFET Mos4 is connected to the midpoint of capacitors C1 and C2, and the source is connected to the other end of capacitor C2.

[0071] The controller is connected to the gates of MOSFETs Mos1, Mos2, Mos3, and Mos4, respectively.

[0072] Specifically, in this embodiment, the functions of two bidirectional switching transistors are achieved by reverse connecting MOSFETs Mos1 and Mos2, and reverse connecting MOSFETs Mos3 and Mos4.

[0073] In this embodiment, the working logic of the DC-side equalization circuit is as follows: When the voltage of capacitor C1 is higher than the voltage of capacitor C2, the controller drives MOSFET Mos1 to turn on, and the current flows as follows: positive terminal of capacitor C1 - drain of MOSFET Mos1 - source of MOSFET Mos1 - midpoint of capacitors C1 and C2 - capacitor C2 is charged, thereby reducing the voltage of capacitor C1; when the voltage of capacitor C2 is higher than the voltage of capacitor C1, the controller drives MOSFET Mos3 to turn on, and the current flows as follows: negative terminal of capacitor C2 - drain of MOSFET Mos3 - source of MOSFET Mos3 - midpoint of capacitors C1 and C2 - capacitor C1 is charged, thereby reducing the voltage of capacitor C1.

[0074] For example, the first circuit of the three-level topology includes: a first three-phase bridge arm and a first parallel clamping circuit.

[0075] The first phase arm of the first three-phase bridge arm includes: IGBT switching transistors Q1, Q4, Q7, and Q10 connected in series.

[0076] The second phase of the first three-phase bridge arm includes: IGBT switches Q2, Q5, Q8, and Q11 connected in series.

[0077] The third phase of the first three-phase bridge arm includes: IGBT switching transistors Q3, Q6, Q9, and Q12 connected in series.

[0078] The first parallel clamping circuit includes clamping diodes D1, D2, D3, D4, D5, and D6.

[0079] Clamping diodes D1 and D2 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q4 and the emitter of IGBT switch Q7.

[0080] Clamping diodes D3 and D4 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q5 and the emitter of IGBT switch Q8.

[0081] Clamping diodes D5 and D6 are connected in parallel, and both are connected in parallel with the collector of IGBT switch Q6 and the emitter of IGBT switch Q9.

[0082] For example, each of the IGBT switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, and Q12 has a freewheeling diode inside.

[0083] For example, the second circuit of the three-level topology includes: a second three-phase bridge arm and a second parallel clamping circuit.

[0084] The first phase of the second three-phase bridge arm includes: IGBT switching transistors Q13, Q16, Q19, and Q22 connected in series.

[0085] The second phase of the second three-phase bridge arm includes: IGBT switching transistors Q14, Q17, Q20, and Q23 connected in series.

[0086] The third phase of the second three-phase bridge arm includes: IGBT switching transistors Q15, Q18, Q21, and Q24 connected in series.

[0087] The second parallel clamping circuit includes clamping diodes D7, D8, D9, D10, D11, and D12.

[0088] Clamping diodes D7 and D8 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q16 and the emitter of IGBT switch Q19.

[0089] Clamping diodes D9 and D10 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q17 and the emitter of IGBT switch Q20.

[0090] Clamping diodes D11 and D12 are connected in parallel and are also connected in parallel with the collector of IGBT switch Q18 and the emitter of IGBT switch Q21.

[0091] For example, each of the IGBT switching transistors Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, and Q24 has a freewheeling diode inside.

[0092] Specifically, in this embodiment, the IGBT switching transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, and Q24 all adopt an insulated gate bipolar transistor (IGBT) module.

[0093] In this embodiment, the collectors of IGBT switches Q1, Q2, and Q3 are all connected to the positive terminal of capacitor C1; the emitters of IGBT switches Q10, Q11, and Q12 are all connected to the negative terminal of capacitor C2; the collectors of IGBT switches Q13, Q14, and Q15 are all connected to the positive terminal of capacitor C1; and the emitters of IGBT switches Q22, Q23, and Q24 are all connected to the negative terminal of capacitor C2.

[0094] For example, the AC side filter circuit includes: reactors L1, L2, L3, L4, L5, L6, and switches S1, S2, S3.

[0095] One end of reactor L1 is connected to IGBT switching transistors Q4 and Q7, and the other end is connected to switch S1.

[0096] One end of reactor L2 is connected to IGBT switching transistors Q5 and Q8, and the other end is connected to switch S2.

[0097] One end of reactor L3 is connected to IGBT switching transistors Q6 and Q9, and the other end is connected to switch S3.

[0098] One end of reactor L4 is connected to IGBT switching transistors Q16 and Q19, and the other end is connected to switch S1.

[0099] One end of reactor L5 is connected to IGBT switching transistors Q17 and Q20, and the other end is connected to switch S2.

[0100] One end of reactor L6 is connected to IGBT switching transistors Q18 and Q21, and the other end is connected to switch S3.

[0101] Switches S1, S2, and S3 are connected to phase A, phase B, and phase C outputs respectively through an LC filter circuit.

[0102] For example, the LC filter circuit connected to switch S1 includes a reactor Lf1 and a capacitor Cf1. The reactor Lf1 is connected in series between switch S1 and the A-phase output. One end of the capacitor Cf1 is connected between the reactor Lf1 and the A-phase output, and the other end is grounded.

[0103] The LC filter circuit connected to switch S2 includes reactor Lf2 and capacitor Cf2. Reactor Lf2 is connected in series between switch S2 and the output of phase B. One end of capacitor Cf2 is connected between reactor Lf2 and the output of phase B, and the other end is grounded.

[0104] The LC filter circuit connected to switch S3 includes reactor Lf3 and capacitor Cf3. Reactor Lf3 is connected in series between switch S3 and the C-phase output. One end of capacitor Cf3 is connected between reactor Lf3 and the C-phase output, and the other end is grounded.

[0105] Specifically, in this embodiment, the setting of three LC filter circuits can effectively suppress the high-frequency switching harmonics generated when switches S1, S2, and S3 are working, making the current and voltage flowing into the power grid closer to a sine wave and improving power quality.

[0106] For example, reactors Ld1 and Ld2 are connected in series between capacitors C1 and C2; reactor Ld1 is located between the midpoint of capacitors C1 and C2 and capacitor C1, and reactor Ld2 is located between the midpoint of capacitors C1 and C2 and capacitor C2.

[0107] Specifically, the installation of reactors Ld1 and Ld2 can effectively suppress current ripple in the DC bus, making the DC bus voltage more stable.

[0108] In one possible embodiment, a fuse is connected in series between switch S1 and reactor Lf1, between switch S2 and reactor Lf2, and between switch S3 and reactor Lf3.

[0109] The embodiments of this application design a DC-side equalization circuit, which connects bidirectional switching transistors in parallel to the two capacitors, thereby reducing resistance loss, improving system efficiency, and providing a faster dynamic response speed to adapt to load fluctuations.

[0110] The proposed specific structure of the two bidirectional switching transistors is as follows: the controller is connected to the gates of MOSFETs Mos1, Mos2, Mos3, and Mos4 respectively, and the current is dynamically adjusted by detecting the voltage difference between capacitors C1 and C2 to achieve DC-side voltage balance.

[0111] The specific structures of the proposed three-level topology first circuit and three-level topology second circuit reduce the withstand voltage requirement, improve potential stability, and reduce waveform distortion while keeping the circuit structure less complex by connecting two clamping diodes in parallel and in parallel with a bridge arm.

[0112] The proposed switches S1, S2, and S3 are connected to the A-phase output, B-phase output, and C-phase output respectively through an LC filter circuit, further filtering out high-frequency harmonics, improving the output voltage waveform, and reducing electromagnetic interference.

[0113] The proposed DC-side equalization circuit incorporates reactors Ld1 and Ld2 connected in series between capacitors C1 and C2, which suppresses DC-side current spikes and high-frequency ripples, thereby improving system stability.

[0114] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0115] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A filter compensation device of a three-level topology, characterized by, The application relates to a three-level topology filter compensation circuit. The three-level topology filter compensation circuit comprises a DC side balancing circuit, a three-level topology first circuit, a three-level topology second circuit and an AC side filter circuit. The DC side balancing circuit comprises capacitors C1 and C2 connected in series, and the capacitors C1 and C2 are respectively connected with first and second bidirectional switch tubes in parallel. The series circuit formed by the capacitors C1 and C2 is connected in parallel with the three-level topology first circuit and the three-level topology second circuit respectively. The three-level topology first circuit and the three-level topology second circuit output phase voltages through the AC side filter circuit. The controller is connected with the first and second bidirectional switch tubes respectively. The first bidirectional switch tube comprises MOSFET tubes Mos1 and Mos2.

2. A filter compensation device of a three-level topology according to claim 1, characterized in that, The source of the MOSFET tube Mos1 is connected to the midpoint of the capacitors C1 and C2, and the drain is connected to the other end of the capacitor C1. The drain of the MOSFET tube Mos2 is connected to the midpoint of the capacitors C1 and C2, and the source is connected to the other end of the capacitor C1. The second bidirectional switch tube comprises MOSFET tubes Mos3 and Mos4. The source of the MOSFET tube Mos3 is connected to the midpoint of the capacitors C1 and C2, and the drain is connected to the other end of the capacitor C2. The drain of the MOSFET tube Mos4 is connected to the midpoint of the capacitors C1 and C2, and the source is connected to the other end of the capacitor C2. The controller is connected with the gates of the MOSFET tubes Mos1, Mos2, Mos3 and Mos4 respectively. The three-level topology first circuit comprises a first three-phase bridge arm and a first parallel clamping circuit.

3. The filter compensation device of a three-level topology according to claim 1, characterized in that, The first phase bridge arm of the first three-phase bridge arm comprises IGBT switch tubes Q1, Q4, Q7 and Q10 connected in series. The second phase bridge arm of the first three-phase bridge arm comprises IGBT switch tubes Q2, Q5, Q8 and Q11 connected in series. The third phase bridge arm of the first three-phase bridge arm comprises IGBT switch tubes Q3, Q6, Q9 and Q12 connected in series. The first parallel clamping circuit comprises clamping diodes D1, D2, D3, D4, D5 and D6. The clamping diodes D1 and D2 are connected in parallel and are connected in parallel with the collector of the IGBT switch tube Q4 and the emitter of the IGBT switch tube Q7. The clamping diodes D3 and D4 are connected in parallel and are connected in parallel with the collector of the IGBT switch tube Q5 and the emitter of the IGBT switch tube Q8. The clamping diodes D5 and D6 are connected in parallel and are connected in parallel with the collector of the IGBT switch tube Q6 and the emitter of the IGBT switch tube Q9. Each of the IGBT switch tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 is provided with a freewheeling diode.

4. The filter compensation device of a three-level topology according to claim 3, characterized in that, The three-level topology second circuit comprises a second three-phase bridge arm and a second parallel clamping circuit.

5. The filter compensation device of claim 1, wherein, The first phase bridge arm of the second three-phase bridge arm comprises IGBT switch tubes Q13, Q16, Q19 and Q22 connected in series. The second phase bridge arm of the second three-phase bridge arm comprises IGBT switch tubes Q14, Q17, Q20 and Q23 connected in series. ​ The third phase bridge arm of the second three-phase bridge arm comprises: IGBT switch tubes Q15, Q18, Q21 and Q24 connected in series; The second parallel clamping circuit comprises: clamping diodes D7, D8, D9, D10, D11 and D12; The clamping diodes D7 and D8 are connected in parallel and are both connected in parallel with the collector of the IGBT switch tube Q16 and the emitter of Q19; The clamping diodes D9 and D10 are connected in parallel and are both connected in parallel with the collector of the IGBT switch tube Q17 and the emitter of Q20; The clamping diodes D11 and D12 are connected in parallel and are both connected in parallel with the collector of the IGBT switch tube Q18 and the emitter of Q21.

6. A filter compensation device of a three-level topology according to claim 5, characterized in that, The IGBT switch tubes Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23 and Q24 are each provided with a freewheeling diode.

7. The filter compensation device of claim 1, wherein, The AC side filter circuit comprises: reactors L1, L2, L3, L4, L5 and L6, and switches S1, S2 and S3. One end of the reactor L1 is connected between the IGBT switch tubes Q4 and Q7, and the other end is connected with the switch S1. One end of the reactor L2 is connected between the IGBT switch tubes Q5 and Q8, and the other end is connected with the switch S2. One end of the reactor L3 is connected between the IGBT switch tubes Q6 and Q9, and the other end is connected with the switch S3. One end of the reactor L4 is connected between the IGBT switch tubes Q16 and Q19, and the other end is connected with the switch S1. One end of the reactor L5 is connected between the IGBT switch tubes Q17 and Q20, and the other end is connected with the switch S2. One end of the reactor L6 is connected between the IGBT switch tubes Q18 and Q21, and the other end is connected with the switch S3. The switches S1, S2 and S3 are respectively connected with the A-phase output, the B-phase output and the C-phase output through an LC filter circuit.

8. A filter compensation device of a three-level topology according to claim 7, characterized in that, The LC filter circuit connected with the switch S1 comprises a reactor Lf1 and a capacitor Cf1, the reactor Lf1 is connected in series between the switch S1 and the A-phase output, and one end of the capacitor Cf1 is connected between the reactor Lf1 and the A-phase output, and the other end is grounded. The LC filter circuit connected with the switch S2 comprises a reactor Lf2 and a capacitor Cf2, the reactor Lf2 is connected in series between the switch S2 and the B-phase output, and one end of the capacitor Cf2 is connected between the reactor Lf2 and the B-phase output, and the other end is grounded. The LC filter circuit connected with the switch S3 comprises a reactor Lf3 and a capacitor Cf3, the reactor Lf3 is connected in series between the switch S3 and the C-phase output, and one end of the capacitor Cf3 is connected between the reactor Lf3 and the C-phase output, and the other end is grounded.

9. The filter compensation device of claim 1, wherein, Capacitors C1 and C2 are connected in series with reactors Ld1 and Ld2; the reactor Ld1 is located between the midpoint of the capacitors C1 and C2 and the capacitor C1, and the reactor Ld2 is located between the midpoint of the capacitors C1 and C2 and the capacitor C2.

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