Packaging chip

Abstract

The utility model discloses a packaging chip. The packaging chip comprises a substrate; the first side of the substrate bears a chipset, the chipset comprises at least two storage chips stacked in a step shape, the storage chips are electrically connected through binding wires, and the storage chips and the substrate are electrically connected through binding wires; the second side of the substrate bears a logic chip, the second side is opposite to the first side, and the logic chip is electrically connected with the storage chip through a conductive hole and a binding wire in the substrate. Through the mode, the chip with a smaller packaging size can be provided.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a packaged chip. Background Technology

[0002] With the development of science and technology, in the field of memory packaging, an increasing number of chips need to be placed inside a single packaging unit to meet task requirements. As the storage demand of memory packaging products increases, more and more memory chips need to be placed inside. To reduce the size of memory packaging products, the memory chips are stacked before packaging to reduce their footprint on the substrate. However, in addition to memory chips, memory packaging products may also contain logic chips such as controllers. These logic chips, in order to maintain normal logic functions, are usually not stacked, which results in a larger substrate area being occupied. Therefore, even with stacked memory chips, the size of memory packaging products remains relatively large when the performance requirements of memory packaging units become increasingly demanding. Utility Model Content

[0003] The primary objective of this application is to provide a packaged chip that enables a smaller package size.

[0004] In a first aspect, this application provides a packaged chip. The packaged chip includes a substrate; a first side of the substrate carries a chip group, the chip group including at least two memory chips stacked in a stepped manner, the memory chips being electrically connected to each other and to the substrate via bonding wires; a second side of the substrate carries a logic chip, the second side being opposite to the first side, the logic chip being electrically connected to the memory chips via conductive holes and bonding wires in the substrate.

[0005] The packaged chip includes a first sealing structure, which is disposed on a first side, and the memory chip and bonding wire are disposed in the first sealing structure.

[0006] The packaged chip includes a second sealing structure, which is disposed on the second side, and the logic chip is disposed in the second sealing structure.

[0007] The packaged chip includes solder balls, which are electrically connected to the second side of the substrate via conductive pillars.

[0008] The solder ball portion is located within the second sealing structure.

[0009] The memory chip has contacts for bonding linear connections, and these contacts are located on the side of the memory chip away from the substrate.

[0010] The memory chip is positioned parallel to the first side.

[0011] The memory chips are stacked in a direction perpendicular to the first side.

[0012] The memory chips are stacked using a chip bonding method.

[0013] In this process, the memory chip and the substrate are stacked together by chip bonding.

[0014] The beneficial effects of this application are: by setting memory chips and logic chips on both sides of the substrate, and electrically connecting the memory chips and logic chips to the substrate, the mounting surface area of ​​the substrate is reduced, the space occupied by the substrate is reduced, and a smaller product size is provided. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of the first embodiment of the packaged chip in this application;

[0017] Figure 2 This is a schematic diagram of the structure of the second embodiment of the packaged chip in this application;

[0018] Figure 3 This is a schematic diagram of the structure of the third embodiment of the packaged chip in this application;

[0019] Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the packaged chip in this application;

[0020] Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the packaged chip in this application;

[0021] Figure 6 This is a schematic diagram of the sixth embodiment of the packaged chip in this application.

[0022] Explanation of reference numerals in the attached figures:

[0023] Substrate 100; conductive hole 110; chipset 200; memory chip 210; logic chip 300; bonding wire 400; contact 500; first sealing structure 600; second sealing structure 700; solder ball 800; conductive post 900. Detailed Implementation

[0024] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0028] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0030] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0031] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0032] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the packaged chip in this application.

[0033] The packaged chip includes a substrate 100, a chipset 200, and a logic chip 300.

[0034] A chipset 200 is supported on a first side of a substrate 100. The chipset 200 includes at least two memory chips 210 stacked in a stepped manner. The memory chips 210 are electrically connected to each other and to the substrate 100 via bonding lines 400.

[0035] A logic chip 300 is carried on the second side of the substrate 100, which is opposite to the first side. The logic chip 300 is electrically connected to the memory chip 210 through conductive holes 110 and bonding lines 400 in the substrate 100.

[0036] For ease of explanation, Figure 1 In this design, the direction perpendicular to the substrate 100 is defined as direction A, and the direction parallel to the substrate 100 is defined as direction B. The positive direction of direction A corresponds to the second side and the first side of the substrate 100, respectively. A chipset 200 is disposed on the first side of the substrate 100, and a logic chip 300 is disposed on the second side of the substrate 100.

[0037] A wiring layer (not shown) is provided on both the first and second surfaces of the substrate 100. The metal traces in the wiring layer are connected to the conductive vias 110 so that the memory chip 210 on the first side of the substrate 100 and the logic chip 300 on the second side are electrically connected through the wiring layer, the conductive vias 110 in the substrate 100, and the bonding wires 400.

[0038] In this embodiment, by setting memory chips and logic chips on both sides of the substrate, and electrically connecting both memory chips and logic chips to the substrate, the mounting surface area of ​​the substrate is reduced, the space occupied by the substrate is reduced, and a smaller product size is provided.

[0039] In some embodiments, the memory chip is further provided with contacts 500 for electrical connection of the bonding line 400, and the contacts 500 of the memory chip 210 are provided on the side of the memory chip 210 away from the substrate 100.

[0040] In some embodiments, the two memory chips 210 connected by the binding line 400 may be adjacent or not adjacent.

[0041] In some embodiments, the logic chip 300 is directly disposed on the substrate 100 and electrically connected to the wiring layer on the second side of the substrate 100.

[0042] In some embodiments, the logic chip 300 is electrically connected to the wiring layer on the second side of the substrate 100 via conductive pillars.

[0043] In some embodiments, the number of logic chips 300 disposed on the second side of the substrate 100 is multiple.

[0044] In some embodiments, at least two chips 210 in the chipset 200 are stacked by chip bonding. Chip bonding may include adhesive bonding, including bonding chips using non-conductive adhesive. The non-conductive adhesive provides only mechanical fixation.

[0045] Non-conductive adhesives can include DAF adhesives, which have excellent bonding and thermal conductivity properties, remain stable in high-temperature environments, and provide reliable mechanical connections and thermal management for chips.

[0046] Reference Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the packaged chip in this application.

[0047] The packaged chip includes a substrate 100, a chipset 200, a logic chip 300, and a first sealing structure 600. The first sealing structure 600 is disposed on a first side, and the memory chip 210 and the bonding wire 400 are disposed in the first sealing structure 600.

[0048] The first sealing structure 600 encloses the chipset 200 and the bonding wire 400. The first sealing structure 600 encloses the chipset 200, protecting each memory chip 210 within it from external dust, moisture, and other impurities. It also provides electrical isolation between the chipset 200 and the external environment, ensuring the operational performance of each memory chip 210. Furthermore, the first sealing structure 600 also encloses the bonding wire 400, protecting it from friction, scratches, and other damage. Simultaneously, the first sealing structure 600 supports and fixes the bonding wire 400, helping to maintain its shape, ensuring a stable connection between the bonding wire 400 and the memory chip 210, and facilitating the connection between the bonding wire 400 and the wiring layer on the substrate 100.

[0049] The first sealing structure 600 can be formed by wrapping the molding compound in a molten state around the chipset 200 and the bonding wire 400, and then cooling and solidifying it to form the first sealing structure 600. The basic components of the molding compound can include a base resin, fillers, curing agents, and additives. The base resin includes a main agent (such as o-cresol-formaldehyde type or alicyclic modified epoxy resin) and a flame-retardant resin (such as olfactory epoxy resin), which provides adhesive and thermosetting properties. The curing agent can include linear phenolic resin, acid alcohol, aromatic amines, etc., which initiate the cross-linking reaction of the epoxy resin to form a stable structure. The fillers can include silica (crystalline or molten), bauxite, aluminum nitride, calcium silicate, etc., which are used to adjust the coefficient of thermal expansion (CTE), improve mechanical strength, and increase thermal conductivity. Additives may include curing accelerators (imidazolium, tertiary amines, phosphorus compounds, etc.), release agents (aliphatic esters, fatty acids and their salts, etc.), toughening agents (silicone rubber, nitrile rubber, etc.), coupling agents (organosilanes, titanate, etc.), colorants (carbon black, dyes, etc.), flame retardant additives (antimony trioxide, etc.), and modifiers, etc.

[0050] The molding compound used in this embodiment can be epoxy molding compound EMC (Epoxy Molding Compound).

[0051] Reference Figure 3 , Figure 3 This is a schematic diagram of the structure of the third embodiment of the packaged chip in this application.

[0052] The packaged chip includes a substrate 100, a chipset 200, a logic chip 300, and a second sealing structure 700. The second sealing structure 700 is disposed on the second side, and the logic chip 300 is disposed within the second sealing structure 700.

[0053] The formation and constituent materials of the second sealing structure are similar to those of the first sealing structure, and will not be described again here. The constituent materials of the first sealing structure may be exactly the same as those of the second sealing structure, or they may be different.

[0054] Reference Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the packaged chip in this application.

[0055] The packaged chip includes a substrate 100, a chipset 200, a logic chip 300, a first sealing structure 600, and a second sealing structure 700. The first sealing structure 600 is disposed on a first side, and the memory chip 210 and the bonding wire 400 are disposed within the first sealing structure 600. The second sealing structure 700 is disposed on a second side, and the logic chip 300 is disposed within the second sealing structure 700.

[0056] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the packaged chip in this application.

[0057] The packaged chip includes a substrate 100, a chipset 200, a logic chip 300, a first sealing structure 600, a second sealing structure 700, and solder balls 800.

[0058] A chipset 200 is supported on a first side of a substrate 100. The chipset 200 includes at least two memory chips 210 stacked in a stepped manner. The memory chips 210 are electrically connected to each other and to the substrate 100 via bonding lines 400.

[0059] A logic chip 300 is carried on the second side of the substrate 100, which is opposite to the first side. The logic chip 300 is electrically connected to the memory chip 210 through conductive holes 110 and bonding lines 400 in the substrate 100.

[0060] A first sealing structure 600 is disposed on the first side, and the memory chip 210 and the bonding line 400 are disposed within the first sealing structure 600. A second sealing structure 700 is disposed on the second side, and the logic chip 300 is disposed within the second sealing structure 700.

[0061] Solder ball 800 is electrically connected to the second side of substrate 100 via conductive post 900.

[0062] In the above embodiment, the solder balls 800 are partially disposed within the second sealing structure 700. The solder balls 800 are partially exposed outside the second sealing structure 700 to facilitate electrical connection between the packaged chip and other electronic devices. Other electronic devices can achieve electrical connection with the chipset 200 and / or logic chip 300 within the packaged chip by connecting the solder balls 800.

[0063] When setting up the second sealing structure, since the solder ball 800 has already been implanted on the substrate 100, in order to allow the solder ball 800 to be partially set outside the second sealing structure 700, a release film process can be used. When setting up the second sealing structure 700, a release film is used to wrap the second side of the substrate 100, so that the solder ball 800 can enter the release film during molding and will not be completely squeezed into the second sealing structure 700, thus ensuring the exposed height of the solder ball.

[0064] In some embodiments, the memory chip is disposed parallel to the first side.

[0065] Furthermore, in some embodiments, the memory chips are stacked in a direction perpendicular to the first side.

[0066] Specifically, refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the sixth embodiment of the packaged chip in this application. During the setup of the chipset 200, the memory chips 210 are placed along direction B and then stacked along direction A. The redistribution layer is set along direction B.

[0067] In some embodiments, the memory chips 210 in the chipset 200 can be stacked sequentially on the bottom layer of memory chips 210 in a gradually staggered manner along the positive direction of direction B, so as to expose the contacts 500 of the memory chips 210 below the top layer near the left edge.

[0068] In some embodiments, the memory chips 210 in the chipset 200 can be stacked sequentially on the bottom layer of memory chips 210 in a gradually staggered manner in the opposite direction of direction B, so as to expose the contacts 500 of the memory chips 210 below the top layer located near their right edges.

[0069] In summary, by placing memory chips and logic chips on both sides of the substrate, and electrically connecting both chips to the substrate and interconnecting them through conductive holes in the substrate, the mounting surface area of ​​the substrate is reduced, the space occupied by the substrate is reduced, and a smaller product size is provided.

[0070] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0071] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0072] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0073] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A packaged chip, comprising: Comprise: a substrate; a first side of the substrate carries a chip set, the chip set comprises at least two memory chips stacked in a stepped manner, the memory chips are electrically connected through bonding wires between the memory chips and between the memory chips and the substrate; a second side of the substrate carries a logic chip, the second side is opposite to the first side, the logic chip is electrically connected with the memory chips through conductive holes in the substrate and the bonding wires.

2. The chip package of claim 1, wherein The chip comprises a first sealing structure, the first sealing structure is arranged on the first side, the memory chips and the bonding wires are arranged in the first sealing structure.

3. The chip package of claim 1, wherein The chip comprises a second sealing structure, the second sealing structure is arranged on the second side, the logic chip is arranged in the second sealing structure.

4. The chip package of claim 3, wherein The chip comprises a tin ball, the tin ball is electrically connected with the second side of the substrate through a conductive column.

5. The chip package of claim 4, wherein, The tin ball is partially arranged in the second sealing structure.

6. The chip package of claim 1, wherein The memory chips are provided with contacts for electrical connection of the bonding wires, the contacts of the memory chips are arranged on a side of the memory chips away from the substrate.

7. The chip package of claim 1, wherein The memory chips are arranged parallel to the first side.

8. The chip package of claim 7, wherein, The memory chips are stacked in a direction perpendicular to the first side.

9. The chip package of claim 1, wherein The memory chips are stacked by chip bonding.

10. The chip package of claim 1, wherein The memory chips and the substrate are stacked by chip bonding.

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