25G clock data recovery instrument

Abstract

The utility model discloses a 25G clock data recovery instrument which is composed of a clock extraction circuit and a high-speed signal input interface. The clock extraction circuit can accurately extract a clock signal from a 25G high-speed data signal, and a phase comparator, a voltage-controlled oscillator and a loop filter are utilized to track the phase change of the signal and generate a stable local clock synchronous with the data rate. The problem that a clock is easily interfered in high-speed data transmission is solved, a stable reference is provided for data processing and transmission, and the bit error rate is reduced. The high-speed signal input interface receives 25G data streams and works cooperatively with the clock extraction circuit. The stable local clock ensures that all links are accurately synchronized when data are received and processed, the data are processed according to a correct time sequence, the data processing efficiency is improved, the data integrity is ensured, and the system can meet application scenes such as 5G communication and high-speed network transmission which have high requirements for speed and stability.

Description

Technical Field

[0001] This utility model belongs to the field of communication technology, specifically a 25G clock data recovery device. Background Technology

[0002] With the rapid development of modern communication technology, data transmission rates are constantly increasing. 25G data transmission rates are widely used in many fields, such as 25G Ethernet and high-speed optical communication links. Signal transmission at this rate faces many severe challenges. Accurately recovering a stable and low-jitter clock signal from high-speed data streams is crucial.

[0003] Traditional clock recovery techniques struggle to meet the high-precision requirements of clock extraction when dealing with high-speed signals like 25 GHz due to complex signal spectrum characteristics and severe noise interference. For example, minute jitter in high-speed signals can be amplified during clock recovery, leading to data sampling errors and increasing the bit error rate. Utility Model Content

[0004] The purpose of this invention is to provide a 25G clock data recovery instrument to solve the problem that, in the prior art, traditional clock recovery technology is difficult to meet the high-precision requirements of clock extraction when facing high speeds such as 25G due to the complex signal spectrum characteristics and severe noise interference.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A 25G clock data recovery device includes a clock extraction circuit and a high-speed signal input interface;

[0007] The clock extraction circuit is used to extract the clock signal from the high-speed data signal; it tracks the phase change of the input data signal through a phase comparator, a voltage-controlled oscillator, and a loop filter, thereby generating a stable local clock signal whose frequency is correlated with and synchronized with the data signal rate.

[0008] The high-speed signal input interface is used to receive data streams at a rate of 25G.

[0009] According to the above technical solution, the high-speed signal input interface includes connector J2, capacitors C14, C15, C16, C17, C18, C28, C29, C30, inductor L1, and inductor L2.

[0010] Pin 13 of connector J2 is connected to one end of capacitor C15, and the other end of capacitor C15 is connected to the clock extraction circuit; pin 12 of connector J2 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the clock extraction circuit.

[0011] Pins 21 to 31 of connector J2 are all connected to one end of capacitor C28, and the other end of capacitor C28 is grounded.

[0012] Pin 3 of connector J2 is grounded; pin 16 of connector J2 is connected to one end of capacitor C14 and inductor L1, and the other end of capacitor C14 is grounded; the other end of inductor L1 is connected to one end of capacitors C17 and C29 and inductor L2; the other end of inductor L2 is connected to one end of capacitors C18 and C30 and pin 15 of connector J2.

[0013] Pins 10, 11, 14, 17, 20, and pin 1 of connector J2 are all grounded.

[0014] According to the above technical solution, inductor L2, capacitor C17, and capacitor C19 are also connected to the power supply.

[0015] According to the above technical solution, the other end of capacitors C17 and C29 is grounded; the other end of capacitors C18 and C30 is grounded.

[0016] According to the above technical solution, the clock extraction circuit includes chip D4, connectors J7, J8, J9, and J10, capacitors C19, C20, C21, C22, C23, C24, C25, C26, C27, C33, and C34, resistors R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, and R19, diodes LED1 and LED2, transistor Q1, and transistor Q2.

[0017] Pins 1 and 2 of chip D4 are both connected to the power supply; pin 3 of chip D4 is connected to one end of capacitor C25, and the other end of capacitor C25 is grounded; pin 4 of chip D4 is connected to capacitor C16, and pin 5 of chip D4 is connected to capacitor C15.

[0018] Pins 6, 7, and 8 of chip D4 are grounded; pin 9 of chip D4 is connected to one end of capacitor C27 and resistor R10, and the other end of capacitor C27 and resistor R10 is grounded; pins 10 and 12 of chip D4 are connected to the power supply; pins 11 and 13 of chip D4 are grounded; pin 14 of chip D4 is connected to one end of capacitor C34, and the other end of capacitor C34 is connected to pin 15 of chip D4.

[0019] Pin 16 of chip D4 is connected to one end of resistors R16 and R13 respectively. The other end of resistor R16 is connected to the base of transistor Q1. The emitter of transistor Q1 is grounded. The collector of transistor Q1 is connected to one end of diode LED1. The other end of diode LED1 is connected to the power supply. The other end of resistor R13 is connected to the MCU.

[0020] Pin 22 of chip D4 is connected to one end of resistor R12 and one end of resistor R17 respectively; the other end of resistor R12 is connected to the MCU; the other end of resistor R17 is connected to the base of transistor Q2, and the emitter of transistor Q2 is grounded; one end of diode LED2 is connected to the collector of transistor Q2, and the other end of diode LED2 is connected to the power supply.

[0021] Pin 23 of chip D4 is connected to one end of capacitor C26 and capacitor C33 respectively; the other end of capacitor C26 is connected to the other end of capacitor C33 and pin 24 of chip D4 respectively.

[0022] Pin 27 of chip D4 is connected to one end of resistor R9 and one end of resistor R11; the other end of resistor R9 is grounded, and the other end of resistor R11 is connected to the MCU.

[0023] Pin 25 of chip D4 is connected to one end of capacitor C23 and resistor R6; pin 26 of chip D4 is connected to one end of capacitor C22 and resistor R8; the other end of resistor R8 is connected to the other end of resistor R6 and one end of capacitor C24; the other end of capacitor C24 is grounded.

[0024] The other end of capacitor C23 is connected to one end of connector J10; the other end of capacitor C22 is connected to one end of connector J9.

[0025] Pin 28 of chip D4 is connected to one end of capacitor C21 and resistor R7; pin 29 of chip D4 is connected to one end of capacitor C20 and resistor R5; the other end of resistor R5 is connected to the other end of resistor R7 and one end of capacitor C19; the other end of capacitor C19 is grounded.

[0026] The other end of capacitor C23 is connected to one end of connector J10; the other end of capacitor C22 is connected to one end of connector J9.

[0027] Pins 31 and 32 of chip D4 are connected to the power supply, while pins 30 and 0 of chip D4 are grounded.

[0028] According to the above technical solution, pin 17 of chip D4 is grounded; pins 18 and 19 of chip D4 are both connected to the power supply.

[0029] According to the above technical solution, pin 20 of chip D4 is connected to one end of resistor R15, and the other end of resistor R15 is connected to the MCU; pin 21 of chip D4 is connected to one end of resistor R14, and the other end of resistor R14 is connected to the MCU.

[0030] According to the above technical solution, capacitors C26 and C33, as well as pin 24 of chip D4, are all connected to the power supply.

[0031] According to the above technical solution, resistors R6 and R8, as well as capacitor C24, are all connected to the power supply; resistors R5 and R7, as well as capacitor C19, are all connected to the power supply.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] In this invention, the clock extraction circuit can accurately extract the clock signal from a 25G high-speed data signal. Using a phase comparator, a voltage-controlled oscillator, and a loop filter, it can track the phase changes of the input data signal in real time, generating a stable local clock signal that is correlated with and synchronized with the data signal rate. This effectively solves the problem of clock signals being susceptible to interference and unstable in high-speed data transmission, providing a stable time reference for subsequent accurate data processing and transmission, significantly improving the accuracy and reliability of data transmission, and reducing the bit error rate.

[0034] The high-speed signal input interface can receive data streams at 25Gbps and works seamlessly with the clock extraction circuit. A stable local clock signal ensures precise synchronization between all stages of data reception and processing, guaranteeing data is processed in the correct timing. This not only improves data processing efficiency but also ensures data integrity, enabling the entire system to meet the demands of high-speed data communication and satisfy application scenarios with extremely high requirements for data transmission rates and stability, such as 5G communication and high-speed network transmission. Attached Figure Description

[0035] Figure 1 This is a circuit diagram of the clock extraction circuit of this utility model;

[0036] Figure 2 This is a circuit diagram of the high-speed signal input interface of this utility model. Detailed Implementation

[0037] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0038] Example 1

[0039] A 25G clock data recovery device, specifically relating to a clock data recovery circuit, a clock extraction circuit, and a high-speed signal input interface;

[0040] The clock extraction circuit is used to extract the clock signal from the high-speed data signal; it tracks the phase change of the input data signal through a phase comparator, a voltage-controlled oscillator, and a loop filter, thereby generating a stable local clock signal whose frequency is correlated with and synchronized with the data signal rate.

[0041] The high-speed signal input interface is used to receive data streams at a rate of 25G.

[0042] In this invention, the clock extraction circuit can accurately extract the clock signal from a 25G high-speed data signal. Using a phase comparator, a voltage-controlled oscillator, and a loop filter, it can track the phase changes of the input data signal in real time, generating a stable local clock signal that is correlated with and synchronized with the data signal rate. This effectively solves the problem of clock signals being susceptible to interference and unstable in high-speed data transmission, providing a stable time reference for subsequent accurate data processing and transmission, significantly improving the accuracy and reliability of data transmission, and reducing the bit error rate.

[0043] The high-speed signal input interface can receive data streams at 25Gbps and works seamlessly with the clock extraction circuit. A stable local clock signal ensures precise synchronization between all stages of data reception and processing, guaranteeing data is processed in the correct timing. This not only improves data processing efficiency but also ensures data integrity, enabling the entire system to meet the demands of high-speed data communication and satisfy application scenarios with extremely high requirements for data transmission rates and stability, such as 5G communication and high-speed network transmission.

[0044] Example 2

[0045] This embodiment is a further refinement of Embodiment 1.

[0046] like Figure 2 As shown, the high-speed signal input interface includes connector J2, capacitors C14, C15, C16, C17, C18, C28, C29, C30, inductor L1, and inductor L2.

[0047] Pin 13 of connector J2 is connected to one end of capacitor C15, and the other end of capacitor C15 is connected to the clock extraction circuit; pin 12 of connector J2 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the clock extraction circuit.

[0048] Pins 21 to 31 of connector J2 are all connected to one end of capacitor C28, and the other end of capacitor C28 is grounded.

[0049] Pin 3 of connector J2 is grounded; pin 16 of connector J2 is connected to one end of capacitor C14 and inductor L1, and the other end of capacitor C14 is grounded; the other end of inductor L1 is connected to one end of capacitors C17 and C29 and inductor L2; the other end of inductor L2 is connected to one end of capacitors C18 and C30 and pin 15 of connector J2.

[0050] Pins 10, 11, 14, 17, 20, and pin 1 of connector J2 are all grounded.

[0051] Inductor L2, capacitor C17, and capacitor C19 are all connected to the power supply.

[0052] The other ends of capacitors C17 and C29 are grounded; the other ends of capacitors C18 and C30 are grounded.

[0053] like Figure 1 As shown, the clock extraction circuit includes chip D4, connectors J7, J8, J9, and J10, capacitors C19, C20, C21, C22, C23, C24, C25, C26, C27, C33, and C34, resistors R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, and R19, diodes LED1 and LED2, transistor Q1, and transistor Q2.

[0054] Pins 1 and 2 of chip D4 are both connected to the power supply; pin 3 of chip D4 is connected to one end of capacitor C25, and the other end of capacitor C25 is grounded; pin 4 of chip D4 is connected to capacitor C16, and pin 5 of chip D4 is connected to capacitor C15.

[0055] Pins 6, 7, and 8 of chip D4 are grounded; pin 9 of chip D4 is connected to one end of capacitor C27 and resistor R10, and the other end of capacitor C27 and resistor R10 is grounded; pins 10 and 12 of chip D4 are connected to the power supply; pins 11 and 13 of chip D4 are grounded; pin 14 of chip D4 is connected to one end of capacitor C34, and the other end of capacitor C34 is connected to pin 15 of chip D4.

[0056] Pin 16 of chip D4 is connected to one end of resistors R16 and R13 respectively. The other end of resistor R16 is connected to the base of transistor Q1. The emitter of transistor Q1 is grounded. The collector of transistor Q1 is connected to one end of diode LED1. The other end of diode LED1 is connected to the power supply. The other end of resistor R13 is connected to the MCU.

[0057] Pin 22 of chip D4 is connected to one end of resistor R12 and one end of resistor R17 respectively; the other end of resistor R12 is connected to the MCU; the other end of resistor R17 is connected to the base of transistor Q2, and the emitter of transistor Q2 is grounded; one end of diode LED2 is connected to the collector of transistor Q2, and the other end of diode LED2 is connected to the power supply.

[0058] Pin 23 of chip D4 is connected to one end of capacitor C26 and capacitor C33 respectively; the other end of capacitor C26 is connected to the other end of capacitor C33 and pin 24 of chip D4 respectively.

[0059] Pin 27 of chip D4 is connected to one end of resistor R9 and one end of resistor R11; the other end of resistor R9 is grounded, and the other end of resistor R11 is connected to the MCU.

[0060] Pin 25 of chip D4 is connected to one end of capacitor C23 and resistor R6; pin 26 of chip D4 is connected to one end of capacitor C22 and resistor R8; the other end of resistor R8 is connected to the other end of resistor R6 and one end of capacitor C24; the other end of capacitor C24 is grounded.

[0061] The other end of capacitor C23 is connected to one end of connector J10; the other end of capacitor C22 is connected to one end of connector J9.

[0062] Pin 28 of chip D4 is connected to one end of capacitor C21 and resistor R7; pin 29 of chip D4 is connected to one end of capacitor C20 and resistor R5; the other end of resistor R5 is connected to the other end of resistor R7 and one end of capacitor C19; the other end of capacitor C19 is grounded.

[0063] The other end of capacitor C23 is connected to one end of connector J10; the other end of capacitor C22 is connected to one end of connector J9.

[0064] Pins 31 and 32 of chip D4 are connected to the power supply, while pins 30 and 0 of chip D4 are grounded.

[0065] Pin 17 of chip D4 is grounded; pins 18 and 19 of chip D4 are both connected to the power supply.

[0066] Pin 20 of chip D4 is connected to one end of resistor R15, and the other end of resistor R15 is connected to the MCU; pin 21 of chip D4 is connected to one end of resistor R14, and the other end of resistor R14 is connected to the MCU.

[0067] Furthermore, in this invention, the MCU uses an existing device, such as the C8051 F320 chip.

[0068] Capacitors C26 and C33, as well as pin 24 of chip D4, are all connected to the power supply.

[0069] Resistors R6 and R8, and capacitor C24 are all connected to the power supply; resistors R5 and R7, and capacitor C19 are also connected to the power supply.

[0070] Furthermore, all electronic components involved in this utility model are existing technologies, such as the ADN2812ACP chip used in chip D4.

[0071] The working principle of this invention is as follows: The high-speed signal input interface is responsible for receiving a 25G data stream. Connector J2 receives the external high-speed data signal, the capacitors act as filters and DC blockers, and the inductors have energy storage and filtering functions. For example, capacitors C15 and C16 transmit the signals from pins 13 and 12 of connector J2 to the clock extraction circuit, respectively, while filtering out unnecessary high-frequency noise; capacitor C28 filters the signals from pins 21-31 of connector J2 and then grounds them to stabilize the signal. The circuit composed of inductors L1 and L2 and capacitors C14, C17, C18, C29, and C30 is used for power supply filtering and impedance matching to ensure that the signal is stably transmitted to the clock extraction circuit.

[0072] The clock extraction circuit is the core component, and chip D4 is the main processing element. Chip D4 tracks the phase changes of the input data signal through a phase comparator, a voltage-controlled oscillator, and a loop filter, thereby generating a stable local clock signal.

[0073] Multiple pins of chip D4 are connected to power and ground to ensure normal operation of the chip. For example, pins 1, 2, 10, 12, 18, 19, 31, and 32 are connected to power, while pins 6, 7, 8, 11, 13, 17, 30, and 0 are grounded.

[0074] Pins 4 and 5 of chip D4 are connected to capacitors C16 and C15 respectively to receive high-speed data signals from the high-speed signal input interface.

[0075] The phase comparator inside chip D4 compares the phase difference between the input data signal and the local oscillator signal, and outputs a control signal to the voltage-controlled oscillator (VCO) based on the phase difference to adjust its output frequency. A loop filter filters the control signal, ensuring that the VCO outputs a stable local clock signal whose frequency is correlated with and synchronized with the data signal rate.

[0076] Chip D4 controls diodes LED1 and LED2 to illuminate via resistors and transistors, indicating the chip's operating status. Simultaneously, multiple pins of chip D4 are connected to the MCU via resistors, transmitting the chip's status information to the MCU for monitoring and control.

[0077] The clock signal generated after processing by chip D4 is output through connectors J7, J8, J9, and J10, providing a stable clock source for subsequent circuits. For example, capacitors C23 and C22 transmit the processed signal to connectors J10 and J9, respectively.

[0078] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0079] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A 25G clock data recovery instrument, characterized by: The clock extraction circuit and the high-speed signal input interface are included. The clock extraction circuit is used for extracting the clock signal from the high-speed data signal; the phase variation of the input data signal is tracked through the phase comparator, the voltage-controlled oscillator and the loop filter, so as to generate the stable local clock signal, the frequency of which is associated with and synchronized with the rate of the data signal; The high-speed signal input interface is used for receiving the data stream at the rate of 25G.

2. The 25G clock data recovery instrument of claim 1, wherein: The high-speed signal input interface includes the connector J2, the capacitors C14, C15, C16, C17, C18, C28, C29, C30, the inductors L1 and L2. The pin 13 of the connector J2 is connected with one end of the capacitor C15, and the other end of the capacitor C15 is connected with the clock extraction circuit; the pin 12 of the connector J2 is connected with one end of the capacitor C16, and the other end of the capacitor C16 is connected with the clock extraction circuit. The pins 21 to 31 of the connector J2 are all connected with one end of the capacitor C28, and the other end of the capacitor C28 is grounded. The pin 3 of the connector J2 is grounded; the pin 16 of the connector J2 is connected with the capacitor C14 and one end of the inductor L1 respectively, and the other end of the capacitor C14 is grounded; the other end of the inductor L1 is connected with one end of the capacitor C17, the capacitor C29 and the inductor L2 respectively; the other end of the inductor L2 is connected with one end of the capacitor C18, the capacitor C30 and the pin 15 of the connector J2 respectively. The pins 10, 11, 14, 17, 20 and 1 of the connector J2 are all grounded.

3. The 25G clock data recovery instrument of claim 2, wherein: The inductor L2, the capacitor C17 and the capacitor C19 are all connected with the power supply.

4. The 25G clock data recovery instrument of claim 3, wherein: The other ends of the capacitor C17 and the capacitor C29 are all grounded; the other ends of the capacitor C18 and the capacitor C30 are all grounded.

5. The 25G clock data recovery instrument of claim 4, wherein: The clock extraction circuit includes the chip D4, the joints J7, J8, J9, J10, the capacitors C19, C20, C21, C22, C23, C24, C25, C26, C27, C33, C34, the resistors R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, the diodes LED1 and LED2, the transistors Q1 and Q2. The pins 1 and 2 of the chip D4 are all connected with the power supply; one end of the capacitor C25 is connected with the pin 3 of the chip D4, and the other end of the capacitor C25 is grounded; the pin 4 of the chip D4 is connected with the capacitor C16, and the pin 5 of the chip D4 is connected with the capacitor C15. The pin 6, 7 and 8 of the chip D4 are grounded; the pin 9 of the chip D4 is connected with the capacitor C27 and the one end of the resistor R10 respectively, and the other end of the capacitor C27 and the resistor R10 are grounded; the pin 10 and 12 of the chip D4 are connected with the power supply respectively; the pin 11 and 13 of the chip D4 are grounded; the pin 14 of the chip D4 is connected with the one end of the capacitor C34, and the other end of the capacitor C34 is connected with the pin 15 of the chip D4; The pin 16 of the chip D4 is connected with the resistor R16 and the one end of the resistor R13 respectively, and the other end of the resistor R16 is connected with the base of the triode Q1; the emitter of the triode Q1 is grounded, and the collector of the triode Q1 is connected with the one end of the diode LED1, and the other end of the diode LED1 is connected with the power supply; the other end of the resistor R13 is connected with the MCU; The pin 22 of the chip D4 is connected with the resistor R12 and the one end of the resistor R17 respectively; the other end of the resistor R12 is connected with the MCU; the other end of the resistor R17 is connected with the base of the triode Q2, and the emitter of the triode Q2 is grounded; the collector of the triode Q2 is connected with the one end of the diode LED2, and the other end of the diode LED2 is connected with the power supply; The pin 23 of the chip D4 is connected with the one end of the capacitor C26 and the capacitor C33 respectively; the other end of the capacitor C26 is connected with the other end of the capacitor C33 and the pin 24 of the chip D4 respectively; The pin 27 of the chip D4 is connected with the resistor R9 and the one end of the resistor R11 respectively; the other end of the resistor R9 is grounded, and the other end of the resistor R11 is connected with the MCU; The pin 25 of the chip D4 is connected with the capacitor C23 and the one end of the resistor R6 respectively; the pin 26 of the chip D4 is connected with the capacitor C22 and the one end of the resistor R8 respectively; the other end of the resistor R8 is connected with the other end of the resistor R6 and the one end of the capacitor C24 respectively; the other end of the capacitor C24 is grounded; The pin 28 of the chip D4 is connected with the capacitor C21 and the one end of the resistor R7 respectively; the pin 29 of the chip D4 is connected with the capacitor C20 and the one end of the resistor R5 respectively; the other end of the resistor R5 is connected with the other end of the resistor R7 and the one end of the capacitor C19 respectively; the other end of the capacitor C19 is grounded; The other end of the capacitor C23 is connected with the one end of the joint J10; the other end of the capacitor C22 is connected with the one end of the joint J9; The pin 31 and 32 of the chip D4 are connected with the power supply respectively, and the pin 30 and 0 of the chip D4 are grounded.

6. The 25G clock data recovery instrument of claim 5, wherein: The pin 17 of the chip D4 is grounded; the pin 18 and 19 of the chip D4 are connected with the power supply respectively.

7. The 25G clock data recovery instrument of claim 6, wherein: The pin 20 of the chip D4 is connected with the one end of the resistor R15, and the other end of the resistor R15 is connected with the MCU; the pin 21 of the chip D4 is connected with the one end of the resistor R14, and the other end of the resistor R14 is connected with the MCU.

8. The 25G clock data recovery instrument of claim 7, wherein: The capacitor C26, the capacitor C33 and the pin 24 of the chip D4 are connected with the power supply respectively.

9. The 25G clock data recovery instrument of claim 8, wherein: The resistor R6, the resistor R8 and the capacitor C24 are connected with the power supply respectively; the resistor R5, the resistor R7 and the capacitor C19 are connected with the power supply respectively.

Images