Multi-system multi-channel broadcast television signal monitoring and coding processor

Abstract

The utility model relates to the field of broadcast television signal monitoring, and particularly discloses a multi-system multichannel broadcast television signal monitoring coding processor, which comprises an SOC control circuit, a multipath DTMB signal acquisition circuit, a multipath AM / FM signal acquisition circuit, a multipath stereo audio acquisition circuit, a multipath AS I signal acquisition circuit and a multipath AES / EBU signal acquisition circuit. The SOC control circuit is respectively in communication connection with the multi-path DTMB signal acquisition circuit, the multi-path AM / FM signal acquisition circuit, the multi-path stereo audio acquisition circuit, the multi-path AS I signal acquisition circuit and the multi-path AES / EBU signal acquisition circuit; the device number is reduced, the device size is reduced, the system stability is improved, the field debugging difficulty is reduced, and the problem that multi-channel multi-system signals cannot be demodulated at the same time is solved.

Description

Technical Field

[0001] This utility model relates to the field of broadcast television signal monitoring, and specifically discloses a multi-standard, multi-channel broadcast television signal monitoring encoding processor. Background Technology

[0002] Currently, conventional broadcast television signal monitoring and encoding processors consist of multiple devices, making the entire system bulky. The numerous cables connecting these devices, coupled with often harsh installation environments, significantly increase the difficulty of on-site debugging, leading to low stability. Conventional broadcast television signal monitoring and encoding processors cannot simultaneously demodulate multiple signal standards. They also employ a single power supply design, rendering them inoperable in the event of a power failure. Furthermore, malfunctions in conventional broadcast television signal monitoring and encoding processors require disconnecting all cables and replacing the equipment, resulting in lengthy repair times.

[0003] Therefore, in order to solve the problems of reducing the number of devices, reducing the size of devices, improving system stability, reducing installation difficulty, reducing on-site debugging difficulty, solving the problem of not being able to demodulate multi-channel and multi-standard signals simultaneously, reducing maintenance time, and solving the problem of not being able to work once the power supply fails, this utility model provides a multi-standard and multi-channel broadcast television signal monitoring and encoding processor. Utility Model Content

[0004] This utility model provides a multi-standard, multi-channel broadcast television signal monitoring and encoding processor, including a SOC control circuit, a multi-channel DTMB signal acquisition circuit, a multi-channel AM / FM signal acquisition circuit, a multi-channel stereo audio acquisition circuit, a multi-channel ASI signal acquisition circuit, and a multi-channel AES / EBU signal acquisition circuit; the SOC control circuit is communicatively connected to the multi-channel DTMB signal acquisition circuit, the multi-channel AM / FM signal acquisition circuit, the multi-channel stereo audio acquisition circuit, the multi-channel ASI signal acquisition circuit, and the multi-channel AES / EBU signal acquisition circuit.

[0005] Furthermore, the SOC control circuit includes an SOC control chip, a DDR3 circuit, an LED circuit, a crystal oscillator circuit, an interface circuit, a WIFI module, a Bluetooth module, an RTC circuit, an EEPROM circuit, a power acquisition circuit, a PHY circuit, a USB PHY circuit, an eMMC circuit, and a FLASH circuit; the SOC control chip is communicatively connected to the DDR3 circuit, the LED circuit, the crystal oscillator circuit, the interface circuit, the WIFI module, the Bluetooth module, the RTC circuit, the EEPROM circuit, the power acquisition circuit, the PHY circuit, the USB PHY circuit, the eMMC circuit, and the FLASH circuit.

[0006] Furthermore, the SOC control chip is selected as XILINX ZYNQ-7000XC7Z020; the oscillation frequency of the crystal oscillator circuit is selected as 33.33MHz.

[0007] Furthermore, the multi-channel stereo audio acquisition circuit adopts a PCM1804 circuit, including a PCM1804 chip; the left channel input pin V of the PCM1804 chip... INL+ and V INL- Connect the left channel input signal L-Channel In; the right channel input pin V INR+ and V INR- The right channel input signal R-Channel In is connected; the V of the PCM1804 chip REFL and V REFR Signal processing is performed through grounding capacitors C1 and C2 respectively, and AGNDL and AGNDR are grounded; V COML and V COMR Signal processing is performed through grounding capacitors C3 and C4 respectively; control pins FMT0 and FMT1 are connected to format control signals; Access master / slave mode control signals; OSR0, OSR1, and OSR2 access oversampling rate control signals; the BY PASS pin accesses the high-pass filter bypass control signal; the power supply pin V... CC and V DD Connect the power supply separately, and V CC Through grounding capacitor C6, V DD Filtering is performed using grounding capacitor C5, and pins DGND and AGND are grounded; reset pin The system clock is connected to the reset signal, and the system clock pin SCKI is connected to the system clock signal; the LRCK / DSDBCK pins output the data clock signal; the BCK / DSDL pins output the left channel data; the DATA / DDSDR pins output the right channel data; all output signals are connected to the audio data processor; the OVFL and OVFR pins of the PCM1804 chip output overflow signals.

[0008] Furthermore, the multi-channel ASI signal acquisition circuit includes a transmitting unit, a receiving unit, and a signal transmission and processing unit; the transmitting unit uses a CY7B923 chip, and the MODE pin of the CY7B923 chip receives the configuration signal; the FOTO pin... and RP receive configuration control signals; pin Pins D0, D1, D2, D3, D4, D5, D6, D7, and SVS receive data signals; pin CKW receives clock signals; pins OUTA+ and OUTA- are connected to the TX+ and TX- pins of the fiber optic transmitter module after being matched by a transmitting end positive emitter coupled logic load circuit composed of 82Ω and 130Ω resistors; pins OUTC+ and OUTC- are connected to the transmission medium via a 270Ω grounding resistor; connection points A and B are respectively set at pins OUTA+ and OUTA-; the receiving unit uses a CY7B933 chip, and the MODE and REFCLK pins of the CY7B933 chip receive configuration signals; pins... SO、 RF and Receive configuration control signals; pins Pins D0, D1, D2, D3, D4, D5, D6, D7, and RVS output data signals; pin CKR receives clock signals; pin IB+ is connected to the CY7B923 chip; pins IB-, IA+, and IA- receive signals from pins SIG, RX+, and RX- of the fiber optic receiver after passing through a matching circuit containing capacitors of 270Ω, 82Ω, 130Ω, and 0.01μF, respectively; connection points E, C, and D are respectively set at pins B-, IA+, and IA-; the signal transmission processing unit is connected to the first coil circuit through connection point A, and connected to the first coil circuit through connection point B via a 270Ω grounding resistor; a 0.01μF grounding capacitor and a 649Ω resistor are connected in parallel to a 1500Ω grounding resistor; the 1500Ω grounding resistor is also connected to connection points C and D through an RL / 2 resistor; the other end of the RL / 2 resistor is connected to the second coil circuit; the second coil circuit is connected to connection point E via a signal detection circuit.

[0009] Furthermore, the AM / FM signal acquisition circuit adopts the SI4735 circuit, which includes a Si473x D60 chip; the signal DOUT is connected to the DOUT pin of the Si473x chip through resistor R1; the signal DFS is connected to the DFS pin of the Si473x chip through resistor R2; the signals GPO3 / DCLK are connected to the GPO3 / DCLK pin of the Si473x chip; the signal GPO2 / INT is connected to the GPO2 / INT pin of the Si473x chip; the signal GPO1 is connected to the GPO1 pin of the Si473x chip; the FM antenna signal is connected to the FMI pin of the Si473x chip through capacitor C8; the AM antenna is connected to the AMI pin of the Si473x chip through inductor and capacitor; the RFGND, NC and GND pins of the Si473x chip are connected to... Ground; signal RSTB is connected to pin RSTB of chip Si473x; signal SENB is connected to pin SENB of chip Si473x; signal SCLK is connected to pin SCLK of chip Si473x; signal SDIO is connected to pin SDIO of chip Si473x; signal RCLK is connected to pin RCLK of chip Si473x; signal VD is connected to pin VD of chip Si473x through ground capacitor C11; signal VA is connected to pin VA of chip Si473x, and connected to pin DBYP of chip Si473x through capacitor C7; signal ROUT is connected to pin ROUT of chip Si473x; signal LOUT is connected to pin LOUT of chip Si473x.

[0010] Furthermore, the AM antenna is connected to the AMI pin of the Si473x chip via inductor L2, transformer T1 and capacitor C12, and the other end of transformer T1 is connected to the RFGND pin of the Si473x chip.

[0011] Furthermore, the signal GPO3 / DCLK is connected to the crystal oscillator X1, and an oscillation circuit is constructed through grounding capacitors C13 and C14. The output of the oscillation circuit serves as the signal RCLK.

[0012] Furthermore, the multi-channel DTMB signal acquisition circuit adopts the ATBM8880 circuit, including the ATBM8881 / 8880 chip; the SDAM pin of the ATBM8881 / 8880 chip is connected to the signal SDA_T; the SCLM pin is connected to the signal SCL_T; the TEST0, TEST1, ADDR and GND pins are grounded; the STATUS pin is connected to the signal STATUS; the TSSYNC pin is connected to the signal TSSYNC; the TSVLD pin is connected to the signal TSVLD; the TSCLK pin is connected to the signal TSCLK; the TS0 pin is connected to the signal TS7; the TS1 pin is connected to the signal TS6; the TS2 pin is connected to the signal TS5; the TS3 pin is connected to the signal TS4; the TS4 pin is connected to the signal TS3; the TS5 pin is connected to the signal TS2; the TS6 pin is connected to the signal TS1; the TS7 pin is connected to the signal TS0; the 3V3 power supply is connected to the VDD33 pin of the ATBM8881 / 8880 chip; the 1V1 power supply is connected to the CVDD pin of the ATBM8881 / 8880 chip; the signal... Connect the RESET pin of the ATBM8881 / 8880 chip; connect the SCLS and SDAS pins of the ATBM8881 / 8880 chip to signals SCL and SDA respectively, and connect the SCL and SDA signals to resistors R6 and R5 respectively to the 3V3 power supply; connect the XTAL1 pin to signal XTAL1; connect the XTAL0 pin to signal XTAL0; connect the 3V3 power supply to the AVDD33 pin of the ATBM8881 / 8880 chip through inductor L3 and parallel grounding capacitors C15 and C16; connect the IFBP pin to signal IFBP through capacitor C17; connect the IFBN pin to signal IFBN through capacitor C18; connect the IFAP pin to signal IFAP through capacitor C19; connect the IFAN pin to signal IFAN through capacitor C20; connect the PWM0 / GPO3 pin to signal PWM0.

[0013] Furthermore, the 3V3 power supply is connected to the signal via resistor R4. Grounding capacitor C21 is connected in parallel with the signal Between and the earth.

[0014] This utility model addresses the problems existing in the prior art by providing a multi-standard, multi-channel broadcast television signal monitoring and encoding processor. It solves the problems of reducing the number of devices, reducing the size of devices, improving system stability, reducing installation difficulty, reducing on-site debugging difficulty, solving the problem of not being able to demodulate multi-channel, multi-standard signals simultaneously, reducing maintenance time, and solving the problem of not being able to work in the event of a power failure. Attached Figure Description

[0015] Figure 1 This is an exemplary structural diagram of a multi-standard, multi-channel broadcast television signal monitoring and encoding processor according to the present invention;

[0016] Figure 2 This is an exemplary schematic diagram of the SOC control circuit in this utility model;

[0017] Figure 3 This is a circuit diagram of the PCM1804 circuit in this utility model;

[0018] Figure 4 This is a circuit diagram of the multi-channel ASI signal acquisition circuit in this utility model;

[0019] Figure 5a This is the circuit diagram of the SI4735 circuit in this utility model;

[0020] Figure 5b This is a circuit diagram of the AM antenna of the SI4735 circuit in this utility model;

[0021] Figure 5c This is a circuit diagram of the clock circuit of the SI4735 circuit in this utility model;

[0022] Figure 6 This is a circuit diagram of the ATBM8880 circuit in this utility model. Detailed Implementation

[0023] The present invention will be further described below with reference to the specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 This is an exemplary structural diagram of a multi-standard, multi-channel broadcast television signal monitoring and encoding processor according to the present invention. Figure 1 As shown, a multi-standard, multi-channel broadcast television signal monitoring and encoding processor includes a SOC control circuit, a multi-channel DTMB signal acquisition circuit, a multi-channel AM / FM signal acquisition circuit, a multi-channel stereo audio acquisition circuit, a multi-channel ASI signal acquisition circuit, and a multi-channel AES / EBU signal acquisition circuit. The SOC control circuit is communicatively connected to the multi-channel DTMB signal acquisition circuit, the multi-channel AM / FM signal acquisition circuit, the multi-channel stereo audio acquisition circuit, the multi-channel ASI signal acquisition circuit, and the multi-channel AES / EBU signal acquisition circuit.

[0025] Figure 2 This is an exemplary schematic diagram of the SOC control circuit in this utility model. (For example...) Figure 2As shown, the SOC control circuit includes an SOC control chip, a DDR3 circuit, an LED circuit, a crystal oscillator circuit, an interface circuit, a WIFI module, a Bluetooth module, an RTC circuit, an EEPROM circuit, a power acquisition circuit, a PHY circuit, a USB PHY circuit, an eMMC circuit, and a FLASH circuit. The SOC control chip is communicatively connected to the DDR3 circuit, the LED circuit, the crystal oscillator circuit, the interface circuit, the WIFI module, the Bluetooth module, the RTC circuit, the EEPROM circuit, the power acquisition circuit, the PHY circuit, the USB PHY circuit, the eMMC circuit, and the FLASH circuit.

[0026] The SOC control circuit uses the Zynq 7020 series, such as the XILINX ZYNQ-7000XC7Z020, with the core board CPU model XC7Z020-2CLG400I, in a CLG400 package. Its operating temperature range is -40℃ to 100℃, it has 400 pins, and its dimensions are 17mm*17mm. The crystal oscillator circuit uses a frequency of 33.33MHz. The SOC control circuit connects to the industrial-grade SPI NOR FLASH via the QSPI0 (CS0) bus on the PS side; it also connects to the industrial-grade eMMC via the SDIO1 bus on the PS side, using 4-bit data lines; and it connects to two industrial-grade DDR3 chips via the DDR bus on the PS side, each using 16-bit data lines, for a total of 32 bits. The SOC control circuit uses two industrial-grade crystal oscillators with clock frequencies of 33.33MHz and 24MHz. The PS side of the SOC control circuit has an 8-bit parallel data interface, USB0. The ULPI is converted into a high-speed USB transceiver bus via a PHY chip; the SOC control circuit monitors power (voltage and current) via an I2C bus, using an 1NA220AIDGS for power consumption monitoring; the SOC control circuit connects an EEPROM via an I2C bus to store board information (factory information, board hardware parameters, etc.), using an AT24C02 chip; the SOC control circuit is equipped with a 32.768kHz passive clock and a coin cell battery to provide clock information to the Zynq system, using a DA1340Z chip; the SOC control circuit connects via an I2C bus... The C-interface monitors the board temperature using the TMP102AIDRLT. The SOC control circuit communicates with the WIFI module via the USB interface, employing a parallel BL-R8188EU2 design; this module is stable, mature, and has low power consumption. The SOC control circuit also communicates with the Bluetooth module via the serial interface, using the WH-BLE105 module. The WH-BLE105 is a BLE 5.2 module, suitable for transparent and encrypted data transmission in master-slave or multi-master / multi-slave configurations. Users do not need to worry about the transmission protocol; simple settings are sufficient for communication, utilizing AT commands. The DDR3 circuit, LED circuit, crystal oscillator circuit, interface circuit, WIFI module, Bluetooth module, RTC circuit, EEPROM circuit, power acquisition circuit, PHY circuit, USB PHY circuit, eMMC circuit, and FLASH circuit connected to the SOC control chip utilize existing mature circuit structures.

[0027] Figure 3This is a circuit diagram of the PCM1804 circuit in this utility model. The PCM1804 stereo analog-to-digital converter is a high-performance, single-chip stereo analog-to-digital converter with fully differential analog voltage input. The PCM1804 employs a precision Δ-Σ modulator and includes a linear phase anti-aliasing digital filter and a high-pass filter (HPF) to remove DC bias from the input signal. The PCM1804 is widely used in mid-to-high-end consumer and professional applications requiring excellent performance and operating on both 5V analog and 3.3V digital power supplies. Thanks to the precision Δ-Σ modulator, the PCM1804 can simultaneously implement PCM audio and DSD formats. The PCM1804 is manufactured using advanced CMOS technology and is packaged in a small 28-pin SSOP package.

[0028] like Figure 3 As shown, the multi-channel stereo audio acquisition circuit uses a PCM1804 circuit, including a PCM1804 chip; the left channel input pin V of the PCM1804 chip... INL+ and V INL- Connect the left channel input signal L-Channel In; the right channel input pin V INR+ and V INR- The right channel input signal R-Channel In is connected; the V of the PCM1804 chip REFL and V REF R is used for signal processing through grounding capacitors C1 and C2 respectively, and AGNDL and AGNDR are grounded; V COM L and V COM R is processed through grounding capacitors C3 and C4 respectively; control pins FMT0 and FMT1 are connected to the format control signal Format[1:0]; Access the Master / Slave mode control signal; OSR0, OSR1, and OSR2 are connected to the OversamplingRatio[2:0] oversampling rate control signal; the BY PASS pin is connected to the HPF Bypass high-pass filter bypass control signal; the power supply pin V CC and V DD Connect the power supply separately, and V CC Through grounding capacitor C6, V DD Filtering is performed using grounding capacitor C5, and pins DGND and AGND are grounded; reset pin The system clock is connected to the Reset signal, the SCKI pin is connected to the System Clock signal, the LRCK / DSDBCK pin outputs the Data Clock signal, the BCK / DSDL pin outputs the left channel data (L-Channel Data Out), the DATA / DDSDR pin outputs the right channel data (R-Channel Data Out), all output signals are connected to the Audio Data Processor, and the OVFL and OVFR pins of the PCM1804 chip output the Overflow signal.

[0029] Figure 4 This is a circuit diagram of the multi-channel ASI signal acquisition circuit in this utility model. The CY78933 is a receiver chip launched by Cypress Semiconductor for high-speed serial data communication between points. The matching transmitter chip is the CY7B923. The internal circuit of the CY7B933 receiver chip mainly includes two pairs of PECL serial input interfaces, a PECL-TTL level converter, a clock synchronizer, a framer, a shifter, a decoder register, a decoder, an output register, and test logic. When used with the CY7B923, the CY7B933 also offers three transmission speed options: The standard series includes four models: CY7B933-JC, CY7B933-JI, CY7B933-SC, and CY7B933-MB, with transmission speeds ranging from 160 to 330 Mbps; the high-speed series includes CY7B933-400JC and CY7B933-400J, with transmission rates of 160 to 400 Mbps; and the low-speed series includes CY7B933-155JC and CY7B933-155J, with transmission rates of 150 to 160 Mbps. The CY7B933 is available in 28-pin SOIC, PLCC, and LCC packages, manufactured using 0.8MBiCMOS technology and powered by a single +5V supply, with a power consumption of 650mW.

[0030] like Figure 4 As shown, the multi-channel ASI signal acquisition circuit includes a transmitting unit, a receiving unit, and a signal transmission and processing unit.

[0031] The transmitting unit uses the CY7B923 chip. The CY7B923 chip's MODE pin receives the configuration signal Config; the FOTO pin... RP receives configuration control signals Control and Status; pin Pins D0, D1, D2, D3, D4, D5, D6, D7, and SVS receive the data signal Data; pin CKW receives the clock signal; pins OUTA+ and OUTA- are connected to the TX+ and TX- pins of the fiber optic transmitter module after being matched by a transmitting end positive emitter coupled logic load circuit consisting of an 82Ω and a 130Ω resistor; pins OUTC+ and OUTC- are connected to the transmission medium via a 270Ω grounding resistor; connection points A and B are set at pins OUTA+ and OUTA-, respectively.

[0032] The receiving unit uses the CY7B933 chip. The CY7B933 chip's MODE and REFCLK pins receive configuration signals; pin... SO、 RF and Receive configuration control signals; pins Pins D0, D1, D2, D3, D4, D5, D6, D7, and RVS output data signals; pin CKR receives clock signals; pin IB+ is connected to the CY7B923 chip; pins IB-, IA+, and IA- receive signals from pins SIG, RX+, and RX- of the fiber optic receiver after passing through a matching circuit containing capacitors of 270Ω, 82Ω, 130Ω, and 0.01μF, respectively; connection points E, C, and D are set at pins IB-, IA+, and IA-, respectively.

[0033] The signal transmission processing unit is connected to the first coil circuit through connection point A, and to the first coil circuit through connection point B via a 270Ω grounding resistor; a 0.01μF grounding capacitor and a 649Ω resistor are connected in parallel and then connected to a 1500Ω grounding resistor; the 1500Ω grounding resistor is also connected to connection points C and D through an RL / 2 resistor; the other end of the RL / 2 resistor is connected to the second coil circuit; the second coil circuit is connected to connection point E via a signal detection circuit.

[0034] Figure 5a This is a circuit diagram of the SI4735 circuit in this utility model. The SI4735 is a highly integrated radio frequency (RF) radio chip that supports FM, AM, and shortwave broadcasting. Its features include automatic frequency control (AFC), digital signal processing (DSP), and a high-precision clock source, ensuring excellent reception quality and stability.

[0035] like Figure 5aAs shown, the AM / FM signal acquisition circuit uses an SI4735 circuit, which includes a Si473xD60 chip. Signal DOUT is connected to the DOUT pin of the Si473x chip via resistor R1; signal DFS is connected to the DFS pin of the Si473x chip via resistor R2; signals GPO3 / DCLK are connected to the GPO3 / DCLK pin of the Si473x chip; signal GPO2 / INT is connected to the GPO2 / INT pin of the Si473x chip; signal GPO1 is connected to the GPO1 pin of the Si473x chip; the FM antenna signal is connected to the FMI pin of the Si473x chip via capacitor C8; the AM antenna is connected to the AMI pin of the Si473x chip via an inductor and capacitor; the RFGND, NC, and GND pins of the Si473x chip are grounded; The following signals are connected: RSTB to pin RSTB of chip Si473x; SENB to pin SENB of chip Si473x; SCLK to pin SCLK of chip Si473x; SDIO to pin SDIO of chip Si473x; RCLK to pin RCLK of chip Si473x; VD connected to pin VD of chip Si473x via grounding capacitor C11; VA connected to pin VA of chip Si473x, and connected to pin DBYP of chip Si473x via capacitor C7; ROUT connected to pin ROUT of chip Si473x; LOUT connected to pin LOUT of chip Si473x.

[0036] Figure 5b This is the circuit diagram of the AM antenna of the SI4735 circuit in this utility model. Figure 5b As shown, the AM antenna is connected to the AMI pin of the Si473x chip via inductor L2, transformer T1 and capacitor C12. The other end of the transformer T1 is connected to the RFGND pin of the Si473x chip.

[0037] Figure 5c This is a circuit diagram of the clock circuit for the SI4735 circuit in this utility model. Figure 5c As shown, the signal GPO3 / DCLK is connected to the crystal oscillator X1, and an oscillation circuit is constructed through grounding capacitors C13 and C14. The output of the oscillation circuit is the signal RCLK.

[0038] Figure 6This is a circuit diagram of the ATBM8880 circuit in this utility model. The ATBM8880 is a demodulator chip that supports the DTMB digital television standard and is pin-compatible with the DVB series demodulator chips from Hightop Semiconductor. It is widely compatible with traditional tuners and silicon tuners with 4-11MHz low-IF and 36-44MHz IF outputs. It supports 100kHz and 400kHz I2C bus communication; it has a flexible SPI / SSI TS output format; it is packaged in a 7x7mm² QFN48 package; and it requires 3.3V and 1.1-1.2V power supplies. It fully complies with GB20600-2006 and is optimized for all modes defined in the standard; it also fully complies with the performance requirements of GB / T 26683-2017 and GB / T26686-2017.

[0039] like Figure 6 As shown, the multi-channel DTMB signal acquisition circuit uses the ATBM8880 circuit, including the ATBM8881 / 8880 chip; the SDAM pin of the ATBM8881 / 8880 chip is connected to the signal SDA_T; the SCLM pin is connected to the signal SCL_T; the TEST0, TEST1, ADDR and GND pins are grounded; the STATUS pin is connected to the signal STATUS; the TSSYNC pin is connected to the signal TSSYNC; the TSVLD pin is connected to the signal TSVLD; the TSCLK pin is connected to the signal TSCLK; the TS0 pin is connected to the signal TS7; the TS1 pin is connected to the signal TS6; the TS2 pin is connected to the signal TS5; the TS3 pin is connected to the signal TS4; the TS4 pin is connected to the signal TS3; the TS5 pin is connected to the signal TS2; the TS6 pin is connected to the signal TS1; the TS7 pin is connected to the signal TS0; a 3V3 power supply is connected to the VDD33 pin of the ATBM8881 / 8880 chip; a 1V1 power supply is connected to the CVDD pin of the ATBM8881 / 8880 chip; the signal... Connect the RESET pin of the ATBM8881 / 8880 chip; connect the SCLS and SDAS pins of the ATBM8881 / 8880 chip to signals SCL and SDA respectively, with SCL and SDA connected to resistors R6 and R5 respectively to the 3V3 power supply; connect the XTAL1 pin to signal XTAL1; connect the XTAL0 pin to signal XTAL0; connect the 3V3 power supply to the AVDD33 pin of the ATBM8881 / 8880 chip through inductor L3 and parallel grounding capacitors C15 and C16; connect the IFBP pin to signal IFBP through capacitor C17; connect the IFBN pin to signal IFBN through capacitor C18; connect the IFAP pin to signal IFAP through capacitor C19; connect the IFAN pin to signal IFAN through capacitor C20; connect the PWM0 / GPO3 pin to signal PWM0. The 3V3 power supply is connected to the signals through resistor R4. Grounding capacitor C21 is connected in parallel with the signal Between and the earth.

[0040] The beneficial effects that this utility model can achieve are:

[0041] Higher level of integration: The encoding processor provided by this utility model integrates a SOC control circuit, enabling the reception and processing of multiple DTMB signals, and allowing for parameter analysis of the signals; the reception and processing of multiple ASI signals, and allowing for parameter analysis of the signals; the reception and processing of multiple AM / FM signals, and allowing for parameter analysis of the signals; the reception and processing of multiple analog stereo audio signals, and allowing for parameter analysis of the signals; the reception and processing of multiple AES / EBU signals, and allowing for parameter analysis of the signals. This reduces equipment size, improves system stability, lowers installation difficulty, reduces on-site debugging difficulty, and solves the problem of not being able to simultaneously demodulate multiple channels and multiple standard signals.

[0042] Standard board design: The equipment is designed using standard boards, with one standard board for each standard. The number of channels can be flexibly added, and installation and replacement are convenient.

[0043] Dual power supply design: The equipment adopts a dual power supply design with redundancy to ensure that the equipment can continue to work even if one power supply fails.

Claims

1. A multi-standard multi-channel broadcast television signal monitoring and encoding processor, characterized by, The SOC control circuit, the multi-path DTMB signal acquisition circuit, the multi-path AM / FM signal acquisition circuit, the multi-path stereo audio acquisition circuit, the multi-path ASI signal acquisition circuit and the multi-path AES / EBU signal acquisition circuit are included. The SOC control circuit is in communication connection with the multi-path DTMB signal acquisition circuit, the multi-path AM / FM signal acquisition circuit, the multi-path stereo audio acquisition circuit, the multi-path ASI signal acquisition circuit and the multi-path AES / EBU signal acquisition circuit respectively.

2. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 1, wherein, The SOC control circuit includes a SOC control chip, a DDR3 circuit, an LED circuit, a crystal oscillator circuit, an interface circuit, a WIFI module, a Bluetooth module, an RTC circuit, an EEPROM circuit, a power acquisition circuit, a PHY circuit, a USB PHY circuit, an eMMC circuit and a FLASH circuit. The SOC control chip is in communication connection with the DDR3 circuit, the LED circuit, the crystal oscillator circuit, the interface circuit, the WIFI module, the Bluetooth module, the RTC circuit, the EEPROM circuit, the power acquisition circuit, the PHY circuit, the USB PHY circuit, the eMMC circuit and the FLASH circuit.

3. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 2, wherein, The SOC control chip selects XILINX ZYNQ-7000XC7Z020; and the oscillation frequency of the crystal oscillator circuit is 33.33MHz.

4. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 1, wherein, The multi-channel stereo audio acquisition circuit adopts PCM1804 circuit, including PCM1804 chip; the left channel input pin V INL+ and V INL- of the PCM1804 chip accesses left channel input signal L-Channel In; the right channel input pin V INR+ and V INR- of the PCM1804 chip accesses right channel input signal R-Channel In; V REF L and V REF R of the PCM1804 chip respectively pass through signal processing of grounding capacitors C1 and C2, AGNDL and AGNDR are grounded; V COM L and V COM R respectively pass through signal processing of grounding capacitors C3 and C4; Control pins FMT0 and FMT1 access format control signals; Access master-slave mode control signals; OSR0, OSR1 and OSR2 access oversampling rate control signals; pin BYPASS accesses high-pass filter bypass control signal; power supply pin V CC and V DD Connect power supply respectively, and V CC Through ground capacitor C6, V DD Through ground capacitor C5 for filtering, pin DGND and AGND are grounded; reset pin Access reset signal, system clock pin SCKI accesses system clock signal; pin LRCK / DSDBCK outputs data clock signal; pin BCK / DSDL outputs left channel data; pin DATA / DDSDR outputs right channel data; output signals are connected to audio data processor; OVFL and OVFR of PCM1804 chip output overflow signals.

5. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 1, wherein, The multi-path ASI signal acquisition circuit includes a transmitting unit, a receiving unit and a signal transmission processing unit. The transmitting unit adopts CY7B923 chip, pin MODE of CY7B923 chip receives configuration signal; pin FOTO, and RP receives configuration control signal; pin D0, D1, D2, D3, D4, D5, D6, D7 and SVS receive data signal; pin CKW receives clock signal; pin OUTA+ and OUTA- are connected to TX+ and TX- pins of the optical fiber transmitting module after being matched with a transmitting end positive emitter coupled logic load circuit formed by 82Ω and 130Ω resistors; pin OUTC+ and OUTC- are connected to transmission medium via 270Ω grounding resistor; connection points A and B are respectively arranged at pin OUTA+ and pin OUTA-. The receiving unit adopts CY7B933 chip, the pin MODE and REFCLK of CY7B933 chip receive configuration signal; the pin SO, RF and receive configuration control signal; the pin D0, D1, D2, D3, D4, D5, D6, D7 and RVS output data signal; the pin CKR receives clock signal; the pin IB+ is connected with the CY7B923 chip; the pins IB-, IA+ and IA- receive the signal from the pins SIG, RX+ and RX- of fiber receiver through the matching circuit containing 270Ω, 82Ω, 130Ω and 0.01μF capacitor; the connection points E, C and D are respectively set at the pins B-, IA+ and IA-. The signal transmission processing unit is connected with a first coil circuit through a connection point A and connected to the first coil circuit through a connection point B via a 270Ω grounding resistor. A 0.01μF grounding capacitor is connected with a 649Ω resistor in parallel and then connected with a 1500Ω grounding resistor; the 1500Ω grounding resistor is also connected with connection points C and D via an RL / 2 resistor; the other end of the RL / 2 resistor is connected with a second coil circuit; the second coil circuit is connected to a connection point E via a signal detection circuit.

6. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 1, wherein, The AM / FM signal acquisition circuit adopts a SI4735 circuit, and the SI4735 circuit includes a Si473xD60 chip. The signal DOUT is connected to the pin DOUT of the chip Si473x through the resistor R1; the signal DFS is connected to the pin DFS of the chip Si473x through the resistor R2; the signal GPO3 / DCLK is connected to the pin GPO3 / DCLK of the chip Si473x; the signal GPO2 / INT is connected to the pin GPO2 / INT of the chip Si473x; the signal GPO1 is connected to the pin GPO1 of the chip Si473x; the FM antenna signal is connected to the pin FMI of the chip Si473x through the capacitor C8; the AM antenna is connected to the pin AMI of the chip Si473x through the inductor and the capacitor; the pins RFGND, NC and GND of the chip Si473x are grounded; the signal RSTB is connected to the pin RSTB of the chip Si473x; the signal SENB is connected to the pin SENB of the chip Si473x; the signal SCLK is connected to the pin SCLK of the chip Si473x; the signal SDIO is connected to the pin SDIO of the chip Si473x; the signal RCLK is connected to the pin RCLK of the chip Si473x; the signal VD is connected to the pin VD of the chip Si473x through the grounding capacitor C11; the signal VA is connected to the pin VA of the chip Si473x and connected to the pin DBYP of the chip Si473x through the capacitor C7; the signal ROUT is connected to the pin ROUT of the chip Si473x; the signal LOUT is connected to the pin LOUT of the chip Si473x.

7. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 6, wherein, The AM antenna is connected to the pin AMI of the chip Si473x through the inductor L2, the transformer T1 and the capacitor C12, the other end of the transformer T1 is connected to the pin RFGND of the chip Si473x.

8. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 6, wherein, The signal GPO3 / DCLK is connected to the crystal oscillator X1, the oscillation loop is built through the grounding capacitors C13 and C14, and the output of the oscillation loop is the signal RCLK.

9. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 1, wherein, The multi-path DTMB signal acquisition circuit adopts ATBM8880 circuit, including ATBM8881 / 8880 chip; the pin SDAM of the ATBM8881 / 8880 chip is connected with the signal SDA_T; the pin SCLM is connected with the signal SCL_T; the pins TEST0, TEST1, ADDR and GND are grounded; the pin STATUS is connected with the signal STATUS; the pin TSSYNC is connected with the signal TSSYNC; the pin TSVLD is connected with the signal TSVLD; the pin TSCLK is connected with the signal TSCLK; the pin TS0 is connected with the signal TS7; the pin TS1 is connected with the signal TS6; the pin TS2 is connected with the signal TS5; the pin TS3 is connected with the signal TS4; the pin TS4 is connected with the signal TS3; the pin TS5 is connected with the signal TS2; the pin TS6 is connected with the signal TS1; the pin TS7 is connected with the signal TS0; the 3V3 power supply is connected with the pin VDD33 of the ATBM8881 / 8880 chip; the 1V1 power supply is connected with the pin CVDD of the ATBM8881 / 8880 chip; the signal the pin RESET of the ATBM8881 / 8880 chip; the pins SCLS and SDAS of the ATBM8881 / 8880 chip are connected with the signals SCL and SDA respectively, the signals SCL and SDA are connected with resistors R6 and R5 to the 3V3 power supply; the pin XTAL1 is connected with the signal XTAL1; the pin XTAL0 is connected with the signal XTAL0; the 3V3 power supply is connected with the pin AVDD33 of the ATBM8881 / 8880 chip through the inductor L3, the parallel ground capacitors C15 and C16; the pin IFBP is connected with the signal IFBP through the capacitor C17; the pin IFBN is connected with the signal IFBN through the capacitor C18; the pin IFAP is connected with the signal IFAP through the capacitor C19; the pin IFAN is connected with the signal IFAN through the capacitor C20; the pin PWM0 / GPO3 is connected with the signal PWM0.

10. The multi-standard multi-channel broadcast television signal monitoring and encoding processor of claim 9, wherein, 3V3 power supply is connected to the signal through resistor R4 Grounding capacitor C21 is connected in parallel to the signal Between ground.

Images