MOSFET device
By designing asymmetrically distributed lightly doped regions at the source and drain ends in MOSFET devices, the hot carrier injection effect is improved, the problem of device performance degradation is solved, and the device performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2026-04-03
AI Technical Summary
Existing MOSFET devices suffer from severe hot carrier injection effects under high field strength, leading to device parameter drift and degradation. Furthermore, increasing the overlap width between the lightly doped drain region and the gate worsens the short-channel effect, affecting device performance.
The source and drain lightly doped regions are designed to be asymmetrically distributed with respect to the gate. The extension width of the lightly doped region at the source is smaller than that at the drain, and the overlap width ratio is 1:1.5 to 1:2. This is achieved through a self-aligned process, which simplifies the process and reduces costs.
It effectively suppresses the hot carrier injection effect, improves device performance, avoids increased leakage current, and ensures that device performance is not affected.
Smart Images
Figure CN224083955U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, and in particular to a MOSFET device. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamental devices for building integrated circuits. Under high electric fields, carriers are continuously accelerated. When the energy exceeds the Si-SiO2 barrier height between the substrate (Si) and the gate oxide layer (SiO2) (electrons ~3.2 eV, holes ~4.5 eV), the interface Si-H bonds are broken or the carriers are injected into the gate oxide layer, generating interface states or becoming trapped charges. This causes the device's threshold voltage (Vth), transconductance (gm), and other parameters to drift and degrade, ultimately leading to device failure. Due to the difference in Si-SiO2 barrier height, and the fact that the effective mass of holes is greater than that of electrons, the hot carrier injection (HCI) effect is more severe in NMOS devices.
[0003] Please continue to refer to this. Figure 1 The industry generally adopts a lightly doped drain (LDD) structure, which introduces a drain-side lightly doped region LDD_D between one end of the channel and the drain region, and a source-side lightly doped region LDD_S between the other end of the channel and the source region. The drain-side lightly doped region LDD_D and the source-side lightly doped region LDD_S are symmetrically distributed on both sides of the gate, which reduces the concentration gradient at the junction of the channel and the source and drain regions, and significantly reduces the electric field strength at the junction of the channel and the source and drain regions. This can suppress the lateral migration of hot carriers to a certain extent, and thus suppress the damage of the gate oxide layer caused by the hot carrier effect to a certain extent. Furthermore, the existing drain-side lightly doped region LDD_D and source-side lightly doped region LDD_S are formed in the active regions AA on both sides of the gate through a self-aligned process after the gate is formed. The overlap between the drain-side lightly doped region LDD_D and the source-side lightly doped region LDD_S and the gate is symmetrical, that is, the overlap width between the drain-side lightly doped region LDD_D and the source-side lightly doped region LDD_S and the gate is W1.
[0004] To further improve the HCI effect, existing technologies simultaneously increase the overlap width between the lightly doped drain region LDD_D and the lightly doped source region LDD_S and the gate. When this overlap width increases to a certain extent, it will worsen the short-channel effect, leading to increased leakage current and thus affecting device performance. Utility Model Content
[0005] The purpose of this invention is to provide a MOSFET device that can improve the hot carrier injection effect of the device without affecting leakage current, thereby improving device performance.
[0006] To achieve the above objectives, this utility model provides a MOSFET device, comprising:
[0007] Substrate,
[0008] A gate is formed on the substrate;
[0009] The lightly doped source region and the lightly doped drain region are formed in the substrates on both sides of the gate and are asymmetrically distributed with respect to the gate.
[0010] Wherein, the width of the lightly doped source region extending below the gate is the first overlap width, the width of the lightly doped drain region extending below the gate is the second overlap width, the first overlap width is less than the second overlap width, and the ratio of the first overlap width to the second overlap width is 1:1.5 to 1:2.
[0011] Optionally, the width of the lightly doped region symmetrically distributed with respect to the gate, formed by the self-aligned process, extending below the gate is the standard overlap width, and the difference between the standard overlap width and the first overlap width is equal to the difference between the second overlap width and the standard overlap width.
[0012] Optionally, the overall width of the lightly doped region at the source end is less than or equal to the overall width of the lightly doped region at the drain end.
[0013] Optionally, the overall depth of the lightly doped region at the source end is less than or equal to the overall depth of the lightly doped region at the drain end.
[0014] Optionally, the MOSFET device further includes a gate oxide layer formed between the gate and the substrate.
[0015] Optionally, the MOSFET device further includes a source region and a drain region. The source region is formed in a substrate surrounding the lightly doped source region, and the drain region is formed in a substrate surrounding the lightly doped drain region. The lightly doped source region, the lightly doped drain region, the source region, and the drain region have the same conductivity type. The source region is heavily doped relative to the lightly doped source region, and the drain region is heavily doped relative to the lightly doped drain region.
[0016] Optionally, the source region and the drain region are symmetrically distributed about the gate.
[0017] Optionally, the MOSFET device further includes a gate sidewall formed on the substrate and on the sidewall of the gate.
[0018] Optionally, the widths of the gate sidewalls on both sides of the gate are the same, or the width of the gate sidewall located above the lightly doped region at the source is smaller than that of the gate sidewall located above the lightly doped region at the drain.
[0019] Compared with the prior art, the MOSFET device provided by this invention has asymmetrical distribution of the lightly doped source region and the lightly doped drain region with respect to its gate. The ratio between the width of the lightly doped source region extending below the gate and the width of the lightly doped drain region extending below the gate is 1:1.5 to 1:2. By controlling the ratio of the degree of asymmetry of the lightly doped regions on both sides of the gate, the hot carrier injection (HCI) effect is improved without affecting the effective channel length of the device, thereby ensuring that leakage current is not affected and thus improving device performance. Attached Figure Description
[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
[0021] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing MOSFET device.
[0022] Figure 2 This is a schematic cross-sectional view of an example MOSFET device according to an embodiment of the present invention.
[0023] Figure 3 yes Figure 2 The diagram shows a top view of the MOSFET device.
[0024] Figures 4 to 6 This is a cross-sectional structural schematic diagram of another example of a MOSFET device according to an embodiment of the present invention. Detailed Implementation
[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some technical features well-known in the art have not been described in order to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that in the following embodiments, when referring to the quantity of elements, etc. (including number, value, quantity, range, etc.), the reference is not limited to that specific quantity, except where specifically stated or clearly limited in principle to a specific quantity, and may be more or less than that specific quantity. Furthermore, it goes without saying that in the following embodiments, structural elements (including elements, steps, etc.) are not necessary, except where specifically stated or generally considered clearly necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of structural elements, etc., the references include cases that are actually approximately or similar to the shape, except for cases that are specifically stated or are generally considered not to be so in principle. The same applies to the above-mentioned values and ranges.
[0026] Please refer to Figure 2 One embodiment of this utility model provides a MOSFET device, which includes a substrate, a gate, a lightly doped source region LDD_S, and a lightly doped drain region LDD_D.
[0027] The substrate can be any suitable material in the art, such as a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, etc. An active region AA can be defined in the substrate using trap ion implantation and shallow trench isolation processes. A gate is formed above the active region AA on the substrate. This gate can be heavily doped polysilicon or a metal gate. Optionally, a gate oxide layer OX is sandwiched between the gate and the substrate. This gate oxide layer OX is silicon dioxide or a high-dielectric-constant material, etc.
[0028] The source-side lightly doped drain region LDD_S and the drain-side lightly doped drain region LDD_D are respectively formed in the substrate on both sides of the gate Gate and are asymmetrically distributed with respect to the gate Gate. Specifically, the width of the source-side lightly doped drain region LDD_S extending under the gate Gate is the first overlap width W2, and the width of the drain-side lightly doped drain region LDD_D extending under the gate Gate is the second overlap width W3, where W2 < W3. And through repeated experiments, when W2 / W3 is 1:1.5 to 1:2, it will not deteriorate the short-channel effect of the MOSFET device, and while improving the hot carrier injection effect of the MOSFET device, it can avoid an increase in leakage current, thereby improving the device performance.
[0029] Among them, the width of the lightly doped drain region symmetrically distributed with respect to the gate formed by the traditional self-aligned process extending under the gate is defined as the standard overlap width W1, and the overall width of the lightly doped drain region on one side of the gate is W0, and the depth is H.
[0030] Please refer to Figures 2 to 3 , in an example, W1 - W2 = W3 - W1. In this example, the corresponding photomask can be used to perform ion implantation of light doping on the substrate to form the source-side lightly doped drain region LDD_S and the drain-side lightly doped drain region LDD_D; then the gate oxide layer OX and the gate Gate are formed on the substrate by using the gate photomask, the gate oxide process, and the gate process in the prior art, and the formed gate can be offset by a distance of W1 - W2 in the direction of the drain region relative to the gate formed in the prior art. This example does not require modifying the gate photomask, reducing costs.
[0031] Please continue to refer to Figure 2 , in this example, the overall width of the source-side lightly doped drain region LDD_S and the overall width of the drain-side lightly doped drain region LDD_D are both W0, and the depth of the source-side lightly doped drain region LDD_S and the depth of the drain-side lightly doped drain region LDD_D are both H, that is, the overall width of the source-side lightly doped drain region LDD_S is equal to the overall width of the drain-side lightly doped drain region LDD_D, and the depth D of the source-side lightly doped drain region LDD_S is equal to the depth of the drain-side lightly doped drain region LDD_D. Thus, in this example, the source-side lightly doped drain region LDD_S and the drain-side lightly doped drain region LDD_D can be formed by the same ion implantation process, and their formation regions can be the same as those in the prior art, thereby simplifying the process and reducing costs.
[0032] In another example, please refer to Figure 4, the overall width of the source-side lightly doped region LDD_S and the overall width of the drain-side lightly doped region LDD_D are both W0. The depth of the source-side lightly doped region LDD_S is H1, and the depth of the drain-side lightly doped region LDD_D is H, and H1 < H. That is, the overall width of the source-side lightly doped region LDD_S is equal to the overall width of the drain-side lightly doped region LDD_D, and the depth D of the source-side lightly doped region LDD_S is less than the depth of the drain-side lightly doped region LDD_D. Thus, in this example, the source-side lightly doped region LDD_S and the drain-side lightly doped region LDD_D can be formed by ion implantation processes with different implantation depths. Among them, the depth of the source-side lightly doped region LDD_S is less than the depth of the source-side lightly doped region LDD_S formed under the prior art, and the depth of the drain-side lightly doped region LDD_D is equal to the depth of the source-side lightly doped region LDD_S formed under the prior art. In this example, a shallower junction can be achieved at the source end relative to the prior art, thereby effectively reducing the parasitic capacitance of the transistor, which is beneficial for manufacturing transistors with higher speed and higher efficiency.
[0033] In another example, please refer to Figure 5 , the overall width of the source-side lightly doped region LDD_S is W3, the overall width of the drain-side lightly doped region LDD_D is W0, the depth of the source-side lightly doped region LDD_S is H1, and the depth of the drain-side lightly doped region LDD_D is H, and W3 < W0, H1 < H. That is, the overall width of the source-side lightly doped region LDD_S is less than the overall width of the drain-side lightly doped region LDD_D, and the depth D of the source-side lightly doped region LDD_S is less than the depth of the drain-side lightly doped region LDD_D. Thus, in this example, the source-side lightly doped region LDD_S and the drain-side lightly doped region LDD_D can be formed by ion implantation processes with different implantation depths and different implantation widths. In this example, not only can a shallower junction be achieved at the source end relative to the prior art, effectively reducing the parasitic capacitance of the transistor, but also the resistance at the source end can be reduced, which is beneficial for manufacturing transistors with higher speed and higher efficiency.
[0034] Please refer to Figure 6In another embodiment of the present invention, the MOSFET device further includes a source region S and a drain region D. The source region S is formed in a substrate surrounding the lightly doped source region LDD_S, and the drain region D is formed in a substrate surrounding the lightly doped drain region LDD_D. The lightly doped source region LDD_S, the lightly doped drain region LDD_D, the source region S, and the drain region D have the same conductivity type (e.g., all are n-type). The source region S is heavily doped relative to the lightly doped source region LDD_S, and the drain region D is heavily doped relative to the lightly doped drain region LDD_D. Optionally, the source region S and drain region D can be formed after the formation of the gate and gate sidewalls via a self-aligned source-drain implantation process. The source region S and drain region D are symmetrically distributed about the gate, i.e., the lateral distance from the source region S and drain region D to the gate is W5. In this case, the overall width of the lightly doped source region LDD_S is W5+W2, and the overall width of the lightly doped drain region LDD_D is W5+W3, where W5+W2... <W5+W3。
[0035] Alternatively, please continue to refer to Figure 6 The MOSFET device also includes gate sidewalls SP_S and SP_D, both of which are formed on the substrate. Gate sidewall SP_S is formed on the sidewall of the gate above the lightly doped source region LDD_S and extends downwards to the sidewall of the gate oxide layer OX, contacting the substrate surface. Gate sidewall SP_D is formed on the sidewall of the gate above the lightly doped drain region LDD_D and extends downwards to the sidewall of the gate oxide layer OX, contacting the substrate surface.
[0036] In one example, the gate sidewalls SP_S and SP_D on both sides of the gate have the same width, for example, both have a bottom width of W5. Therefore, conventional gate sidewall technology can be used to form the gate sidewalls SP_S and SP_D. Thus, the formation positions of the source region S and the drain region D are defined by the gate sidewalls SP_S and SP_D, so that the source region S and the drain region D are symmetrically distributed on both sides of the gate.
[0037] In another example, according to device performance requirements, the width of the gate sidewall SP_S located above the lightly doped source region LDD_S is smaller than that of the gate sidewall SP_D located above the lightly doped drain region LDD_D. Thus, the formation positions of the source region S and the drain region D are defined by the gate sidewalls SP_S and SP_D, and the source region S and the drain region D are asymmetrically distributed on both sides of the gate.
[0038] In summary, the source-side lightly doped region and the drain-side lightly doped region of the MOSFET device provided by this invention are asymmetrically distributed with respect to the gate, and the ratio between the width of the source-side lightly doped region extending below the gate and the width of the drain-side lightly doped region extending below the gate is 1:1.5 to 1:2. Therefore, by controlling the ratio of the asymmetric distribution of the lightly doped regions on both sides of the gate, the hot carrier injection (HCI) effect is improved without affecting the effective channel length of the device, thereby ensuring that leakage current is not affected, thus improving device performance.
[0039] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present utility model.
Claims
1. A MOSFET device, characterized by, Comprise: a substrate, a gate formed on the substrate; a source lightly doped region and a drain lightly doped region formed in the substrate on both sides of the gate respectively and asymmetrically distributed about the gate; wherein the source lightly doped region extends under the gate with a first overlap width, the drain lightly doped region extends under the gate with a second overlap width, the first overlap width is smaller than the second overlap width and the ratio of the first overlap width to the second overlap width is 1:1.5-1:
2.
2. The MOSFET device of claim 1, wherein, The lightly doped region formed by a self-alignment process and symmetrically distributed about the gate extends under the gate with a standard overlap width, the difference between the standard overlap width and the first overlap width is equal to the difference between the second overlap width and the standard overlap width.
3. The MOSFET device of claim 2, wherein, The overall width of the source lightly doped region is smaller than or equal to the overall width of the drain lightly doped region.
4. The MOSFET device of any of claims 1-3, wherein, The overall depth of the source lightly doped region is smaller than or equal to the overall depth of the drain lightly doped region.
5. The MOSFET device of claim 1, wherein, Further comprise a gate oxide layer formed between the gate and the substrate.
6. The MOSFET device of claim 1, wherein, Further comprise a source region formed in the substrate outside the source lightly doped region and a drain region formed in the substrate outside the drain lightly doped region, and the source region and the drain region are of the same conductivity type as the source lightly doped region and the drain lightly doped region, and the source region is heavily doped relative to the source lightly doped region and the drain region is heavily doped relative to the drain lightly doped region.
7. The MOSFET device of claim 6, wherein, The source region and the drain region are symmetrically distributed about the gate.
8. The MOSFET device of claim 1, wherein, Further comprise a gate side wall formed on the substrate and on the sidewall of the gate.
9. The MOSFET device of claim 8, wherein, The width of the gate side wall on both sides of the gate is the same, or the width of the gate side wall above the source lightly doped region is smaller than the gate side wall above the drain lightly doped region.