Cascade chip voltage division circuit
An adaptive voltage divider module composed of voltage divider resistors and NMOS transistors solves the problem of uneven voltage division during chip cascading, achieving uniform voltage division and low power consumption, and reducing the cost of chip sorting.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, when multiple chips are cascaded, the voltage distribution is uneven due to differences in electrical characteristics, some chips cannot work properly, power consumption increases, and the cost of sieving and sorting chips is high.
A voltage divider module consisting of voltage divider resistors, differential-to-single-ended modules, and NMOS transistors monitors the difference between the chip voltage and the reference voltage in real time and dynamically adjusts the turn-on ratio of the NMOS transistors to form an adaptive and precise voltage divider.
It achieves uniform voltage distribution on the chip, reduces cost and power consumption, reduces ineffective energy consumption by 30%-70%, and eliminates the need for chip sieving and sorting.
Smart Images
Figure CN224096168U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the technical field of partial pressure, especially, a kind of cascading chip partial pressure circuit. BACKGROUND
[0002] In many electronic devices, in order to realize specific function or processing demand (such as improving computing ability, processing specific signal, etc.), multiple chip series cascading structure is often used.For example, in high-performance computing board, in order to cooperatively process complex task, multiple computing chips are cascaded.
[0003] At present, resistance is generally used to divide voltage of chip in industry to realize voltage division of multiple chips. When chip works normally, it can be equivalent to a resistance. Due to inherent discreteness of semiconductor manufacturing process, electrical characteristics of each chip in series are difficult to be completely consistent, so the equivalent resistance of each chip is different. This characteristic difference will lead to uneven voltage division of chip. Uneven voltage division will lead to that part of chip is divided voltage too low, which is lower than chip working voltage and cannot work normally, and divided voltage is too high, which increases power consumption of chip a lot.
[0004] In addition, in prior art, in order to realize accurate voltage division, chip screening standard needs to be classified more finely, which increases classification cost and maintenance cost. INVENTION CONTENTS
[0005] Therefore, in view of the above technical problems, a cascading chip partial pressure circuit is provided.
[0006] To solve the above technical problems, the utility model adopts the following technical scheme:
[0007] A cascading chip partial pressure circuit, characterized by comprising:
[0008] Partial pressure resistance, the partial pressure resistance is connected in series on the power supply of the chip;
[0009] A differential-to-single-ended module for collecting positive reference voltage and negative reference voltage from both ends of the partial pressure resistance respectively and outputting as reference voltage, the input end of the differential-to-single-ended module is connected with both ends of the partial pressure resistance;
[0010] Partial pressure module, the partial pressure module includes NMOS tube for dividing voltage of the chip and first control unit for closing the NMOS tube when chip voltage is lower than the reference voltage and controlling opening proportion of the NMOS tube according to proportionality with high amount when chip voltage is higher than the reference voltage, the gate of the NMOS tube is connected with the output end of the first control unit, the source is grounded, the drain is connected with the power supply pin of the chip, and the input end of the first control unit is connected with the power supply pin and the output end of the differential-to-single-ended module.
[0011] The utility model discloses a kind of cascaded chip voltage division circuits, difference is converted into single-ended module and the voltage difference of the voltage division resistor both ends is converted into single-ended reference voltage, to provide independent, stable reference voltage for corresponding chip, first control unit monitors the difference of chip voltage and reference voltage in real time, when chip voltage>reference voltage, first control unit can be according to the opening proportion of NMOS pipe proportional control (voltage high amount) difference, form dynamic voltage division path, realize the adaptive precision voltage division of chip based on voltage difference, do not need to screen chip, reduce cost. BRIEF DESCRIPTION OF DRAWINGS
[0012] The utility model will be described in detail in combination with the drawings and specific embodiment:
[0013] Figure 1 The structure diagram of a kind of cascaded chip voltage division circuits provided for the embodiment of the application;
[0014] Figure 2 The schematic diagram of the application environment of the embodiment of the application. DETAILED DESCRIPTION
[0015] Figure 2 The application environment of the embodiment of the application is shown, including multiple voltage division circuits 1 and multiple chips 2, multiple voltage division circuits 1 and multiple chips 2 one-to-one correspondence, respectively for corresponding chip 2 is divided, to realize the equalization of multiple chips 2, wherein, chip 2 can be the computing chip of computing board, multiple chips 2 and power supply VCC are connected in series.
[0016] As Figure 1 Shown, the embodiment of the application provides a kind of cascaded chip voltage division circuits 1, including voltage division resistor 110, difference is converted into single-ended module 120, voltage division module 130 and overcurrent protection module 140.
[0017] The voltage division resistor 110 of multiple voltage division circuits 1 is connected in series on power supply VCC in turn, and the last voltage division resistor 110 is grounded.
[0018] Wherein, since voltage division resistor 110 is not for chip voltage division, but provides reference voltage, so higher resistance (1K-10K ohm) resistance (less than or equal to 1 ohm) compared with traditional voltage division resistor can be used, with 1K ohm as an example, compared with traditional 1 ohm resistance, static power consumption is 1000 times less.
[0019] Difference is converted into single-ended module 120 for collecting positive reference voltage and negative reference voltage from the both ends of voltage division resistor 110 and single-ended output as reference voltage.
[0020] In the embodiment, the differential-to-single-ended module 120 comprises a first operational amplifier 121, the positive input terminal and the negative input terminal of the first operational amplifier 121 are connected with the two ends of the voltage dividing resistor 110 as the input terminals of the differential-to-single-ended module 120, and the output terminal thereof is the output terminal of the differential-to-single-ended module 120 and outputs the reference voltage.
[0021] The voltage dividing module 130 comprises an NMOS transistor 131 and a first control unit.
[0022] The NMOS transistor 131 is used for voltage dividing for the corresponding chip 2, the gate thereof is connected with the output terminal of the first control unit, the source thereof is grounded, and the drain thereof is connected with the power supply pin of the chip 1.
[0023] The first control unit comprises a second operational amplifier 132a and a third operational amplifier 132b.
[0024] The positive input terminal and the negative input terminal of the second operational amplifier 132a are the input terminals of the first control unit, wherein the positive input terminal is connected with the power supply pin of the chip 1 through the third operational amplifier 132b, the negative input terminal is connected with the output terminal of the first operational amplifier 121, and the output terminal thereof is the output terminal of the first control unit and is connected with the gate of the NMOS transistor 131.
[0025] The positive input terminal and the negative input terminal of the second operational amplifier 132a obtain the chip voltage and the reference voltage from the power supply pin of the chip 1 and the output terminal of the first operational amplifier 121 respectively, when the chip voltage is lower than the reference voltage, the second operational amplifier 132a outputs a low level to make the NMOS transistor 131 close (cut off), when the chip voltage is higher than the reference voltage, the second operational amplifier 132a outputs a high level to make the NMOS transistor 131 open (conduct), wherein the voltage of the high level output by the second operational amplifier 132a is proportional to the overage (the difference between the chip voltage and the reference voltage), that is, the higher the chip voltage is higher than the reference voltage, the greater the voltage output by the second operational amplifier 132a, the greater the voltage, the greater the opening ratio of the NMOS transistor 131, thereby, the opening ratio of the NMOS transistor 131 can be controlled according to the size of the voltage, the greater the opening ratio, the stronger the voltage dividing capability of the NMOS transistor 131, so that the chip 1 can be adaptively voltage divided according to the degree that the chip voltage is higher than the reference voltage.
[0026] The positive input terminal of the third operational amplifier 132b is connected with the power supply pin of the chip 1, and the output terminal thereof is connected with the positive input terminal of the second operational amplifier 132a, which functions to increase the input impedance and driving capability of the power supply pin, and therefore, the third operational amplifier 132b can be omitted.
[0027] The overcurrent protection module 140 is configured to close the NMOS tube 131 when the current of the NMOS tube 131 exceeds a threshold value.
[0028] In the embodiment, the overcurrent protection module 140 comprises a current sensor 141, a first switch 142 which is always open, a second switch 143 which is always closed, a NOT gate 144 and a second control unit 145.
[0029] The current sensor 141 is configured to collect the current of the NMOS tube 131, and is connected to the source of the NMOS tube 131 and the input of the second control unit 145.
[0030] The first switch 142 is connected to the gate and the source of the NMOS tube 131.
[0031] The second switch 143 is connected between the gate of the NMOS tube 131 and the output of the second operational amplifier 132a.
[0032] The output of the second control unit 145 is connected to the control end of the first switch 142, and the output is also connected to the control end of the second switch 143 through the NOT gate 144.
[0033] When the current of the NMOS tube 131 exceeds the set threshold value, which means that the current exceeds the bearing capacity of the NMOS tube 131, the output of the second control unit 145 outputs a high level, so that the first switch 142 is closed, thereby short-circuiting the gate and the source of the NMOS tube 131, and the NMOS tube 131 is closed to protect it. At the same time, the output high level becomes a low level through the NOT gate 144, so that the second switch 143 is opened. The purpose is to avoid the output end of the second operational amplifier 132a being connected to the ground through the first switch 142, which causes the second operational amplifier 132a to work continuously at high power and increase power consumption. Therefore, the second switch 143 and the NOT gate 144 can be omitted.
[0034] In the embodiment, the first switch 142 and the second switch 143 can be MOS tubes, and the second control unit 145 can be an ASIC chip.
[0035] As can be seen from the above, the cascade chip voltage dividing circuit provided by the embodiment of the application converts the voltage difference between the two ends of the voltage dividing resistor into a single-ended reference voltage through the differential-to-single-ended module, to provide an independent and stable reference voltage for the corresponding chip. The first control unit monitors the difference between the chip voltage and the reference voltage in real time. When the chip voltage > the reference voltage, the first control unit can control the opening ratio of the NMOS tube according to the proportional relationship between the voltage difference (voltage overshoot), to form a dynamic voltage dividing path, thereby realizing adaptive and accurate voltage division of the chip based on the voltage difference, without the need to screen the chip, thereby reducing the cost.
[0036] The traditional resistance voltage division needs to consume power continuously, and the embodiment of the application only activates the dynamic voltage division path when the chip voltage exceeds the standard, which significantly reduces the invalid power consumption (can reduce 30%-70% in typical scenarios), and.
[0037] In addition, the voltage division resistance of the embodiment of the application is not for voltage division of the chip, but provides a reference voltage, so a higher resistance value resistance can be used compared with the traditional voltage division resistance, further reducing power consumption.
[0038] However, those skilled in the art in the technical field should realize that the above embodiments are only used to illustrate the utility model, and are not used as a limitation on the utility model, as long as the changes and modifications of the above described embodiments are within the scope of the utility model, they will fall within the scope of the claims of the utility model.
Claims
1. A cascaded chip voltage divider circuit, characterized in that, include: A voltage divider resistor is connected in series with the power supply of the chip; A differential-to-single-ended module is used to acquire positive and negative reference voltages from the two ends of the voltage divider resistor and output them as reference voltages. The input end of the differential-to-single-ended module is connected to the two ends of the voltage divider resistor. The voltage divider module includes an NMOS transistor for dividing the voltage of the chip and a first control unit for turning off the NMOS transistor when the chip voltage is lower than the reference voltage and controlling the NMOS transistor to turn on proportionally to the excess voltage when the chip voltage is higher than the reference voltage. The gate of the NMOS transistor is connected to the output terminal of the first control unit, the source is grounded, and the drain is connected to the power supply pin of the chip. The input terminal of the first control unit is connected to the power supply pin and the output terminal of the differential-to-single-ended module.
2. The cascaded chip voltage divider circuit according to claim 1, characterized in that, The differential-to-single-ended module includes a first operational amplifier, the positive input terminal and the inverting input terminal of the first operational amplifier are respectively connected to the two ends of the voltage divider resistor, and its output terminal is connected to the input terminal of the first control unit.
3. The cascaded chip voltage divider circuit according to claim 1, characterized in that, The first control unit includes a second operational amplifier, the positive input terminal and the negative input terminal of the second operational amplifier are respectively connected to the power supply pin and the output terminal of the differential to single-ended module, and its output terminal is connected to the gate of the NMOS transistor.
4. A cascaded chip voltage divider circuit according to claim 3, characterized in that, The first control unit further includes a third operational amplifier, the positive input terminal of which is connected to the power supply pin, and its output terminal is connected to the positive input terminal of the second operational amplifier.
5. A cascaded chip voltage divider circuit according to claim 1, characterized in that, It also includes an overcurrent protection module for shutting down the NMOS transistor when the current in the NMOS transistor exceeds a threshold.
6. A cascaded chip voltage divider circuit according to claim 5, characterized in that, The overcurrent protection module includes a current sensor for acquiring the current of the NMOS transistor, a normally open first switch, and a second control unit for controlling the first switch to close to short-circuit the gate and source of the NMOS transistor when the current of the NMOS transistor exceeds a threshold. The current sensor is connected to the source of the NMOS transistor and the input terminal of the second control unit. The first switch is connected to the gate and source of the NMOS transistor. The output terminal of the second control unit is connected to the control terminal of the first switch.
7. A cascaded chip voltage divider circuit according to claim 6, characterized in that, The overcurrent protection module further includes a normally closed second switch and a NOT gate. The second switch is connected between the gate of the NMOS transistor and the output terminal of the first control unit. The output terminal of the second control unit is connected to the control terminal of the second switch via the NOT gate.
8. A cascaded chip voltage divider circuit according to claim 7, characterized in that, Both the first switch and the second switch are MOSFETs.
9. A cascaded chip voltage divider circuit according to claim 8, characterized in that, The second control unit is an ASCII chip.