Semiconductor device

Abstract

The utility model provides a semiconductor device, which comprises a semiconductor substrate, a first electrode and a second electrode, a plurality of first and second substrate vias extending through the semiconductor substrate; an interconnect structure disposed over the semiconductor substrate, the interconnect structure including a plurality of first metallization patterns electrically coupled to the first substrate vias and a plurality of second metallization patterns electrically coupled to the second substrate vias; a first sealing ring surrounding the first metallization pattern and defining a first semiconductor region; the second sealing ring surrounds the second metallization pattern and defines a second semiconductor region; a local interconnect structure bonding both the first semiconductor region and the second semiconductor region and directly covering the first seal ring and the second seal ring; and a first redistribution circuit structure disposed on the semiconductor device, the first redistribution circuit structure being electrically connected to the first semiconductor region through the first substrate via and electrically connected to the second semiconductor region through the second substrate via.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this improvement in integration has come from the iterative reduction in the smallest feature size (e.g., shrinking semiconductor process nodes to below 20nm), allowing more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the need for smaller and more innovative semiconductor die packaging technologies is also increasing.

[0003] With further advancements in semiconductor technology, stacked and bonded semiconductor devices have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor assemblies, active circuit systems such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically bonded together to form functional components. This bonding process uses complex techniques and requires improvement. Utility Model Content

[0004] This utility model provides a semiconductor device, including: a semiconductor substrate; a plurality of first substrate vias and a plurality of second substrate vias extending through the semiconductor substrate; an interconnect structure disposed above the semiconductor substrate, the interconnect structure including a plurality of first metallization patterns electrically coupled to the plurality of first substrate vias and a plurality of second metallization patterns electrically coupled to the plurality of second substrate vias; a first sealing ring surrounding the plurality of first metallization patterns and defining a first semiconductor region; and a second sealing ring surrounding the plurality of second metallization patterns and defining a second semiconductor region; a partial interconnect structure joining the first semiconductor region and the second semiconductor region, wherein the partial interconnect structure directly covers the first sealing ring and the second sealing ring; and a first redistributed circuit structure disposed on the semiconductor device, the first redistributed circuit structure being electrically connected to the first semiconductor region through the plurality of first substrate vias and electrically connected to the second semiconductor region through the plurality of second substrate vias. Attached Figure Description

[0005] The various aspects of the embodiments of this utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1 to 8 A semiconductor wafer is shown according to some embodiments, wherein a semiconductor device is attached to the semiconductor wafer to form a first semiconductor package.

[0007] Figure 9 A top-down cross-sectional view of a first semiconductor package according to some embodiments is shown.

[0008] Figures 10 to 18 This illustrates the formation of a second semiconductor package using a local interconnect first process according to some embodiments.

[0009] Figure 19 A top-down cross-sectional view of a second semiconductor package according to some embodiments is shown.

[0010] Figures 20 to 30 This illustrates the formation of a third semiconductor package using a second process with local interconnects according to some embodiments.

[0011] Figure 31 A top-down cross-sectional view of a third semiconductor package according to some embodiments is shown.

[0012] Figure 32A A first semiconductor package having a substrate through-hole protection ring and a deep trench capacitor is shown according to some embodiments.

[0013] Figure 32B A top-down cross-sectional view is shown of a substrate through-hole protection ring surrounding a through-substrate through-hole according to some embodiments.

[0014] [Icon Symbol Explanation]

[0015] 100: Semiconductor wafer;

[0016] 101: First semiconductor device area;

[0017] 102: Middle area;

[0018] 103: First substrate;

[0019] 105: First metallization layer;

[0020] 107: First active device;

[0021] 111: First substrate perforation;

[0022] 151: Perforation opening in the first metallization layer;

[0023] 153: Dielectric materials;

[0024] 155: First conductive structure;

[0025] 175: Sealing ring;

[0026] 201: Perforation of the first metallization layer;

[0027] 207: First conductive bonding pad;

[0028] 209: First wafer bonding layer;

[0029] 301: Second active device;

[0030] 303, 1083, 2503: Dielectrics;

[0031] 305: Second conductive structure;

[0032] 307: Perforation of the second metallization layer;

[0033] 313: First Semiconductor die;

[0034] 315: Second semiconductor die;

[0035] 317: Second substrate;

[0036] 319: Second metallization layer;

[0037] 321: Second wafer bonding layer;

[0038] 323: Second conductive bonding pad;

[0039] 350: First section internal interconnect core;

[0040] 351: First interconnect substrate;

[0041] 353: First internal interconnect structure;

[0042] 355: First inner line metallized pattern;

[0043] 357: First interconnect dielectric layer;

[0044] 375: First internal interconnect conductive pad;

[0045] 401: First package seal;

[0046] 500: First substrate;

[0047] 501: First bonding layer;

[0048] 503: Second bonding layer;

[0049] 601: Depression;

[0050] 701: First passivation film;

[0051] 800: First backside overlay circuit structure;

[0052] 801: Re-lay the metallization layer;

[0053] 803: Redistributed dielectric layer;

[0054] 805: Redistributed conductive components;

[0055] 807: First metallized contact pad;

[0056] 809: First layer of passivation;

[0057] 811: Metal under the first bump;

[0058] 818: First conductive connector;

[0059] 850: First Semiconductor Package;

[0060] 1000: Second carrier substrate;

[0061] 1001: Third semiconductor die;

[0062] 1003: The fourth semiconductor die;

[0063] 1005: Second part internal interconnect core;

[0064] 1021: Second interconnect substrate;

[0065] 1023: Second internal connection structure;

[0066] 1025: Second inner line metallized pattern;

[0067] 1027: Second interconnect dielectric layer;

[0068] 1051: Third bonding layer;

[0069] 1071: Third active device;

[0070] 1077: Third substrate;

[0071] 1079: Third metallization layer;

[0072] 1081: Third conductive structure;

[0073] 1101: Second package sealed;

[0074] 1200: Third substrate;

[0075] 1201: Fourth bonding layer;

[0076] 1203: Fifth bonding layer;

[0077] 1300: First carrier removal process;

[0078] 1401: Perforation of the third metallization layer;

[0079] 1409: Third wafer bonding layer;

[0080] 1411: Third conductive bonding pad;

[0081] 1501: First semiconductor device;

[0082] 1503: Second semiconductor device;

[0083] 1553: Substrate of the first device;

[0084] 1555: First device metallization layer;

[0085] 1557, 2057: Fourth active device;

[0086] 1559: Perforation of the metallization layer of the first device;

[0087] 1561: First device substrate perforation;

[0088] 1563: First device bonding layer;

[0089] 1565: Conductive bonding material for the first device;

[0090] 1601: Third package seal;

[0091] 1701: Second passivation film;

[0092] 1850: Second semiconductor package;

[0093] 2000: Fourth substrate;

[0094] 2001: Third Semiconductor Device;

[0095] 2003: The Fourth Semiconductor Device;

[0096] 2050: Third local internal connection structure;

[0097] 2053: Substrate for the second device;

[0098] 2055: Second device metallization layer;

[0099] 2061: Second device substrate perforation;

[0100] 2071: Sixth bonding layer;

[0101] 2073: Seventh bonding layer;

[0102] 2101: Fourth package sealed;

[0103] 2200: Fifth substrate;

[0104] 2251: Eighth bonding layer;

[0105] 2253: Ninth bonding layer;

[0106] 2300: Second carrier removal process;

[0107] 2401: Perforation of the metallization layer of the second device;

[0108] 2403: Fourth wafer bonding layer;

[0109] 2405: Fourth conductive bonding pad;

[0110] 2501: The fifth active device;

[0111] 2505: Fourth conductive structure;

[0112] 2507: Perforation of the fourth metallization layer;

[0113] 2513: The fifth semiconductor die;

[0114] 2515: The sixth semiconductor die;

[0115] 2517: Fourth substrate;

[0116] 2519: Fourth metallization layer;

[0117] 2521: Fifth wafer bonding layer;

[0118] 2523: Fifth conductive bonding pad;

[0119] 2550: Third section internal interconnect core;

[0120] 2557: Third interconnect dielectric layer;

[0121] 2571: Third interconnect substrate;

[0122] 2573: Third internal connection structure;

[0123] 2575: Third inner line metallized pattern;

[0124] 2601: Fifth package sealed;

[0125] 2700: Sixth substrate;

[0126] 2751: Tenth bonding layer;

[0127] 2753: Eleventh bonding layer;

[0128] 2800: Third carrier removal process;

[0129] 2901: Third passivation film;

[0130] 3050: Third semiconductor package;

[0131] 3201: TSV protection ring;

[0132] 3203: Deep trench capacitor;

[0133] AA: Section cutting line. Detailed Implementation

[0134] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be reused in various instances of this disclosure. Such reuse is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0135] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0136] Examples of bonding various device wafers or semiconductor devices via front-side to front-side orientation (sometimes referred to as face-to-face bonding) will be described below. Front-side to front-side orientation allows back-side redistribution structures to be combined with local interconnect structures to provide additional connection paths between active circuit systems. This sequence of steps and the resulting structural arrangement provide improved processes and structures that help reduce or eliminate potential dielectric stripping.

[0137] Now for reference Figure 1 The image illustrates a semiconductor wafer 100 in which a plurality of first semiconductor device regions 101 are formed and located on the semiconductor wafer 100. In a particular embodiment, the first semiconductor device regions 101 may be memory devices, such as dynamic random access memory (DRAM) devices with a large number of I / O interfaces, for example, more than 256 interfaces, thus enabling large bandwidth data even at low clock speeds. However, the first semiconductor device regions 101 may also be any other suitable type of memory device with a high rate of data transfer (e.g., LPDDRn memory devices or the like with a high data transfer rate), or any other suitable device (e.g., logic dies, central processing unit (CPU) dies, input / output dies, combinations thereof, etc.). Additionally, the semiconductor wafer 100 may be received by the manufacturer from a third-party manufacturer or may be manufactured internally.

[0138] In one embodiment, the first semiconductor device region 101 may include a first substrate 103, a plurality of first active devices 107, and a plurality of first metallization layers 105. The first substrate 103 may include a doped or undoped bulk silicon material or an active layer with a silicon-on-insulator (SOI) substrate on an insulating layer. Generally, the SOI substrate comprises a layer of semiconductor material, including, for example, silicon, germanium, silicon-germanium, SOI, silicon-germanium on-insulator (SGOI), or combinations thereof. Other substrates that can be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

[0139] The first active device 107 includes a variety of active and passive devices, such as capacitors, resistors, inductors, and the like, which can be used to achieve the desired structural and functional requirements of the design of the first semiconductor device region 101. The first active device 107 can be formed on or within the first substrate 103 using any suitable method.

[0140] A first metallization layer 105 is formed on the first substrate 103 and the first active device 107, intended to connect the respective active devices to form a functional circuit system. In one embodiment, the first metallization layer 105 is formed by multiple first alternating layers of dielectric material 153 (e.g., low-k dielectric material, extremely low-k dielectric material, ultra-low-k dielectric material, combinations thereof, or the like) and multiple first conductive structures 155 (e.g., multiple wires and multiple vias). In one embodiment, the first metallization layer 105 can be formed by any suitable process (e.g., deposition, metal damascene, double-track metal damascene, etc.). In one embodiment, at least four metallization layers may be spaced apart from the first substrate 103 through at least one interlayer dielectric layer (ILD), but the exact number of first metallization layers 105 depends on the design of the first semiconductor device region 101.

[0141] Multiple first substrate vias (TSVs) 111 may be formed within the first substrate 103, and, if desired, within one or more layers of the first metallization layer 105, to provide electrical connectivity from the front side of the first substrate 103 to the back side of the first substrate 103. In one embodiment, the first substrate vias 111 may be formed by initially forming multiple silicon via openings in the first substrate 103, and, if desired, any overlying first metallization layer 105 may be formed (e.g., after the desired first metallization layer 105 has been formed but before the formation of the next overlying first metallization layer 105). The silicon via openings may be formed by applying and developing appropriate photoresist and removing a portion of the exposed underlying material to the desired depth. The silicon via openings may be formed to extend into the first substrate 103 to a depth greater than the final desired height of the first substrate 103. Thus, while the depth depends on the overall design, it may be between about 20 μm and about 200 μm, for example, about 50 μm.

[0142] After the silicon through-hole openings have been formed within the first substrate 103 and / or any first metallization layer 105, the silicon through-hole openings can be lined with a liner. The liner can be, for example, an oxide or silicon nitride formed from tetraethylorthosilicate (TEOS), but any suitable dielectric material can also be used. The liner can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, but other suitable processes such as physical vapor deposition (PVD) or thermal processes can also be used. Additionally, the liner can be formed with a thickness between about 0.1 μm and about 5 μm, for example, about 1 μm.

[0143] After forming a pad along the sidewalls and bottom of the silicon through-hole opening, a barrier layer is formed, and any remaining portion of the silicon through-hole opening can be filled with a first conductive material. The first conductive material may include copper, but other suitable materials may also be used, such as aluminum alloys, doped polycrystalline silicon, combinations thereof, and the like. The first conductive material can be formed by electroplating copper onto a seed layer to fill and overfill the silicon through-hole opening. After the silicon through-hole opening has been filled, excess pads, barrier layer, seed layer, and first conductive material located outside the silicon through-hole opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process may also be used.

[0144] In some embodiments, one or more seal rings 175 are located at the periphery of each of the first semiconductor device regions 101. Each seal ring 175 may be a loop configuration (see, for example...). Figure 9 The sealing ring 175 surrounds the functional metallization pattern (e.g., circuitry) in each first semiconductor device region 101. In one embodiment, the sealing ring 175 may further serve as a boundary region, so that the semiconductor wafer 100 may not include any functional circuitry located outside the sealing ring 175. For example, the functional circuitry in each first semiconductor device region 101 may be electrically isolated from each other.

[0145] Additionally, multiple intermediate regions 102 are disposed between adjacent first semiconductor device regions 101, such as between adjacent sealing rings 175. In one embodiment, an intermediate region 102 may be a region without an active circuit system, although some structures (e.g., test structures) may still be formed within the intermediate region 102. In some embodiments, some of the intermediate regions 102 may serve as dicing regions and may subsequently undergo a singulation process, while other intermediate regions 102, other than those serving as dicing regions, remain intact in the diced die. Furthermore, in one embodiment, the intermediate region 102 may be defined by forming multiple sealing rings 175. In one embodiment, multiple sealing rings 175 are formed within multiple first semiconductor device regions 101.

[0146] Multiple first metallization layer via openings 151 may be formed on the front side of the first metallization layer 105 to prepare for the fabrication of multiple first metallization layer vias 201 (not in the first metallization layer 105). Figure 1 As shown in the text, but Figure 2 (As shown in the diagram). In one embodiment, the first metallization layer through-hole 151 may be formed by first applying and patterning photoresist on the front side of the first metallization layer 105. The photoresist is then used to etch the dielectric material 153 in the first alternating layer to form the first metallization layer through-hole 151. The dielectric material 153 in the first alternating layer may be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. According to some embodiments of this disclosure, the etching stops on the first conductive structure 155 of the first metallization layer 105, such that the first conductive structure 155 of the first metallization layer 105 is exposed through the first metallization layer through-hole 151 in the first metallization layer 105.

[0147] Now for reference Figure 2 The first metallization layer vias 151 can be filled to form a plurality of first metallization layer vias 201, and a first wafer bonding layer 209 can be formed over the first metallization layer 105 on the first substrate 103. In some embodiments, after exposing the first conductive structure 155 of the first metallization layer 105, the first metallization layer vias 201 can be formed to be in physical and electrical contact with the first conductive structure 155 in the first metallization layer 105. In some embodiments, the first metallization layer vias 201 may include a barrier layer, a seed layer, a fill metal, or a combination thereof (not shown separately). For example, the barrier layer may be a blanket layer deposited over the first metallization layer 105. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The seed layer can be a conductive material (e.g., copper) and, depending on the required material, can be a blanket layer deposited over the barrier layer using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or similar methods. The filler metal can be a conductor such as copper or a copper alloy and can be deposited over the seed layer using plating processes such as electrical plating or electroless plating to fill or overfill the opening. After the filler metal has been deposited, excess material in the filler metal, seed layer, and barrier layer can be removed from the outside of the opening using planarization processes such as chemical mechanical polishing.

[0148] In one embodiment, the first wafer bonding layer 209 can be used for hybrid bonding (also known as dielectric-to-dielectric and metal-to-metal bonding) or fusion bonding (also known as oxide-to-oxide bonding). According to some embodiments, the first wafer bonding layer 209 is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, etc. The first wafer bonding layer 209 can be deposited to a thickness between about 1 nm and about 1000 nm (e.g., about 5 nm) using any suitable method such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDP-CVD), PVD, or the like. However, any suitable material, process, and thickness can also be used.

[0149] After forming the first wafer bonding layer 209, a plurality of bond openings for preparing to manufacture a plurality of first conductive bond pads 207 can be formed within the first wafer bonding layer 209. In one embodiment, the bond openings can be formed first by applying and patterning photoresist on the top surface of the first wafer bonding layer 209. The photoresist is then used to etch the first wafer bonding layer 209 to form the bond openings. The first wafer bonding layer 209 can be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. According to some embodiments of this disclosure, the etching stops above the first metallization layer via 201 of the first metallization layer 105, such that the first metallization layer 105 is exposed through the bond openings in the first wafer bonding layer 209.

[0150] After the first metallization layer via 201 is exposed, the first conductive bonding pad 207 can be formed as a physical and electrical contact with the first metallization layer via 201. In one embodiment, the first conductive bonding pad 207 may include an optional barrier layer, an optional seed layer, a filler metal, or a combination thereof (not shown separately). For example, the optional barrier layer may be a blanket layer deposited over the first metallization layer 105. The optional barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The optional seed layer may be a conductive material such as copper, and may be a blanket layer deposited over the optional barrier layer using a process such as sputtering, vapor deposition, or plasma-enhanced chemical vapor deposition (PECVD), or similar methods, depending on the desired material. The filler metal may be a conductor such as copper or a copper alloy, and may be deposited over the optional seed layer to fill or overfill the bonding opening by a plating process such as electroplating or electroless plating. After the filler metal has been deposited, excess material of the filler metal, optional seed layer, and optional barrier layer can be removed from the outside of the bonding opening by a planarization process (e.g., chemical mechanical polishing). Although a single damascene process for forming the first conductive bonding pad 207 and the first metallization layer through-hole 201 has been described, any suitable method, such as a dual damascene process, can also be used.

[0151] However, the above embodiments (where the first wafer bonding layer 209 is formed and patterned, and the first conductive bonding pad 207 is electroplated within the bonding opening prior to planarization) are intended to be illustrative and not to limit the embodiments. Rather, the first wafer bonding layer 209 and the first conductive bonding pad 207 can be formed using any suitable method. In other embodiments, for example, photolithographic patterning and plating processes can be used to first form the first conductive bonding pad 207, followed by using a dielectric material to gap-fill the area around the first conductive bonding pad 207, and then planarizing using a planarization process. Any such manufacturing process is fully intended to be included within the scope of the embodiments.

[0152] refer to Figure 3 The process involves bonding the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 to the first conductive bonding pad 207 and the first wafer bonding layer 209. In one embodiment, each of the first semiconductor die 313 and the second semiconductor die 315 can be a system-on-a-chip device, such as a logic device, designed to operate in conjunction with the first semiconductor device region 101 (e.g., a wide I / O DRAM device). However, the first semiconductor die 313 and the second semiconductor die 315 can utilize any suitable function, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, or the like.

[0153] In one embodiment, the first semiconductor die 313 and the second semiconductor die 315 may each have a second substrate 317, a second active device 301, a second metallization layer 319, a plurality of second metallization layer vias 307, a second wafer bonding layer 321, and a plurality of second conductive bonding pads 323. In one embodiment, the second metallization layer 319 includes a plurality of second alternating layers of a plurality of second conductive structures 305 and a dielectric 303. In one embodiment, the second substrate 317, the second active device 301, the second metallization layer 319, the second metallization layer vias 307, the second wafer bonding layer 321, and the second conductive bonding pads 323 may be similar to the first substrate 103, the first active device 107, the first metallization layer 105, the first metallization layer vias 201, the first wafer bonding layer 209, and the first conductive bonding pads 207 described above, respectively. However, in other embodiments, these structures may be formed using different processes and different materials.

[0154] After the first semiconductor die 313 and the second semiconductor die 315 are prepared, they are bonded to the first semiconductor device region 101 using, for example, metal-to-metal and oxide-to-oxide bonding. In one embodiment, the surfaces of the first semiconductor device region 101 (e.g., the first wafer bonding layer 209 and the first conductive bonding pad 207) and the surfaces of the first semiconductor die 313 and the second semiconductor die 315 (e.g., the second wafer bonding layer 321 and the second conductive bonding pad 323) may be activated first. As an example, the activation of the top surfaces of the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 may include dry processing, wet processing, plasma processing, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, or a combination thereof. In embodiments using wet processing, for example, RCA cleaning may be used. In another embodiment, the activation process may include other types of processing. The activation process assists in the hybrid bonding of the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315.

[0155] Following the activation process, the first semiconductor die 313 and the second semiconductor die 315 can be placed together in contact with the first semiconductor device region 101. In specific embodiments using metal-to-metal and oxide-to-oxide bonding, the first conductive bonding pad 207 and the second conductive bonding pad 323 are placed in physical contact, while the first wafer bonding layer 209 and the second wafer bonding layer 321 are placed in physical contact. As the activation process chemically modifies the aforementioned surfaces, the bonding process between the materials begins at physical contact.

[0156] After the physical contact bonding process begins, the bonding can be strengthened by heat treatment of the components. In one embodiment, the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 can withstand temperatures between about 200°C and about 400°C to enhance the bonding between the first wafer bonding layer 209 and the second wafer bonding layer 321. Then, the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 can be subjected to temperatures equal to or higher than the eutectic point of the materials of the first conductive bonding pad 207 and the second conductive bonding pad 323. In this way, the fusion of the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 forms a hybrid-bonded device.

[0157] Furthermore, while specific processes have been described to initiate and enhance metal-to-metal and oxide-to-oxide bonding between the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315, these descriptions are intended to be illustrative and not to limit the embodiments. Instead, baking, annealing, pressing, or other bonding processes, or any suitable bonding process or combination thereof, may be utilized. All such processes are intended to be included within the scope of the embodiments.

[0158] Additionally, while metal-to-metal and oxide-to-oxide bonding have been described as one method for bonding the first semiconductor device region 101 to the first semiconductor die 313 and the second semiconductor die 315, this is intended to be illustrative only and not to limit the embodiments. Conversely, any suitable bonding method may be used, such as solder bonding using a ball grid array. Any suitable method for bonding the first semiconductor device region 101 to the first semiconductor die 313 and the second semiconductor die 315 may be utilized.

[0159] Furthermore, in one embodiment, the first local interconnect die 350 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) includes a first interconnect substrate 351 supporting a first interconnect structure 353, the first interconnect structure 353 comprising a plurality of first interconnect metallization layers 355 (e.g., wires, vias, and conductive pads) located within one or more first interconnect dielectric layers 357. The first interconnect metallization layers 355 and the first interconnect dielectric layers 357 may be formed and formed of similar materials, respectively, in a manner similar to that discussed with respect to the first conductive structure 155 of the first metallization layer 105 and the dielectric material 153 in the first alternating layer. In one embodiment, the first interconnect substrate 351 may be formed of silicon, such as bulk silicon. In one embodiment, the first interconnect substrate 351 may be formed in a manner similar to that of the first substrate 103 and made of a material similar to that of the first substrate 103.

[0160] In one embodiment, in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207 respectively, one of the plurality of first interconnect conductive pads 375 in the first interconnect metallization pattern 355, together with one of the first interconnect dielectric layers 357, can be used to bond the first local interconnect die 350 to the first wafer bonding layer 209.

[0161] In one embodiment, a first local interconnect die 350 electrically couples a functional metallization pattern to individual first semiconductor device regions 101. Furthermore, in one embodiment, a first semiconductor die 313 is electrically coupled to a functional metallization pattern of one of a plurality of first semiconductor device regions 101, and a second semiconductor die 315 is electrically coupled to a functional metallization pattern of another plurality of first semiconductor device regions 101. In one embodiment, the first semiconductor die 313 can be electrically coupled to the second semiconductor die 315 via the first local interconnect die 350, which is electrically coupled to the first semiconductor device regions 101 of the first semiconductor die 313 and the second semiconductor die 315, respectively.

[0162] refer to Figure 4 The first semiconductor die 313, the second semiconductor die 315, the first local interconnect die 350, and the first semiconductor device region 101 can be encapsulated by a first encapsulant 401. In one embodiment, the encapsulation can be performed in a molding device, which may include a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion is lowered to be adjacent to the bottom molding portion, molding cavities can be formed for the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350.

[0163] During the encapsulation process, the top molding portion can be placed adjacent to the bottom molding portion to enclose the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first partial interconnect die 350 within the molding cavity. After encapsulation, the top and bottom molding portions form an hermetically tight seal to control the inflow and outflow of gas from the molding cavity. After sealing, the first encapsulator 401 can be placed into the molding cavity.

[0164] The first encapsulant 401 can be an epoxy or molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyether sulfone (PES), heat-resistant crystal resin, or combinations thereof. The first encapsulant 401 can be placed in the molding cavity before the alignment of the top and bottom molding portions, or it can be injected into the molding cavity through an injection port using compression molding, transfer molding, or similar methods.

[0165] After the first encapsulant 401 is placed into the molding cavity, thereby encapsulating the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350, the first encapsulant 401 can be cured to achieve optimal protection by hardening the first encapsulant 401. While the exact curing process depends at least in part on the specific material selected for the first encapsulant 401, in embodiments where the molding compound is selected as the first encapsulant 401, the curing process can be performed, for example, by heating the first encapsulant 401 to between approximately 100°C and approximately 200°C, for example, approximately 125°C for approximately 60 seconds to approximately 3000 seconds (e.g., approximately 600 seconds). Additionally, an initiator and / or catalyst may be included within the first encapsulant 401 to better control the curing process.

[0166] However, as those skilled in the art will recognize, the curing process described above is merely exemplary and is not intended to limit the current embodiments. Other curing processes may also be used, such as irradiation or even allowing the first encapsulation 401 to cure at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0167] Figure 4The thinning of the first encapsulation 401 is further illustrated to expose the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 for further processing. Thinning can be performed, for example, using mechanical grinding, chemical methods, or chemical mechanical polishing (CMP) processes, wherein a chemical etchant and a polishing agent react and grind away the first encapsulation 401 to expose the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350, and the first encapsulation 401 has a thickness between approximately 100 μm and approximately 150 μm. Therefore, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 can have flat surfaces coplanar with the first encapsulation 401. In another embodiment, grinding can be omitted. For example, if the first semiconductor die 313 and the second semiconductor die 315 have already been exposed after encapsulation, grinding can be omitted.

[0168] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process can be used to thin the first encapsulation 401. For example, a series of chemical etching processes can be used. The described process and any other suitable process can be used to planarize the first encapsulation 401, and all such processes are fully intended to be included within the scope of the embodiments.

[0169] refer to Figure 5 The image shows the placement of a first carrier substrate 500. In one embodiment, the first carrier substrate 500 comprises, for example, a silicon-based material, such as silicon, glass, etc. In one embodiment, the first carrier substrate 500 is planar to accommodate the attachment of a first semiconductor die 313 and a second semiconductor die 315, which can be attached by a bonding process or by using an adhesive layer (not shown separately).

[0170] In one embodiment, a first carrier substrate 500 is bonded to a first semiconductor die 313 and a second semiconductor die 315. In this embodiment, a first bonding layer 501 may be formed on the flat surfaces of the first semiconductor die 313 and the second semiconductor die 315. In one embodiment, the first bonding layer 501 may comprise an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the first bonding layer 501.

[0171] After the formation of the first bonding layer 501, the first carrier substrate 500 can be bonded to the first bonding layer 501 through a second bonding layer 503. In one embodiment, the second bonding layer 503 is formed on the first carrier substrate 500 in a similar manner and from a similar material as the first bonding layer 501. According to some embodiments, the first carrier substrate 500 includes silicon, etc. In one embodiment, the second bonding layer 503 is bonded to the first bonding layer 501 through a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). In one embodiment, the dielectric-to-dielectric bonding process may include applying a surface treatment to one or more of the first bonding layer 501 and the second bonding layer 503. The surface treatment may include a plasma treatment, which may be applied to the exposed surfaces of the respective bonding layers. The plasma treatment may be performed in a vacuum environment. Following plasma treatment, surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like), which may be applied to one or more of the first bonding layer 501 and the second bonding layer 503. Next, the first carrier substrate 500 is aligned with the first bonding layer 501 and pressed together to initiate a pre-bonding of the first carrier substrate 500 to the first bonding layer 501 on the first semiconductor die 313 and the second semiconductor die 315. This pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be performed, for example, by heating the first bonding layer 501 and the second bonding layer 503 to a temperature in the range of 150°C to 500°C. This annealing process increases the bonding strength and triggers the formation of covalent bonds between the first bonding layer 501 and the second bonding layer 503. Other bonding processes, such as ambient bonding, vacuum bonding, or the like, may also be used in other embodiments.

[0172] refer to Figure 6 After attaching the first carrier substrate 500, the second side of the first substrate 103 can be thinned to expose the first substrate through-hole 111. In one embodiment, thinning of the second side of the first substrate 103 can expose the first substrate through-hole 111. The thinning of the second side of the first substrate 103 can be performed by a planarization process such as chemical mechanical polishing or etching. However, any suitable method can be used to thin the second side of the first substrate 103. In one embodiment, etching is a time-controlled anisotropic plasma etching process that forms a plurality of recesses 601 from which the first substrate through-hole 111 protrudes. In one embodiment, the recesses 601 can be formed to a sufficient depth to accommodate the thickness of the subsequently formed first passivation layer 701 (not shown in the figure). Figure 6 As shown in the text, but Figure 7 (as shown in the image).

[0173] refer to Figure 7 The diagram illustrates the formation of a first passivation film 701 over a second side of a first substrate 103. In one embodiment, the first passivation film 701 may comprise silicon oxide, silicon oxynitride, silicon nitride, etc. In one embodiment, the first passivation film 701 may be deposited via CVD, ALD, PVD, etc. After the deposition of the first passivation film 701, a planarization process may be performed to expose the top surface of the first substrate via 111.

[0174] refer to Figure 8 A first backside redistribution structure 800 is formed. The first backside redistribution structure 800 may include one or more redistribution dielectric layers 803 and corresponding one or more redistribution metallization layers 801 within the redistribution dielectric layers 803. The redistribution dielectric layers 803 may be, for example, low-dielectric-constant dielectric layers. The redistribution metallization layers 801 may include multiple vias (e.g., multiple redistribution conductive elements 805) formed between the redistribution metallization layers 801. The redistribution metallization layers 801 may be formed of a conductive material (e.g., metals, such as copper, cobalt, aluminum, gold, combinations thereof). The redistribution metallization layers 801 of the first backside redistribution structure 800 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0175] In one embodiment, a first metallization contact pad 807 is formed on top of the top dielectric layer of the first back-side redistribution wiring structure 800. The first metallization contact pad 807 can be formed in a manner similar to that of the redistribution metallization layer 801. In one embodiment, the first metallization contact pad 807 can be formed to a different thickness than the redistribution metallization layer 801. In one embodiment, a first redistribution passivation layer 809 can be formed above the top dielectric layer and above the first metallization contact pad 807. The first redistribution passivation layer 809 can be a material such as nitride, oxide, polyimide, low-temp polyimide, solder resist, or combinations thereof. Once formed, the first redistribution passivation layer 809 can be patterned (e.g., using appropriate photolithography and etching processes) to the exposed portions of the first metallization contact pad 807.

[0176] In one embodiment, a plurality of under-bump metallization (UBM) 811 are formed for external connection to a first back-side redistributed wiring structure 800. The first UBM 811 has a bump portion located above and extending along the main surface of the first redistributed passivation layer 809, and a through-hole portion extending through the first redistributed passivation layer 809 for physical and electrical coupling to the first metallized contact pad 807. The first UBM 811 may be formed of the same material as the redistributed metallization layer 801.

[0177] In one embodiment, a plurality of first conductive connectors 818 are formed on the metal 811 under the first bump. The first conductive connectors 818 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The first conductive connectors 818 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, titanium nitride, the like, or combinations thereof. In some embodiments, the formation of the first conductive connectors 818 may involve first forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. After the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the first conductive connectors 818 include metal pillars (e.g., copper pillars) formed through sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed above the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process. Figure 8 The resulting structure can be referred to as a first semiconductor package 850.

[0178] Subsequently, in some embodiments, the first carrier substrate 500 may be removed, and a dicing process may be performed around the periphery of the illustrated package region. However, certain regions in the intermediate region 102 may not undergo a dicing process, such as the region between the two illustrated first semiconductor device regions 101.

[0179] refer to Figure 9 The image shows a top-down cross-sectional view of the first semiconductor package 850. In one embodiment, a plurality of seal rings 175 surround the active circuitry of a plurality of first semiconductor device regions 101 and also completely cover the first semiconductor die 313 and the second semiconductor die 315, respectively. In one embodiment, a first local interconnect die 350 overlaps with the seal ring 175 defining one of the first semiconductor device regions 101, completely overlaps with the intermediate region 102, and overlaps with the seal ring 175 defining another of the first semiconductor device regions 101.

[0180] Figures 1 to 9This illustrates one specific package architecture, but other architectures are also possible. For example, Figures 10 to 19 Various intermediate steps in the manufacture of semiconductor packages according to some other embodiments are illustrated. References Figure 10 The third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) are attached to the second carrier substrate 1000. In one embodiment, each of the third semiconductor die 1001 and the fourth semiconductor die 1003 can be a system-on-a-chip device, such as a logic device. However, the third semiconductor die 1001 and the fourth semiconductor die 1003 can utilize any suitable function, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, or the like.

[0181] In one embodiment, the third semiconductor die 1001 and the fourth semiconductor die 1003 may each have a third substrate 1077, a third active device 1071, and a third metallization layer 1079, the third metallization layer 1079 comprising a plurality of third conductive structures 1081 and a plurality of third alternating layers of dielectric 1083. In one embodiment, the third substrate 1077, the third active device 1071, and the third metallization layer 1079 may be formed in a manner similar to that of the first substrate 103, the first active device 107, and the first metallization layer 105 as described above. However, in other embodiments, these structures may be formed using different processes and different materials.

[0182] In one embodiment, the front side of the third semiconductor die 1001, the front side of the fourth semiconductor die 1003, and the front side of the second local interconnect die 1005 are bonded to the second carrier substrate 1000. In this embodiment, a third bonding layer 1051 may be formed on the second carrier substrate 1000. In one embodiment, the third bonding layer 1051 may include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the third bonding layer 1051.

[0183] In one embodiment, alternating layers of dielectrics of the third metallization layer 1079 are bonded to the third bonding layer 1051 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0184] Furthermore, in one embodiment, the second local interconnect die 1005 includes a second interconnect substrate 1021 supporting a second interconnect structure 1023, the second interconnect structure 1023 including a plurality of second interconnect metallization patterns 1025 (e.g., wires, vias, and conductive pads) located in one or more second interconnect dielectric layers 1027. The second interconnect metallization patterns 1025 and the second interconnect dielectric layers 1027 may be formed and formed of similar materials in a manner similar to that discussed with respect to the first conductive structure 155 of the first metallization layer 105 and the dielectric material 153 in the first alternating layer. In one embodiment, the second interconnect substrate 1021 may be formed of silicon, such as a bulk silicon material. In one embodiment, the second interconnect substrate 1021 may be formed in a manner similar to that of the first substrate 103 and formed of a material similar to that of the first substrate 103. In one embodiment, the second interconnect dielectric layer 1027 is used to form a dielectric-to-dielectric bonding with the third bonding layer 1051 to bond the second local interconnect die 1005 to the second carrier substrate 1000.

[0185] refer to Figure 11 The third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 can be encapsulated by a second encapsulator 1101. In one embodiment, the encapsulation can be performed in a molding apparatus, which may include a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion is lowered to be adjacent to the bottom molding portion, molding cavities for the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 can be formed.

[0186] During the encapsulation process, the top molding portion can be placed adjacent to the bottom molding portion, thereby enclosing the third semiconductor die 1001, the fourth semiconductor die 1003, and the second partial interconnect die 1005 within the molding cavity. After sealing, the top and bottom molding portions can form an hermetically tight seal to control the inflow and outflow of gas from the molding cavity. After sealing, the second encapsulator 1101 can be placed within the molding cavity.

[0187] The second encapsulant 1101 can be an epoxy or molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethyl ether sulfone (PES), heat-resistant crystalline resin, or combinations thereof. The second encapsulant 1101 can be placed in the molding cavity before the alignment of the top and bottom molding portions, or it can be injected into the molding cavity through an injection port using compression molding, transfer molding, or the like.

[0188] After the second encapsulant 1101 is placed into the molding cavity, thereby encapsulating the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005, the second encapsulant 1101 can be cured to achieve optimal protection by hardening the second encapsulant 1101. While the exact curing process depends at least in part on the specific material selected for the second encapsulant 1101, in embodiments where the molding compound is selected as the second encapsulant 1101, the curing process can be performed, for example, by heating the second encapsulant 1101 to between approximately 100°C and approximately 200°C, for example, approximately 125°C for approximately 60 seconds to approximately 3000 seconds (e.g., approximately 600 seconds). Additionally, an initiator and / or catalyst may be included within the second encapsulant 1101 to better control the curing process.

[0189] However, as those skilled in the art will recognize, the curing process described above is merely exemplary and is not intended to limit the current embodiments. Other curing processes may also be used, such as irradiation or even allowing the second encapsulation 1101 to cure at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0190] Figure 11 The thinning of the second encapsulation 1101 is further illustrated to expose the back side of the third semiconductor die 1001, the back side of the fourth semiconductor die 1003, and the back side of the second local interconnect die 1005 for further processing. Thinning can be performed, for example, using mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, wherein a chemical etchant and an abrasive react and polish away the second encapsulation 1101 to expose the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005, and the second encapsulation 1101 has a thickness between approximately 100 μm and approximately 150 μm. Therefore, the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 can have flat surfaces coplanar with the second encapsulation 1101.

[0191] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process can be used to thin the second encapsulation 1101. For example, a series of chemical etching processes can be used. The described process and any other suitable process can be used to planarize the second encapsulation 1101, and all such processes are fully intended to be included within the scope of the embodiments.

[0192] refer to Figure 12 The image shows the placement of a third carrier substrate 1200. In one embodiment, the third carrier substrate 1200 comprises, for example, a silicon-based material, such as silicon, glass, etc. In one embodiment, the third carrier substrate 1200 is planar to accommodate the attachment of a third semiconductor die 1001 and a fourth semiconductor die 1003, which can be attached by a bonding process or by using an adhesive layer (not shown separately).

[0193] In one embodiment, the third carrier substrate 1200 is bonded to the back side of the third semiconductor die 1001, the back side of the fourth semiconductor die 1003, and the back side of the second local interconnect die 1005. In this embodiment, the fourth bonding layer 1201 may be formed on the planar surfaces of the third semiconductor die 1001, the fourth semiconductor die 1003, the second local interconnect die 1005, and the second encapsulation 1101. In one embodiment, the fourth bonding layer 1201 may comprise an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the fourth bonding layer 1201.

[0194] In one embodiment, the third carrier substrate 1200 can be bonded to the fourth bonding layer 1201 via a fifth bonding layer 1203. In one embodiment, the fifth bonding layer 1203 is formed on the third carrier substrate 1200 in a similar manner to the fourth bonding layer 1201 and from a similar material. According to some embodiments, the third carrier substrate 1200 includes silicon, etc. In one embodiment, the fifth bonding layer 1203 is bonded to the fourth bonding layer 1201 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0195] refer to Figure 13This shows the flipped Figure 12 The intermediate device shown illustrates a first carrier removal process 1300 for the second carrier substrate 1000. In one embodiment, the first carrier removal process 1300 may be a mechanical process (e.g., polishing), a chemical process (e.g., etching), or a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may also be used. In one embodiment, the first carrier removal process 1300 exposes the front side of the third semiconductor die 1001, the front side of the fourth semiconductor die 1003, and the front side of the second local interconnect die 1005.

[0196] refer to Figure 14 Multiple third metallization layer vias 1401 can be formed in the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005. Furthermore, Figure 14 A third wafer bonding layer 1409 and a plurality of third conductive bonding pads 1411 are shown formed on the front side of the third semiconductor die 1001, the front side of the fourth semiconductor die 1003, and the front side of the second local interconnect die 1005.

[0197] In one embodiment, the third metallization layer via 1401 may be formed in a similar manner to that described above with respect to the first metallization layer via 201 and may be formed of a similar material. The third metallization layer via 1401 may be formed as a first conductive structure 155 that makes both physical and electrical contacts to the first metallization layer 105.

[0198] In one embodiment, the third wafer bonding layer 1409 may be formed in a similar manner to that described above with respect to the first wafer bonding layer 209 and formed of a similar material. However, the third metallization layer via 1401 and the third wafer bonding layer 1409 may be formed using any suitable process and materials.

[0199] refer to Figure 15 The first semiconductor device 1501 and the second semiconductor device 1503 are attached to the third wafer bonding layer 1409. In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 may each be a system-on-a-chip device, such as a logic component. However, the first semiconductor device 1501 and the second semiconductor device 1503 may utilize any suitable function, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, or the like.

[0200] In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 may each have a first device substrate 1553, a fourth active device 1557, a first device metallization layer 1555, a plurality of first device metallization layer vias 1559, a plurality of first device substrate vias 1561, a first device bonding layer 1563, and a first device conductive bonding material 1565. In one embodiment, the first device substrate 1553 may be formed of a material similar to that of the first substrate 103. The fourth active device 1557 may be formed in a manner similar to that of the first active device 107. The first device metallization layer 1555 may be formed in a manner similar to that of the first metallization layer 105 and of a material similar to that of the first metallization layer 105. The first device metallization layer vias 1559 may be formed in a manner similar to that of the first metallization layer via 201 and of a material similar to that of the first metallization layer via 201. The first device substrate vias 1561 may be formed in a manner similar to that of the first substrate via 111 and of a similar material. The first device bonding layer 1563 may be formed of a material similar to the first wafer bonding layer 209 and may be formed using a process similar to that of the first wafer bonding layer 209. Similarly, the first device conductive bonding material 1565 may be formed of a material similar to the first conductive bonding pad 207 and may be formed using a process similar to that of the first conductive bonding pad 207. However, any suitable materials and processes may also be used to form the structures of the first semiconductor device 1501 and the second semiconductor device 1503.

[0201] In one embodiment, the first semiconductor device 1501 and the second semiconductor device can be formed as a portion of a wafer, similar to... Figure 1 The semiconductor wafer 100 described herein is formed. Then, a first semiconductor device 1501 and a second semiconductor device 1503 can be formed by dividing the wafer into individual semiconductor devices along a dicing path (not shown separately) defined by a sealing ring (not shown separately) (as shown).

[0202] In one embodiment, the front side of the first semiconductor device 1501 and the front side of the second semiconductor device 1503 may be attached to the front side of the third semiconductor die 1001, the front side of the fourth semiconductor die 1003, and the front side of the second local interconnect die 1005. In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 may be attached by a bonding process or by using an adhesive layer (not shown separately).

[0203] In one embodiment, the first semiconductor device 1501 can be bonded to the third semiconductor die 1001 and the second local interconnect die 1005 by bonding the first device bonding layer 1563 and the first device conductive bonding material 1565 of the first semiconductor device 1501 to the third wafer bonding layer 1409 and the third conductive bonding pad 1411, respectively. In one embodiment, the first device bonding layer 1563 and the first device conductive bonding material 1565 can be bonded to the third wafer bonding layer 1409 and the third conductive bonding pad 1411 in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the first semiconductor device 1501 to the third wafer bonding layer 1409.

[0204] In one embodiment, the second semiconductor device 1503 can be bonded to the fourth semiconductor die 1003 and the second local interconnect die 1005 by respectively bonding the first device bonding layer 1563 and the first device conductive bonding material 1565 to the third wafer bonding layer 1409 and the third conductive bonding pad 1411. In one embodiment, the first device bonding layer 1563 and the first device conductive bonding material 1565 can be bonded to the third wafer bonding layer 1409 and the third conductive bonding pad 1411 in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the second semiconductor device 1503 to the third wafer bonding layer 1409.

[0205] In one embodiment, a second local interconnect die 1005 electrically couples a first semiconductor device 1501 to a second semiconductor device 1503. Furthermore, in one embodiment, a third semiconductor die 1001 is electrically coupled to the first semiconductor device 1501 and a fourth semiconductor die 1003 is electrically coupled to the second semiconductor device 1503. In one embodiment, the third semiconductor die 1001 can be electrically coupled to the fourth semiconductor die 1003 via a second local interconnect die 1005 electrically coupled between the first semiconductor device 1501 electrically coupled to the third semiconductor die 1001 and the second semiconductor device 1503 electrically coupled to the fourth semiconductor die 1003.

[0206] refer to Figure 16 The first semiconductor device 1501 and the second semiconductor device 1503 may be encapsulated by a third encapsulator 1601. In one embodiment, the third encapsulator 1601 may be formed by a process similar to that described for the second encapsulator 1101. However, any suitable process and materials may be used for the third encapsulator 1601.

[0207] Furthermore, after encapsulating the first semiconductor device 1501 and the second semiconductor device 1503 with the third encapsulator 1601, the back side of the third encapsulator 1601, the back side of the first semiconductor device 1501, and the back side of the second semiconductor device 1503 can be thinned, thereby exposing the top surface of the first device substrate through-hole 1561 of the first semiconductor device 1501 and the top surface of the first device substrate through-hole 1561 of the second semiconductor device 1503. Thinning can be performed, for example, by mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, in which the third encapsulator 1601 is removed by reacting a chemical etchant and an abrasive, and portions of the first device substrate 1553 of both the first semiconductor device 1501 and the second semiconductor device 1503 are removed. Therefore, the back side of the first semiconductor device 1501, the back side of the second semiconductor device 1503, and the third encapsulator 1601 can have flat surfaces.

[0208] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process can be used to thin the third encapsulation 1601 and the first device substrate 1553. For example, a series of chemical etching processes can be used. The described process and any other suitable process can be used to planarize the third encapsulation 1601 and the first device substrate 1553, and all such processes are fully intended to be included within the scope of the embodiments.

[0209] refer to Figure 17 The diagram illustrates the formation of a second passivation film 1701 on the back side of a first semiconductor device 1501 and on the back side of a second semiconductor device 1503. In one embodiment, an etch-back process is performed on the first device substrate 1553 of the first semiconductor device 1501 and the first device substrate 1553 of the second semiconductor device 1503, respectively. The etch-back process can be a time-controlled anisotropic plasma etching process that forms a plurality of recesses (not shown separately) within the first device substrate 1553 of the first semiconductor device 1501 and the first device substrate 1553 of the second semiconductor device 1503, such that a first device substrate through-hole 1561 protrudes from the first device substrate 1553. In one embodiment, the recesses can be formed to a sufficient depth to accommodate the thickness of the second passivation film 1701.

[0210] In one embodiment, the second passivation film 1701 may include silicon oxide, silicon oxynitride, silicon nitride, etc. In one embodiment, the second passivation film 1701 may be deposited by CVD, ALD, PVD, etc. After the deposition of the second passivation film 1701, a planarization process may be performed to expose the top surface of the first device substrate via 1561.

[0211] refer to Figure 18 A first backside redistribution circuit structure 800 is formed over the back side of the first semiconductor device 1501 and the back side of the second semiconductor device 1503. In one embodiment, the first backside redistribution circuit structure 800 is formed in a similar manner and with similar materials as described above, but is formed over the first semiconductor device 1501 and the second semiconductor device 1503. Furthermore, in one embodiment, the first metallized contact pad 807, the first redistribution passivation layer 809, the plurality of first bump under-metals 811, and the plurality of first conductive connectors 818 are formed over the first backside redistribution circuit structure 800 in a similar manner and with similar materials as described above. Figure 18 The resulting structure can be referred to as the second semiconductor package 1850.

[0212] refer to Figure 19 The image shows a top-down cross-sectional view of a second semiconductor package 1850. In one embodiment, a third encapsulation 1601 in the top-down cross-sectional view defines the periphery of the second semiconductor package 1850. In one embodiment, a first semiconductor device 1501 completely covers the third semiconductor die 1001 and covers a first portion of the second local interconnect die 1005. In one embodiment, a second semiconductor device 1503 completely covers the fourth semiconductor die 1003 and covers a second portion of the second local interconnect die 1005.

[0213] Figures 10 to 19 This illustrates one specific package architecture, but other architectures are also possible. For example, Figures 20 to 31 Various intermediate steps in the manufacture of semiconductor packages according to some other embodiments are illustrated. References Figure 20 The third semiconductor device 2001 and the fourth semiconductor device 2003 are attached to the fourth carrier substrate 2000. In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 may each be a system-on-a-chip device, such as a logic component. However, the third semiconductor device 2001 and the fourth semiconductor device 2003 may utilize any suitable function, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, or the like.

[0214] In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 may each include a second device substrate 2053, a fourth active device 2057, a second device metallization layer 2055, and a plurality of second device substrate vias 2061. In one embodiment, the second device substrate 2053 may be formed of a material similar to that of the first substrate 103. The fourth active device 2057 may be formed in a manner similar to that of the first active device 107. The second device metallization layer 2055 may be formed in a manner similar to that of the first metallization layer 105 and of a material similar to that of the first metallization layer 105. The second device substrate vias 2061 may be formed in a manner similar to that of the first substrate vias 111 and of a similar material. However, any suitable materials and processes may also be used to form the structures of the third semiconductor device 2001 and the fourth semiconductor device 2003.

[0215] In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 may be formed as portions of a wafer, similar to... Figure 1 The semiconductor wafer 100 described herein is formed. Then, a third semiconductor device 2001 and a fourth semiconductor device 2003 can be formed by dividing the wafer into individual semiconductor devices along a dicing path (not shown separately) defined by a sealing ring (not shown separately) (as shown).

[0216] In one embodiment, the fourth carrier substrate 2000 comprises, for example, a silicon-based material, such as silicon, glass, etc. In one embodiment, the fourth carrier substrate 2000 is planar to accommodate the attachment of the third semiconductor device 2001 and the fourth semiconductor device 2003, which may be attached by a bonding process or by using an adhesive layer (not shown separately).

[0217] In one embodiment, the fourth carrier substrate 2000 is bonded to the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003. In this embodiment, a sixth bonding layer 2071 may be formed over the second device metallization layer 2055 of the third semiconductor device 2001 and the second device metallization layer 2055 of the fourth semiconductor device 2003. In one embodiment, the sixth bonding layer 2071 may include oxides, such as silicon oxide, silicon oxynitride, etc., or combinations thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or combinations thereof. Other oxide materials formed by any acceptable process may also be used to form the sixth bonding layer 2071.

[0218] The fourth carrier substrate 2000 can be bonded to the sixth bonding layer 2071 of the third semiconductor device 2001 and the sixth bonding layer 2071 of the fourth semiconductor device 2003 via its seventh bonding layer 2073. In one embodiment, the seventh bonding layer 2073 is formed on the fourth carrier substrate 2000 in a similar manner to the fourth bonding layer 1201 and from a similar material. According to some embodiments, the fourth carrier substrate 2000 includes silicon, etc. In one embodiment, the seventh bonding layer 2073 is bonded to the sixth bonding layer 2071 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0219] refer to Figure 21 The third semiconductor device 2001 and the fourth semiconductor device 2003 may be packaged in a fourth encapsulation 2101. In one embodiment, the fourth encapsulation 2101 may be formed by a process similar to that of the third encapsulation 1601 described above. However, any suitable process and materials may be used for the fourth encapsulation 2101.

[0220] Furthermore, after encapsulating the third semiconductor device 2001 and the fourth semiconductor device 2003 with the fourth encapsulator 2101, the back side of the fourth encapsulator 2101, the back side of the third semiconductor device 2001, and the back side of the fourth semiconductor device 2003 can be thinned, thereby exposing the top surface of the second device substrate through-hole 2061 of the third semiconductor device 2001 and the top surface of the second device substrate through-hole 2061 of the fourth semiconductor device 2003. Thinning can be performed, for example, by mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, in which the fourth encapsulator 2101 is removed by reacting a chemical etchant and an abrasive, and portions of the second device substrate 2053 of both the third semiconductor device 2001 and the fourth semiconductor device 2003 are removed. Therefore, the back side of the third semiconductor device 2001, the back side of the fourth semiconductor device 2003, and the fourth encapsulator 2101 can have flat surfaces.

[0221] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process can be used to thin the fourth encapsulation 2101 and the second device substrate 2053. For example, a series of chemical etching processes can be used. The described process and any other suitable process can be used to planarize the fourth encapsulation 2101 and the second device substrate 2053, and all such processes are fully intended to be included within the scope of the embodiments.

[0222] refer to Figure 22A fifth carrier substrate 2200 is attached to the back side of the third semiconductor device 2001 and the back side of the fourth semiconductor device 2003. In one embodiment, the back sides of the third semiconductor device 2001 and the back sides of the fourth semiconductor device 2003 are bonded to the fifth carrier substrate 2200. In this embodiment, an eighth bonding layer 2251 may be formed on the fifth carrier substrate 2200. In one embodiment, the fifth carrier substrate 2200 comprises, for example, a silicon-based material, such as silicon, glass, etc. In one embodiment, the eighth bonding layer 2251 may comprise an oxide, such as silicon oxide, silicon oxynitride, etc., or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the eighth bonding layer 2251. Furthermore, the ninth bonding layer 2253 may be formed on the flat surfaces of the third semiconductor device 2001, the fourth semiconductor device 2003, and the fourth encapsulation 2101. In one embodiment, the ninth bonding layer 2253 may comprise an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed using any acceptable process may be used to form the ninth bonding layer 2253.

[0223] In one embodiment, the eighth bonding layer 2251 is bonded to the ninth bonding layer 2253 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0224] refer to Figure 23 ,Will Figure 22 The intermediate device shown flips over and performs a second carrier removal process 2300 on the fourth carrier substrate 2000. In one embodiment, the second carrier removal process 2300 may be a mechanical process (e.g., polishing), a chemical process (e.g., etching), or a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may also be used. In one embodiment, the second carrier removal process 2300 exposes the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003.

[0225] refer to Figure 24Multiple second device metallization layer vias 2401 can be formed in the third semiconductor device 2001 and the fourth semiconductor device 2003. Furthermore, Figure 24 A fourth wafer bonding layer 2403 is shown, and a fourth conductive bonding pad 2405 is formed on the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003.

[0226] In one embodiment, the second device metallization layer through-hole 2401 may be formed in a similar manner to that described above with respect to the first device metallization layer through-hole 201 and from a similar material. The second device metallization layer through-hole 2401 may be formed as a physical contact and an electrical contact with the second device metallization layer 2055.

[0227] In one embodiment, the fourth wafer bonding layer 2403 may be formed in a similar manner and from a similar material as described above with respect to the first wafer bonding layer 209, and the fourth conductive bonding pad 2405 may be formed in a similar manner and from a similar material as described above with respect to the first conductive bonding pad 207. However, the second device metallization layer via 2401, the fourth wafer bonding layer 2403, and the fourth conductive bonding pad 2405 may also be formed using any suitable process and materials.

[0228] Now, for reference Figure 25 The fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) are bonded to a fourth conductive bonding pad 2405 and a fourth wafer bonding layer 2403. In one embodiment, each of the fifth semiconductor die 2513 and the sixth semiconductor die 2515 can be a system-on-a-chip device, such as a logic device. However, the fifth semiconductor die 2513 and the sixth semiconductor die 2515 can utilize any suitable function, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, or the like.

[0229] In one embodiment, the fifth semiconductor die 2513 and the sixth semiconductor die 2515 may each have a fourth substrate 2517, a fifth active device 2501, a fourth metallization layer 2519, a plurality of fourth metallization layer vias 2507, a fifth wafer bonding layer 2521, and a plurality of fifth conductive bonding pads 2523. In one embodiment, the fourth metallization layer 2519 includes a plurality of fourth alternating layers of dielectric 2503 and a plurality of fourth conductive structures 2505. In one embodiment, the fourth substrate 2517, the fifth active device 2501, the fourth metallization layer 2519, the fourth metallization layer vias 2507, the fifth wafer bonding layer 2521, and the fifth conductive bonding pads 2523 may be similar to the first substrate 103, the first active device 107, the first metallization layer 105, the first metallization layer via 201, the first wafer bonding layer 209, and the first conductive bonding pad 207 described above, respectively. However, in other embodiments, these structures may be formed using different processes and different materials.

[0230] Furthermore, in one embodiment, the third local interconnect die 2550 includes a third interconnect substrate 2571 supporting a third interconnect structure 2573. The third interconnect substrate 2571 includes a plurality of third interconnect metallization patterns 2575 (e.g., wires, vias, and conductive pads) located within one or more third interconnect dielectric layers 2557. The third interconnect metallization patterns 2575 and the third interconnect dielectric layers 2557 can be formed and formed of similar materials, respectively, in a manner similar to that discussed with respect to the first conductive structure 155 of the first metallization layer 105 and the dielectric material 153 in the first alternating layer. In one embodiment, the third interconnect substrate 2571 can be formed of silicon, such as a bulk silicon material. In one embodiment, the third interconnect substrate 2571 can be formed in a manner similar to that of the first substrate 103 and formed of a material similar to that of the first substrate 103.

[0231] In one embodiment, a fifth semiconductor die 2513 is bonded to a third semiconductor device 2001. The fifth semiconductor die 2513 can be bonded to the third semiconductor device 2001 by bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405, respectively, on the front side of the third semiconductor device 2001. In one embodiment, bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405 can be performed in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403.

[0232] In one embodiment, a sixth semiconductor die 2515 is bonded to a fourth semiconductor device 2003. The sixth semiconductor die 2515 can be bonded to the fourth semiconductor device 2003 by bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405, respectively, on the front side of the fourth semiconductor device 2003. In one embodiment, bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405 can be performed in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403.

[0233] Furthermore, in one embodiment, in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207 respectively, a plurality of conductive pads in the third interconnect metallization pattern 2575 and one of the third interconnect dielectric layers 2557 can be used to bond the third local interconnect die 2550 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405.

[0234] In one embodiment, a third local interconnect die 2550 electrically couples a third semiconductor device 2001 to a fourth semiconductor device 2003. Furthermore, in one embodiment, a fifth semiconductor die 2513 is electrically coupled to the third semiconductor device 2001, and a sixth semiconductor die 2515 is electrically coupled to the fourth semiconductor device 2003. In one embodiment, the third semiconductor device 2001 can be electrically coupled to the fourth semiconductor device 2003 via a third local interconnect die 2550 electrically coupled between the third semiconductor device 2001 electrically coupled to the fifth semiconductor die 2513 and the fourth semiconductor device 2003 electrically coupled to the sixth semiconductor die 2515.

[0235] refer to Figure 26 The fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 may be encapsulated by a fifth encapsulator 2601. In one embodiment, the fifth encapsulator 2601 may be formed by a process similar to that of the third encapsulator 1601 described above. However, any suitable process and materials may be used for the fifth encapsulator 2601.

[0236] Furthermore, after encapsulating the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 with the fifth encapsulation 2601, the fifth encapsulation 2601 can be thinned. In one embodiment, the thinning of the fifth encapsulation 2601 exposes the back side of the fifth semiconductor die 2513, the back side of the sixth semiconductor die 2515, and the back side of the third local interconnect die 2550 for further processing. Thinning can be performed, for example, using mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, wherein the fifth encapsulation 2601 is removed by reacting a chemical etchant and an abrasive, so that the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 can have flat surfaces, which are also coplanar with the fifth encapsulation 2601.

[0237] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process can be used to thin the fifth encapsulation 2601. For example, a series of chemical etching processes can be used. The described process and any other suitable process can be used to planarize the fifth encapsulation 2601, and all such processes are fully intended to be included within the scope of the embodiments.

[0238] refer to Figure 27A sixth carrier substrate 2700 is attached to the back side of a fifth semiconductor die 2513, the back side of a sixth semiconductor die 2515, the back side of a third local interconnect die 2550, and a fifth encapsulation 2601. In one embodiment, the back side of the fifth semiconductor die 2513, the back side of the sixth semiconductor die 2515, the back side of the third local interconnect die 2550, and the fifth encapsulation 2601 are bonded to the sixth carrier substrate 2700. In the embodiment, a tenth bonding layer 2751 may be formed on the sixth carrier substrate 2700. In one embodiment, the tenth bonding layer 2751 may include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the tenth bonding layer 2751. Furthermore, the eleventh bonding layer 2753 may be formed on the planar surfaces of the fifth semiconductor die 2513, the sixth semiconductor die 2515, the third local interconnect die 2550, and the fifth encapsulation 2601. In one embodiment, the eleventh bonding layer 2753 may comprise an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into an oxide), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the eleventh bonding layer 2753.

[0239] In one embodiment, the tenth bonding layer 2751 is bonded to the eleventh bonding layer 2753 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0240] refer to Figure 28 ,Will Figure 27 The intermediate device shown flips over and performs a third carrier removal process 2800 on the fifth carrier substrate 2200. In one embodiment, the third carrier removal process 2800 may be a mechanical process (e.g., polishing), a chemical process (e.g., etching), or a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may also be used. In one embodiment, the third carrier removal process 2800 exposes the back side of the third semiconductor device 2001 and the back side of the fourth semiconductor device 2003.

[0241] refer to Figure 29 A third passivation film 2901 is formed on the back side of the third semiconductor device 2001 and the back side of the fourth semiconductor device 2003. In one embodiment, an etch-back process is performed on the second device substrate 2053 of the third semiconductor device 2001 and the second device substrate 2053 of the fourth semiconductor device 2003, respectively. The etch-back process can be a time-controlled anisotropic plasma etching process that forms multiple recesses (not shown separately) in the second device substrate 2053 of the third semiconductor device 2001 and the second device substrate 2053 of the fourth semiconductor device 2003, such that a second device substrate via 2061 protrudes from the second device substrate 2053. In one embodiment, the recesses can be formed to a sufficient depth to accommodate the thickness of the third passivation film 2901.

[0242] In one embodiment, the third passivation film 2901 may include silicon oxide, silicon oxynitride, silicon nitride, etc. In one embodiment, the third passivation film 2901 may be deposited by CVD, ALD, PVD, etc. After the deposition of the third passivation film 2901, a planarization process may be performed to expose the top surface of the second device substrate via 2061.

[0243] refer to Figure 30 A first backside redistribution circuit structure 800 is formed on the back side of the third semiconductor device 2001 and the back side of the fourth semiconductor device 2003. In one embodiment, the first backside redistribution circuit structure 800 is formed in a similar manner and with similar materials, but on the third semiconductor device 2001 and the fourth semiconductor device 2003. Furthermore, in one embodiment, a plurality of first metallized contact pads 807, a first redistribution passivation layer 809, a plurality of first bump under-metals 811, and a plurality of first conductive connectors 818 are formed on the first backside redistribution circuit structure 800 in a similar manner and with similar materials. Figure 30 The resulting structure shown can be referred to as a third semiconductor package 3050.

[0244] refer to Figure 31 The image shows a top-down cross-sectional view of a third semiconductor package 3050. In one embodiment, a fourth encapsulation 2101 in the top-down cross-sectional view defines the periphery of the third semiconductor package 3050. In one embodiment, a third semiconductor device 2001 completely covers a fifth semiconductor die 2513 and a first portion of a third local interconnect die 2550. In one embodiment, a fourth semiconductor device 2003 completely covers a sixth semiconductor die 2515 and a second portion of a third local interconnect die 2550.

[0245] refer to Figure 32A The first semiconductor package 850 is shown having a plurality of TSV guard rings 3201 around a plurality of first substrate vias 111, and a deep trench capacitor (DTC) 3203 may optionally be formed in the first local interconnect die 350. In one embodiment, the TSV guard rings 3201 may be formed by a metal inlay process. The TSV guard rings 3201 may be formed in the first metallization layer 105 and surround the first substrate vias 111 in the first metallization layer 105 in a top-down view (see, for example...). Figure 32B In one embodiment, the TSV guard ring 3201 does not extend into the first substrate 103. The TSV guard ring 3201 may comprise a metal, such as copper. However, the TSV guard ring 3201 may also be formed using any suitable method and material.

[0246] In one embodiment, the TSV guard ring 3201 can reduce leakage current and provide electrical isolation between the first substrate via 111 and other structures in the first metallization layer 105. Additionally, during the fabrication and operation of the first semiconductor package 850, the first substrate via 111 may introduce mechanical stress, and the TSV guard ring 3201 can provide stress relief.

[0247] Figure 32A Also shown are multiple passive devices, such as deep trench capacitors (DTCs) 3203, formed in a first local interconnect die 350 of the first semiconductor package 850. In some embodiments, the deep trench capacitor 3203 may be formed in a first interconnect substrate 351 of the first local interconnect die 350. In one embodiment, the deep trench capacitor 3203 may comprise a three-dimensional corrugated stack having multiple metal layers (not shown separately) separated by multiple insulating layers (not shown separately). In one embodiment, the deep trench capacitor 3203 may be a single trench capacitor containing multiple metal through-holes (not shown separately) in a single recess (not shown separately), or it may be a multi-trench capacitor containing multiple metal through-holes in multiple recesses.

[0248] In addition, although Figure 32AThe TSV guard ring 3201 and deep trench capacitor 3203 in the first semiconductor package 850 are shown, but are for illustrative purposes only. The TSV guard ring 3201 can be formed of similar materials and similar processes to surround the first device substrate through-hole 1561 in the second semiconductor package 1850 and the second device substrate through-hole 2061 in the third semiconductor package 3050. Similarly, the DTC can be formed in a similar process and of similar materials in the second local interconnect die 1005 of the second semiconductor package 1850 and the third local interconnect die 2550 of the third semiconductor package 3050.

[0249] refer to Figure 32B ,exist Figure 32A The image shows a top-down section view of the TSV protection ring 3201 surrounding the first substrate through-hole 111, taken at section cut line AA. In one embodiment, the TSV protection ring 3201 may be rectangular (e.g., square) in the top view. However, any suitable shape may be used to surround the first substrate through-hole 111.

[0250] Advantages can be achieved by combining various local interconnect structures (e.g., first local interconnect die 350, second local interconnect die 1005, and third local interconnect die 2550) with various carrier substrates (e.g., first carrier substrate 500, second carrier substrate 1000, third carrier substrate 1200, etc.) via front-to-front orientation bonding of various semiconductor devices or semiconductor wafers with active circuit systems. The various carrier substrates allow for the formation of various local interconnect structures at different manufacturing steps, thereby increasing flexibility. Furthermore, front-to-front orientation allows for the formation of back-side redistribution structures (e.g., first back-side redistribution structure 800) to facilitate external connectivity. The combination of back-side redistribution structures and various local interconnect structures allows for increased interconnectivity between functional circuit systems within various semiconductor packages (e.g., first semiconductor package 850, second semiconductor package 1850, and third semiconductor package 3050) and improved functionality, efficiency, and performance of these various semiconductor packages. Improved design flexibility allows for enhanced functionality in the manufacture of various semiconductor packages while reducing costs.

[0251] According to an embodiment, a method includes bonding a first semiconductor die to a first side of a first semiconductor device, the first semiconductor device including a first region of an active circuit system and a second region of an active circuit system electrically isolated from the first region of the active circuit system; bonding a second semiconductor die to the first side of the first semiconductor device and adjacent to the first semiconductor die; bonding a partial interconnect die to the first side of the first semiconductor device and between the first semiconductor die and the second semiconductor die, wherein the partial interconnect die electrically connects the first region of the active circuit system to the second region of the active circuit system; and forming a redistribution circuit structure on a second side of the first semiconductor device opposite to the first side of the first semiconductor device, wherein forming the redistribution circuit structure includes forming a plurality of dielectric layers over the second side of the first semiconductor device opposite to the first side and forming a plurality of metallization layers within the plurality of dielectric layers. In one embodiment, the first region of the active circuit system and the second region of the active circuit system are disposed on the same semiconductor substrate. In one embodiment, before bonding the first semiconductor die to the first semiconductor device, the process further includes forming a first sealing ring and a second sealing ring within the first semiconductor device, wherein the first sealing ring surrounds a first region of the active circuit system and the second sealing ring surrounds a second region of the active circuit system. In one embodiment, after bonding the local interconnect die to the first semiconductor device, the local interconnect die directly covers the first sealing ring, the second sealing ring, and an intermediate region disposed between the first sealing ring and the second sealing ring. In one embodiment, after forming the first sealing ring and the second sealing ring in the first semiconductor device, a thinning process is performed on the back side of the first semiconductor device to expose a plurality of substrate vias of the first semiconductor device, the plurality of substrate vias being electrically coupled to the interconnect structure of the first semiconductor device. In one embodiment, bonding the first semiconductor die to the first semiconductor device includes forming a plurality of metal-to-metal bonds and a plurality of dielectric-to-dielectric bonds between the first semiconductor device and the first semiconductor die. In one embodiment, before bonding the local interconnect die to the first side of the first semiconductor device, the process further includes bonding the local interconnect die to a carrier substrate. In one embodiment, after bonding the local interconnect die to the first side of the first semiconductor device, the method further includes bonding the local interconnect die to a carrier substrate.

[0252] According to an embodiment, an apparatus includes a semiconductor device having a semiconductor substrate, a plurality of first substrate vias and a plurality of second substrate vias extending through the semiconductor substrate, an interconnect structure above the semiconductor substrate including a plurality of first metallization patterns electrically coupled to the plurality of first substrate vias and a plurality of second metallization patterns electrically coupled to the plurality of second substrate vias, a first sealing ring surrounding the plurality of first metallization patterns to define a first semiconductor region and a second sealing ring surrounding the plurality of second metallization patterns to define a second semiconductor region, a partial interconnect structure coupled to both the first semiconductor region and the second semiconductor region, wherein the partial interconnect structure directly covers the first sealing ring and the second sealing ring, and a first redistributable wiring structure disposed on the semiconductor device, the first redistributable wiring structure being electrically connected to the first semiconductor region through the plurality of first substrate vias and electrically connected to the second semiconductor region through the plurality of second substrate vias. In one embodiment, the apparatus further includes a first semiconductor die coupled to the first semiconductor region and a second semiconductor die coupled to the second semiconductor region. In one embodiment, the first semiconductor die is electrically coupled to the second semiconductor die through the first redistributable wiring structure. In one embodiment, the first semiconductor region is electrically coupled to the second semiconductor region through the local interconnect structure, the first semiconductor die is electrically coupled to the first semiconductor region, and the second semiconductor die is electrically coupled to the second semiconductor region. In one embodiment, the first semiconductor die and the second semiconductor die are embedded in a molding compound. In one embodiment, the first semiconductor region and the second semiconductor region in the semiconductor device are electrically isolated.

[0253] According to an embodiment, a method includes bonding a first metallization structure of a first semiconductor die to a second metallization structure of a semiconductor device, wherein the second metallization structure is surrounded by a first sealing ring; bonding a third metallization structure of the second semiconductor die to a fourth metallization structure of the semiconductor device, wherein the fourth metallization structure is surrounded by a second sealing ring; bonding a fifth metallization structure of a local interconnect die to the second and fourth metallization structures of the semiconductor device, wherein the fifth metallization structure overlaps with both the first and second sealing rings; and forming a first redistribution circuit structure on the opposite side of the semiconductor device to the first semiconductor die, the second semiconductor die, and the local interconnect die. In one embodiment, forming the first redistribution circuit structure includes forming a sixth metallization structure in a plurality of dielectric layers using one or more damascene processes. In one embodiment, the method further includes forming a contact pad on the sixth metallization structure, forming a passivation layer on the contact pad, forming an under-bump metal (UBM) in direct physical contact with the contact pad, a portion of the under-bump metal being embedded in the passivation layer, and forming a conductive connector in direct physical contact with the under-bump metal, wherein the conductive connector and the contact pad are on opposite sides of the under-bump metal. In one embodiment, the intermediate region is located between the first sealing ring and the second sealing ring and has no active circuitry. In one embodiment, the method further includes bonding a carrier substrate to the semiconductor substrate of the semiconductor device relative to the first metallization structure after bonding the first metallization structure of the first semiconductor die to the second metallization structure of the semiconductor device. In one embodiment, the first sealing ring surrounds the second metallization structure, electrically isolating the second metallization structure within the semiconductor device from the fourth metallization structure.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor device, including: Semiconductor substrate; Multiple first substrate through-holes and multiple second substrate through-holes extend through the semiconductor substrate; An interconnect structure is disposed above the semiconductor substrate, the interconnect structure including a plurality of first metallization patterns electrically coupled to the plurality of first substrate vias and a plurality of second metallization patterns electrically coupled to the plurality of second substrate vias; A first sealing ring surrounds the plurality of first metallization patterns and defines a first semiconductor region; and A second sealing ring surrounds the plurality of second metallization patterns and defines a second semiconductor region; A local interconnect structure joins the first semiconductor region and the second semiconductor region, wherein the local interconnect structure directly covers the first sealing ring and the second sealing ring; and A first redistributed circuit structure is disposed on the semiconductor device. The first redistributed circuit structure is electrically connected to the first semiconductor region through the plurality of first substrate vias and electrically connected to the second semiconductor region through the plurality of second substrate vias.

2. The semiconductor device according to claim 1, characterized in that, Including: The first semiconductor die is bonded to the first semiconductor region; as well as The second semiconductor die is bonded to the second semiconductor region.

3. The semiconductor device according to claim 2, characterized in that, The first semiconductor die is electrically coupled to the second semiconductor die through the first redistribution circuit structure.

4. The semiconductor device according to claim 2, characterized in that, The first semiconductor region is electrically coupled to the second semiconductor region through the local interconnect structure, the first semiconductor die is electrically coupled to the first semiconductor region, and the second semiconductor die is electrically coupled to the second semiconductor region.

5. The semiconductor device according to claim 2, characterized in that, The first semiconductor die and the second semiconductor die are embedded in a molding compound.

6. The semiconductor device according to claim 1, characterized in that, The first semiconductor region and the second semiconductor region within the semiconductor device are electrically isolated.

7. The semiconductor device according to claim 1, characterized in that, Including: Multiple conductive connectors are disposed above the first re-laid circuit structure and electrically coupled to it.

8. The semiconductor device according to claim 7, characterized in that, Including: Multiple bumps under metal are disposed between the multiple conductive connectors and the first redistributed circuit structure and electrically coupled thereto.

9. The semiconductor device according to claim 1, characterized in that, Including: The intermediate zone is located between the first sealing ring and the second sealing ring.

10. The semiconductor device according to claim 9, characterized in that, The intermediate region contains no active circuitry.

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