Low-end ideal diode based on voltage comparator

Abstract

The utility model discloses a low-end ideal diode based on a voltage comparator, which comprises an NMOS (N-channel Metal Oxide Semiconductor) main tube, a comparator and the voltage comparator, and is characterized in that the NMOS main tube, the comparator and the voltage comparator form an integral circuit, the comparator consists of two NMOS auxiliary tubes and a resistor, and the resistor is connected with the NMOS auxiliary tubes. And the output signal of the front-end NMOS auxiliary tube or the rear-end NMOS auxiliary tube of the comparator is compared with the voltage comparator again. Based on the characteristics of a hysteresis voltage comparator (operational amplifier), advantages are complemented to achieve advantage complementation, a novel low-end ideal diode device is achieved based on the technical scheme of an NMOS main tube, an NMOS auxiliary tube (geminate tube) and the hysteresis voltage comparator, the circuit has the function of preventing backflow, and a pre-stage circuit can be protected; the loss is low, and the quiescent current loss is small; the circuit is simple, low in cost and high in practicability.

Description

TECHNICAL FIELD

[0001] The utility model relates to diode technical field, concretely is a low end ideal diode based on voltage comparator. BACKGROUND

[0002] Diode has unidirectional conduction characteristic and prevents reverse flow function, and is applied more and more, especially Schottky diode has smaller voltage drop, and is more and more welcomed by designers. Since the conduction voltage drop of Schottky diode is still greater than the voltage drop of MOS tube, for some voltage-sensitive circuits, MOS tube with low impedance characteristic is more inclined to be used, and the reliability of product is improved.

[0003] At present, Oring circuit is applied to many occasions, and the role is to ensure that each single power supply is independent of each other and does not appear reverse flow phenomenon, and is most commonly applied in current sharing circuit, and meets different power requirements. Therefore, a low-loss low-end ideal diode is required, and the ideal diode with ultra-low loss further reduces the voltage drop and has the functions of preventing reverse flow and protecting the previous stage, so that the loss is minimized, and the battery working time is prolonged.

[0004] The main technical scheme of the low-end ideal diode realized by the prior art is as follows:

[0005] NMOS main tube+NPN auxiliary tube technical scheme (one-way conduction device patent number: TW200537799A) belongs to low-end ideal diode and has unidirectional conductivity. Circuit uses NPN auxiliary tube combination logic control circuit to control power NMOS main tube, uses two NPN tubes of the same manufacturer and the same batch, so that the parameters of the two NPN tubes are basically equal, or the two NPN pair tubes are preferably packaged together, and the parameters of the two NPN pair tubes are almost equal, so that the appropriate switching and reverse flow prevention functions can be ensured, the insertion conduction voltage drop is low, and it is suitable for application in ultra-low power consumption occasions and can be used as a low-end low-power ideal power diode. The disadvantage is that the bias resistance of NPN auxiliary tube is kilo-ohm level, and the static working current loss is milli-ampere level, so the current loss is large, and the loss is large.

[0006] NMOS main tube+NMOS auxiliary tube technical scheme: (a kind of ultra-low loss low-end ideal diode, patent number: CN202020206261.X) belongs to low-end ideal diode and has unidirectional conductivity. Circuit uses NMOS auxiliary tube combination logic control circuit to control NMOS main tube. The bias resistance of NMOS auxiliary tube is mega-ohm level, and the static working current loss is micro-ampere level, so the current loss is very small, and the current loss is much lower than that of NMOS main tube+NPN auxiliary tube technical scheme.

[0007] The comparator realized by the above technical scheme belongs to single-limit comparator: that is, the circuit has only one threshold voltage V T, any slight change of input voltage near the threshold voltage will cause the output voltage to jump, regardless of the slight change from the input signal or external interference. When the input voltage Vi gradually increases or decreases, the output Vo voltage jumps from V T to V OH , or V OL to V OL , or V OH . The applied circuit is a zero-crossing comparator, a general single-limit comparator. The single-limit comparator is sensitive, but poor in anti-interference ability.

[0008] In the single-limit comparator, slight changes in the input voltage near the threshold voltage can cause the output voltage to jump, with high sensitivity but weak anti-interference ability. The hysteresis comparator has hysteresis, i.e. inertia, and thus has certain anti-interference ability. A positive feedback circuit is generally introduced to form a double-threshold reverse input hysteresis voltage comparator (also known as a Schmidt trigger), which has a threshold voltage that changes with the output voltage due to the effect of positive feedback, thus improving the anti-interference ability and obtaining a more ideal voltage transmission characteristic. The hysteresis comparator circuit has two threshold voltages, V T1 , the threshold voltage V T2 that makes the output voltage Vo jump during the gradual decrease of the input voltage Vi, V T1 ≠ V T2 , the circuit has hysteresis. The same as the single-limit comparator is that when the input voltage changes in a single direction, the output voltage Vo only jumps once. The absolute value of the difference between the two threshold voltages is called the hysteresis voltage ΔV = V T2 -V T1 , the greater the hysteresis voltage, the stronger the anti-interference ability, and the worse the sensitivity. According to the use occasion, the relevant values are reasonably set, and for this purpose, a low-end ideal diode based on a voltage comparator is proposed to solve the above problems. Content of the utility model

[0009] The utility model aims at providing a low-end ideal diode based on a voltage comparator to solve the problems in the background technology.

[0010] To achieve the above purpose, the utility model provides the following technical scheme: a low-end ideal diode based on a voltage comparator, comprising an NMOS main pipe, a comparator, and a voltage comparator, characterized in that: the NMOS main pipe, the comparator, and the voltage comparator constitute an integral circuit, the comparator is composed of two NMOS auxiliary pipes and a resistor, and the output signal of the front-end NMOS auxiliary pipe or the rear-end NMOS auxiliary pipe of the comparator is compared again with the voltage comparator.

[0011] Preferably, the comparator comprises NMOS auxiliary tube V2, NMOS auxiliary tube V3, resistance R1 and resistance R2, which constitute a common gate differential amplifier circuit, the gate and drain of the NMOS auxiliary tube V3 are short-circuited, the drain of the NMOS auxiliary tube V2 indirectly controls the NMOS main tube V1, the gate and drain of the NMOS auxiliary tube V2 are short-circuited, and the NMOS auxiliary tube V3 indirectly controls the NMOS main tube V1.

[0012] Preferably, the source of the NMOS auxiliary tube V2 and the source of the NMOS auxiliary tube V3 are respectively inserted with a diode and the drain of the NMOS main tube.

[0013] Preferably, the voltage comparator is a hysteresis comparator.

[0014] Compared with the prior art, the utility model has the advantages that: based on the characteristics of the hysteresis voltage comparator (operational amplifier), the advantages are complementary by taking the strengths and compensating for the weaknesses, the new low-end ideal diode device is realized based on the NMOS main tube + NMOS auxiliary tube (opposite tube) + hysteresis voltage comparator technical scheme, the circuit has the function of preventing backflow and can protect the front-stage circuit; the circuit is simple, the cost is low, and the practicability is strong. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is the front-end NMOS auxiliary tube control NMOS type (main tube) low-end ideal diode principle diagram of the utility model;

[0016] Figure 2 It is the front-end NMOS auxiliary tube control NMOS type (main tube) low-end ideal diode improved principle diagram of the utility model;

[0017] Figure 3 It is the rear-end NMOS auxiliary tube control NMOS type (main tube) low-end ideal diode principle diagram of the utility model;

[0018] Figure 4 It is the rear-end NMOS auxiliary tube control NMOS type (main tube) low-end ideal diode improved principle diagram of the utility model;

[0019] Figure 5 It is the utility model Figure 1 Forward bias simulation;

[0020] Figure 6 It is the utility model Figure 1 Reverse bias simulation;

[0021] Figure 7 It is the utility model Figure 2 Reverse bias simulation;

[0022] Figure 8For the utility model Figure 3 Forward bias simulation;

[0023] Figure 9 For the utility model Figure 3 Reverse bias simulation;

[0024] Figure 10 For the utility model Figure 4 Reverse bias simulation. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the utility model. EMBODIMENT

[0026] With reference to Figure 1 , 2 , the first embodiment of the utility model provides a low-end ideal diode based on voltage comparator, including NMOS main pipe V1, comparator (V2 pipe, V3 pipe, R1, R2 constitute common gate differential amplifier circuit, the gate and drain of V3 pipe are short-circuited), voltage comparator U1, NMOS main pipe, comparator, voltage comparator constitute integral circuit, the comparator is formed by two NMOS auxiliary pipes and resistance, the output signal of NMOS auxiliary pipe in the front end of comparator or NMOS auxiliary pipe in the rear end of comparator is compared with voltage comparator again, and the output signal of voltage comparator controls the conduction and cut-off of NMOS main pipe.

[0027] The comparator includes NMOS auxiliary pipe V2, NMOS auxiliary pipe V3, resistance R1 and resistance R2, and constitutes common gate differential amplifier circuit, the gate and drain of NMOS auxiliary pipe V3 are short-circuited, the drain of NMOS auxiliary pipe V2 indirectly controls NMOS main pipe V1, the gate and drain of NMOS auxiliary pipe V2 are short-circuited, and NMOS auxiliary pipe V3 indirectly controls NMOS main pipe V1.

[0028] As Figure 1As shown, the comparator is composed of a front end (or left end, left side, in front of the NMOS main pipe) NMOS auxiliary pipe V2 and a rear end (or right end, right side, in the back of the NMOS main pipe) NMOS auxiliary pipe V3, and the circuit belongs to the indirect control of the drain of the front end NMOS auxiliary pipe V2. The comparator uses two NMOS auxiliary pipes V2 and V3, and the comparator compares the voltage of the drain (GND) and the source (V1S) of the NMOS main pipe V1. The comparator compares the output signal VC of the front end NMOS auxiliary pipe V2 with the reference voltage VREF, and the voltage comparator U1 outputs a signal VB to control the conduction and cutoff of the NMOS main pipe V1. When the voltage V1S is not less than the voltage GND, the voltage comparator U1 outputs a high level VB to control the conduction of the drain-source channel of the NMOS main pipe V1; otherwise, when the voltage V1S is less than the voltage GND, the voltage comparator U1 outputs a low level VB to control the cutoff of the drain-source channel of the NMOS main pipe V1, preventing the GND current from flowing back to VCC and protecting the VCC power supply front-end circuit.

[0029] The sources of the NMOS auxiliary pipe V2 and the NMOS auxiliary pipe V3 are respectively inserted with a diode and the source of the NMOS main pipe and the drain of the NMOS main pipe.

[0030] The voltage comparator is a hysteresis comparator with a hysteresis loop transmission characteristic.

[0031] The working principle of the low-end ideal diode is as follows.

[0032] When the DC power supply VCC=VCC1 is powered on (the NMOS pipe V1 is forwardly conducted), the current output by VCC passes through RL, the body diode of the NMOS pipe V1 (GND=V1S-V F ≈0V, V F is the body diode conduction voltage drop), when the output current gradually increases and the internal voltage V1S is obviously higher than the external voltage GND (V1S>GND), the NMOS pipe V3 is gradually conducted (from cutoff, linear conduction, and finally to saturation conduction, and the conduction current is inversely proportional to R2), VA=GND+V TN (V TN is the NMOS pipe conduction threshold voltage); the drain-source channel impedance of the NMOS pipe V2 gradually increases (from saturation conduction, linear conduction, and finally to weak conduction, and the drain-source conduction impedance of the V2 pipe is greater than that of the V3 pipe), the drain voltage VC of the NMOS pipe V2 gradually increases, and when VREF=VCC×R6 / (R6+R5)<VC, the voltage comparator U1 outputs a high level, i.e. VB≈VCC, and V1 GS =VB-V1S≈VCC-V F >V TN, NMOS V1 drain-source channel conduction, VCC current through the load RL, NMOS V1 drain-source low impedance channel to the power supply negative GND (no longer through the NMOS V1 body diode high impedance channel), V1S ≈ 0V, V1 GS =VB-V1S≈VCC>V TN , NMOS V1 drain-source channel conduction impedance is small, that is, the conduction loss is less than the diode, reducing power loss and improving power utilization efficiency.

[0033] When the external voltage GND = VCC2 is greater than the internal power supply VCC (VCC + V F >VCC2>VCC), the impedance of the NMOS V3 drain-source channel gradually increases (from saturation conduction, linear conduction, and finally to the cutoff state, V3 body diode cutoff), and the impedance of the NMOS V2 drain-source channel gradually increases (from saturation conduction, linear conduction, and finally to the cutoff state). The voltage VC gradually increases, and finally VC ≈ VCC, V1S ≈ VCC, VC > VREF = VCC × R6 / (R6 + R5). The voltage comparator U1 outputs a high level, VB ≈ VCC, V1 GS =VB-V1S≈0<V TN , NMOS V1 drain-source channel cutoff, power supply VCC1 and external voltage VCC2 are isolated, and the current of the external power supply (other power supplies connected in parallel with voltage VCC2) cannot flow back to the internal power supply VCC, achieving the purpose of protecting the power supply VCC.

[0034] When VCC2 ≥ VCC - V F , V3 body diode conduction, VA = VCC2 - V F , V3 GS =VA-VCC2≈ VCC2-V F -VCC2=-V F <V TN , NMOS V3 drain-source channel cutoff, but there is a backflow current of VCC2 through the body diode, R2 to VCC; V2 GS =VA-V1S≈VCC2-V F -VCC>0V, since the voltage at the drain and source of V2 is VCC, when V2 GS =VA-V1S=VCC2-V F -VCC>V TN , NMOS V2 drain-source channel conduction, but there is no closed loop, no loop current, so regardless of the conduction or cutoff of the NMOS V2 drain-source channel, VC ≈ VCC; since VCC > VREF, U1 outputs a high level VB == VCC, V1S = VCC, V1 GS =VB-V1S≈VCC-VCC=0V<VTN , the drain-source channel of NMOS V1 is cut off. Embodiment

[0035] On the basis of embodiment 1, a diode is inserted between the source of V2 and the drain of NMOS main tube V1, and a diode is inserted between the source of V3 and the drain of NMOS main tube V1, as shown in Figure 2 When VCC2≥VCC, the current of VCC2 can be prevented from flowing back to power supply VCC. Embodiment

[0036] This embodiment has basically the same circuit structure as embodiment 1, as shown in Figure 3 The difference between this embodiment and the above two embodiments is that embodiment 1 indirectly controls NMOS main tube V1 by the drain of front-end NMOS auxiliary tube V2, and embodiment 2 indirectly controls NMOS main tube V1 by the drain of rear-end NMOS auxiliary tube V3.

[0037] When the direct current power supply VCC=VCC1 is powered on (NMOS V1 is forward conducting), the current output by VCC flows through RL, the body diode of NMOS V1, to the negative electrode of the power supply (GND=V1S-V F ≈0V, V F is the conduction voltage drop of the body diode), when the output current gradually increases and the internal voltage V1S is obviously higher than the external voltage GND (V1S>GND), NMOS V3 gradually conducts (from cut-off, linear conduction, to finally saturated conduction, the conduction current is inversely proportional to R2), VA=GND+V TN (V TN is the conduction threshold voltage of NMOS), the drain-source channel impedance of NMOS V2 gradually increases (from saturated conduction, linear conduction, to finally weak conduction, the drain-source conduction impedance of V2 is greater than that of V3), the drain voltage VC of NMOS V3 gradually decreases, and finally VC≈GND=0V, when VREF=VCC×R6 / (R6+R5)>VC, the voltage comparator U1 outputs high level, i.e. VB≈VCC, and V1 GS =VB-V1S≈VCC-V F >V TN When the drain-source channel of NMOS V1 is conducting, the current of VCC flows through the load RL and the low-impedance channel of the drain and source of NMOS V1 to the negative electrode of the power supply GND (no longer through the high-impedance channel of the body diode of NMOS V1), the conducting impedance of the drain-source channel of NMOS V1 is small, i.e. the conduction loss is less than that of the diode, which reduces the power loss and improves the power utilization efficiency.

[0038] When the external voltage GND=VCC2 is greater than the internal power supply VCC (VCC+V FVCC2>VCC), the drain-source channel impedance of NMOS V3 gradually increases (from saturation conduction, linear conduction, and finally to the off state, with the V3 body diode off), the drain-source channel impedance of NMOS V2 gradually increases (from saturation conduction, linear conduction, and finally to the off state), the voltage VC gradually increases, VC≈VCC, V1S≈VCC, VC>VREF=VCCxR6 / (R6+R5), the voltage comparator U1 outputs a low level, VB≈0V, V1 GS =VB-V1S≈-VCC<0<V TN , the drain-source channel of NMOS V1 is off, the power supply VCC1 is isolated from the external voltage VCC2, and the current of the external power supply (another power supply connected in parallel with the voltage VCC2) cannot flow back to the internal power supply VCC, achieving the purpose of protecting the power supply VCC.

[0039] When VCC2≥VCC+V F , the V3 body diode is on, VC=VCC2-V F , VA=VCC, V3 GS =VA-VCC2≈VCC-V F -VCC2<-2xV F <V TN , the drain-source channel of NMOS V3 is off, but there is a weak backflow current of VCC2 through the body diode, R2 to VCC; since the voltages at the drain and source of V2 are both VCC, V2 GS =VA-V1S≈VCC-VCC=0V<V TN , the drain-source channel of NMOS V2 is off; since VC>VREF, U1 outputs a low level, VB=0V, V1 GS =VB-V1S≈0V-VCC=-VCC<V TN , the drain-source channel of NMOS V1 is off. Embodiment

[0040] On the basis of Embodiment 3, a diode is inserted between the source and drain of NMOS main tube V1, respectively, as shown in Figure 4 When VCC2≥VCC, the current of VCC2 can be prevented from flowing back to the power supply VCC.

[0041] According to Figures 1 to 4 the circuit schematic diagram is simulated and tested using the simulation software Multisim (version V14.0) of National Instruments Company, the selected model of the voltage comparator is LMC7211AIM5, a rail-to-rail operational amplifier, and the output stage uses a push-pull amplifier to achieve approximate full swing; the selected model of the NMOS tube is BSP030 of NXP Company, with a minimum on-state threshold voltage of VTN(MIN) =1V, maximum value V TN(MAX) =2.8V, no typical value V TN , on current I D =10A / 30V, on resistance R DS(ON) ≤0.03Ω (V GS =10V), R DS(ON) ≤0.05Ω (V GS =4.5V), maximum working voltage is 30V; the diode is selected from the components of Motorola company, model is 1N4001. Load resistance RL=10Ω, the specific simulation test is as follows.

[0042] Simulation of example 1

[0043] Simulation test of forward conduction of DC power supply: set R5=300kΩ, R6=100kΩ, R1=R2=1MΩ, VCC=VCC1=12V (switch J1 is closed), VREF≈VCC / 4=3V, NMOS main pipe V1 output current 1.2A (test point PR4) when forward conduction; the drain current of NMOS auxiliary pipe V2 is 8.80μA (test point PR7), which can be considered that the drain-source channel of NMOS auxiliary pipe V2 is turned on; the drain current of NMOS auxiliary pipe V3 is 10.6μA (test point PR8), which can be considered that the drain-source channel of NMOS auxiliary pipe V3 is turned on, the drain-source channel conduction resistance V3R DS(ON) of V2 pipe drain-source channel conduction resistance V2R DS(ON) is smaller (V3R DS(ON) <V2R DS(ON) ), the drain output high level of the front end NMOS auxiliary pipe V2, that is, VC=3.2V (test point PR2), VC is compared with VREF, the voltage comparator U1 outputs VB=12.0V, the drain-source channel of NMOS main pipe V1 is turned on, and the conduction voltage drop is 22.748mV (measured by a multimeter), which is lower than the conduction voltage drop V F =0.6V of the diode, the conduction resistance R DS(ON) =22.748mV / 1.2A=18.956mΩ, which is consistent with the data manual, as shown in Figure 5 .

[0044] Simulation test of reverse cut-off of DC power supply: after the switch J1 is closed, the switch J2 is also closed, and the GND symbol of the simulation diagram is deleted, that is, GND=VCC2=24V, VCC2>VCC=VCC1=12V, the drain current of NMOS auxiliary pipe V2 is 4.49nA (test point PR7), which can be considered that the drain-source channel of NMOS auxiliary pipe V2 is cut off; the drain current of NMOS auxiliary pipe V3 is-11.6μA (test point PR8), which can be considered that the body diode channel of NMOS auxiliary pipe V3 is turned on, V3GS = VA-Vout = 23.6V-24V = -0.4V < V TN , V3's drain-source channel is off; V1S = VCC-88.8nA x 10Ω ≈ VCC = 12V, V2 GS = VA-V1S = 23.6V-12V = 13.6V > V TN , V2's drain-source channel is on, but there is no closed loop, only weak conduction current (4.49nA); the NMOS auxiliary V2's drain output high level, VC = 12.0V (test point PR2), VC > VREF = VCC / 4 = 3V, voltage comparator U1 output VB = 12.0V, V1 GS = VB-V1S ≈ 0V < V TN , NMOS main V1's drain-source channel is off, NMOS main V1 has no reverse current, VCC1 output current is 88.8nA (test point PR4) to RL, no backflow current occurs, as shown in Figure 6 .

[0045] Example 2 simulation

[0046] The source of V2 and V3 is inserted with a diode respectively, and the DC power supply is reverse off simulation test: after closing switch J1, switch J2 is also closed, that is, GND = VCC2 = 24V, VCC2 > VCC = VCC1 = 12V, due to the existence of reverse leakage current of D1, the drain current of NMOS auxiliary V2 is -785nA (test point PR7), which can be considered that the body diode channel of NMOS auxiliary V2 is weakly on; due to the existence of reverse leakage current of D2, the drain current of NMOS auxiliary V3 is -86.2nA (test point PR8), which can be considered that the body diode channel of NMOS auxiliary V3 is weakly on, compared with the reverse bias simulation of technical scheme (one) (the reverse current of V3 is 11.6μA), the reverse current of V3 in the implementation mode two is greatly reduced; the NMOS auxiliary V2's drain output high level, VC = 12.4V (test point PR2), VC compared with VREF, voltage comparator U1 output VB = 12.1V, V1S = VCC-31.1μA x 10Ω ≈ VCC = 12V, V1 GS = VB-V1S = 0.1V < V TN , NMOS main V1's drain-source channel is off, NMOS main V1 has no reverse current, VCC1 output current is greater than 31.1μA (test point PR4), no backflow current occurs, as shown in Figure 7 , which can prevent the current of VCC2 from flowing back to the power supply VCC. Adding a diode can avoid the backflow current in the simulation of technical scheme one.

[0047] Example 3 Simulation

[0048] DC power supply forward conduction simulation test: R5 = 100kΩ, R6 = 300kΩ, VREF = VCC × R6 / (R6 + R5) = 0.75 × VCC = 9V, R1 = R2 = 100kΩ, VCC = VCC1 = 12V (switch J1 closed). During forward conduction, the NMOS main transistor V1 outputs a current of 1.2A; the drain current of the NMOS auxiliary transistor V2 is 10.5μA (test point PR7), indicating that the drain-source channel of NMOS auxiliary transistor V2 is conducting; the drain current of the NMOS auxiliary transistor V3 is 11.9μA (test point PR8), indicating that the drain-source channel of NMOS auxiliary transistor V3 is conducting. The drain-source channel on-resistance of transistor V3 is V3R. DS(ON) The drain-source path on-resistance V2R of transistor V2 DS(ON) Small (V3R) DS(ON) <V2R DS(ON) The drain output of the NMOS auxiliary transistor V3 at the front end of the comparator is low, VC=89.6mV (test point PR2). VC is compared with VREF, and the voltage comparator U1 outputs VB=12.0V. The drain-source channel of the NMOS main transistor V1 is turned on, and the on-state voltage drop is 22.732mV (measured with a multimeter), which is lower than the diode's on-state voltage drop VF=0.6V, corresponding to the on-resistance VR. DS(ON) =22.732mV / 1.20A=18.94mΩ, consistent with the simulation of technical solution one. Figure 8 As shown.

[0049] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed. The GND symbol in the simulation diagram is removed, meaning GND = VCC2 = 24V, VCC2 > VCC = VCC1 = 12V. The drain current of NMOS auxiliary transistor V2 is -446pA (test point PR7), indicating that the drain-source channel of NMOS auxiliary transistor V2 is cut off. The drain current of NMOS auxiliary transistor V3 is -118μA (test point PR8), indicating that the drain-source channel of NMOS auxiliary transistor V3 is cut off (body diode is conducting). The drain output of NMOS auxiliary transistor V3 at the comparator is high, i.e., VC = 23.5V (test point PR2). Comparing VC with VREF, the voltage comparator U1 outputs VB = 67.9mV. GS =VB-V1S≈-12.0V<0V<V TN The drain-source channel of NMOS transistor V1 is cut off, and there is no reverse current in VMOS transistor V1. The output current of VCC1 is -65.7μA (test point PR4). There is a slight reverse current, which can be ignored. (Details are as follows...) Figure 9 As shown.

[0050] Example 4 Simulation

[0051] The source of the V2 tube and the source of the V3 tube are respectively inserted with a diode, and the source of the NMOS main tube V1 is inserted with a diode, and the direct current power supply is reversely cut off for simulation test: after the switch J1 is closed, the switch J2 is also closed, that is, GND=VCC2=24V, VCC2>VCC=VCC1=12V, because of the reverse leakage current of D1, the drain current of the NMOS auxiliary tube V2 is 317pA (test point PR7), and it can be considered that the body diode channel of the NMOS auxiliary tube V2 is weakly turned on; because of the reverse leakage current of D2, the drain current of the NMOS auxiliary tube V3 is 32nA (test point PR8), and it can be considered that the body diode channel of the NMOS auxiliary tube V3 is weakly turned on, the drain output of the rear end of the comparator NMOS auxiliary tube V3 is high level, VC=12.0V (test point PR2), VC is compared with VREF, the voltage comparator U1 outputs VB=67.9mV, V1S=VCC=12.0V, V1 GS =VB-V1S≈-12.0V<V TN , the drain-source channel of the NMOS main tube V1 is cut off, the NMOS main tube V1 does not have a reverse current, and the output current of VCC1 is 52.0uA (test point PR4), no backflow current occurs, and details are shown in Figure 10 , which can prevent the current of VCC2 from flowing back to the power supply VCC. The diode can avoid the backflow current in the simulation of the third technical scheme.

[0052] Under the same conditions, the turn-on voltage drop of the main tube of the low-end ideal diode is only a few tens of millivolts, which is suitable for occasions with large working current, and it is verified that the NMOS tube as the main tube has extremely low turn-on impedance.

[0053] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirits of the utility model, and the scope of the utility model is defined by the appended claims and their equivalents.

Claims

1. A low-side ideal diode based on a voltage comparator, comprising an NMOS main, a comparator, a voltage comparator, characterized in that: The NMOS main pipe, the comparator, the voltage comparator constitute an overall circuit, the comparator is composed of two NMOS auxiliary pipes and resistance, the comparator front end NMOS auxiliary pipe or rear end NMOS auxiliary pipe output signal is compared again with voltage comparator.

2. A low-side ideal diode based on a voltage comparator according to claim 1, characterized in that: The comparator includes NMOS auxiliary pipe V2, NMOS auxiliary pipe V3, resistance R1 and resistance R2, constitutes a common gate differential amplification circuit, the gate and drain of the NMOS auxiliary pipe V3 are short-circuited, the drain of the NMOS auxiliary pipe V2 indirectly controls the NMOS main pipe V1, the gate and drain of the NMOS auxiliary pipe V2 are short-circuited, and the NMOS auxiliary pipe V3 indirectly controls the NMOS main pipe V1.

3. A low-side ideal diode based on a voltage comparator according to claim 2, characterized in that: The source of the NMOS auxiliary pipe V2 and the source of the NMOS auxiliary pipe V3 are respectively inserted with a diode.

4. A low-side ideal diode based on a voltage comparator according to claim 1, characterized in that: The voltage comparator is a hysteresis comparator.

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