Time sequence alignment circuit and memory
By setting up data input/output modules with the same delay duration in the timing alignment circuit, the problem of incorrect data latching in traditional methods is solved, and correct data latching under different process and frequency conditions is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI XINCUN SEMICONDUCTOR CO LTD
- Filing Date
- 2025-02-18
- Publication Date
- 2026-04-17
AI Technical Summary
Traditional methods are difficult to effectively adjust the latching time under different process and frequency conditions, leading to data latching inaccuracies.
A timing alignment circuit is adopted. By setting the first and second data input/output modules, data and latch signals are output after the first and second delay times of receiving the clock control signal, respectively, and the delay times of the two are the same, so as to dynamically adapt to changes in external conditions.
The data caching module has improved the latching accuracy under different conditions, ensuring that data can be latched correctly under various processes and frequencies.
Smart Images
Figure CN224137909U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a timing alignment circuit and a memory. Background Technology
[0002] Setup time refers to the time it takes for data to remain stable before the clock edge of the flip-flop arrives. If the setup time is insufficient, the data will not be properly latched into the flip-flop. Setup time is typically one clock cycle (tCK), but with changes in manufacturing processes and increased operating frequencies, one clock cycle is no longer sufficient for the setup time required for data latching.
[0003] The traditional approach is to add a delay unit to the latch clock to ensure the latch setup time. However, it is difficult to adjust this method to the optimal value. If the delay is set too small, it cannot be guaranteed that the setup time is sufficient under all operating conditions. If the delay is set too large, there is a risk that the data will be latched to the next clock cycle after more than one cycle.
[0004] Therefore, improving the accuracy of latched data has become an urgent problem to be solved. Utility Model Content
[0005] This application provides at least one timing alignment circuit and memory to improve the correctness of latched data.
[0006] This application provides a timing alignment circuit, including a data buffer module, a clock signal receiving module, a first data input / output module, and a second data input / output module. The clock signal receiving module is configured to generate a clock control signal based on a clock signal. The first data input / output module is connected to the clock signal receiving module and is configured to output data to the data buffer module after receiving the clock control signal for a first delay duration. The second data input / output module is connected to the clock signal receiving module and is configured to generate a first latch signal after receiving the clock control signal for a second delay duration to instruct the data buffer module to latch the data output by the first data input / output module. The second delay duration is set to be the same as the first delay duration.
[0007] A second aspect of this application provides a memory including the timing alignment circuit described above.
[0008] Therefore, both the first data input / output module and the second data input / output module are connected to the clock signal receiving module. The first data input / output module outputs data to the data buffer module after a first delay period following the receipt of the clock control signal, and the second data input / output module outputs a first latch signal to the data buffer module after a second delay period following the receipt of the clock control signal. The second delay period is set to be the same as the first delay period. Thus, the second data input / output module enables the data buffer module to latch data when the first data input / output module outputs data to the data buffer module, thereby improving the accuracy of the data latched by the data buffer module.
[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description
[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.
[0011] Figure 1 This is a schematic diagram of the framework of a timing alignment circuit based on a fixed delay unit in the prior art;
[0012] Figure 2 This is a schematic diagram of the framework of an embodiment of the timing alignment circuit in this application;
[0013] Figure 3 This is a schematic diagram of the framework of another embodiment of the timing alignment circuit in this application;
[0014] Figure 4a This is a schematic diagram of the framework of yet another embodiment of the timing alignment circuit in this application;
[0015] Figure 4b This is a schematic diagram of another embodiment of the timing alignment circuit of this application.
[0016] Figure 5 This is a schematic diagram of a framework of an embodiment of the memory in this application. Detailed Implementation
[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0018] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.
[0019] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "many" in this document means two or more. Moreover, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.
[0020] Setup time refers to the time it takes for data to remain stable before the clock signal edge of the flip-flop arrives. If the setup time is insufficient, the data will not be correctly latched into the flip-flop. Setup time is typically one clock cycle, but with changes in manufacturing processes and increased operating frequencies, one clock cycle is no longer sufficient for data latching setup time. Traditional methods add a fixed delay unit to the latch clock to ensure the latch setup time. However, this method is difficult to adjust to its optimal value. If the delay is set too small, it cannot guarantee sufficient setup time under all operating conditions; if the delay is set too large, there is a risk of latching data beyond one cycle to the next clock cycle.
[0021] Please refer to Figure 1 , Figure 1This is a schematic diagram of the framework of a timing alignment circuit 100 based on a fixed delay unit in the prior art. Assuming that at time T0, the clock signal receiving module 110 generates a clock control signal and sends it to the data input / output module 120, causing the data input / output module 120 to send the stored data in the memory array area (not shown) to the data cache module 140. Simultaneously, the clock control signal is also sent to the data cache module 140, causing the data cache module 140 to latch the data received from the data input / output module 120 upon receiving the clock control signal. After passing through complex and numerous control logics and long traces in the data input / output module 120, the clock control signal places the stored data in the memory array area of the data input / output module 120 onto the data bus (not shown), and then sends this stored data to the data cache module 140 via the data bus. The clock control signal generated at time T0 experiences a delay in the data input / output module 120 due to the complex and numerous control logic steps and long traces involved. This means that the stored data in the memory array area is placed onto the data bus only after this delay. Therefore, to ensure the data cache module 140 can correctly latch the data, a fixed delay unit 130 is added between the clock signal receiving module 110 and the data cache module 140, ensuring the clock control signal arrives at the data cache module 140 after a fixed delay. However, the delay duration of the clock control signal in the data input / output module 120 is affected by external factors such as temperature, voltage, and frequency. Therefore, even with the fixed delay unit 130, it is difficult to guarantee that the delay in the data input / output module 120 will match under all conditions, thus preventing the data cache module 140 from correctly latching the data.
[0022] To improve the accuracy of data latching, this application provides a timing alignment circuit 200, please refer to... Figure 2The timing alignment circuit 200 includes a data buffer module 240, a clock signal receiving module 210, a first data input / output module 220, and a second data input / output module 230. The clock signal receiving module 210 is configured to generate a clock control signal based on a clock signal. The first data input / output module 220 is connected to the clock signal receiving module 210 and is configured to output data to the data buffer module 240 after a first delay period following the receipt of the clock control signal. The second data input / output module 230 is connected to the clock signal receiving module 210 and is configured to cause the data buffer module 240 to receive a first latch signal after a second delay period following the receipt of the clock control signal, instructing the data buffer module 240 to latch the data output by the first data input / output module 220. The second delay period is set to be the same as the first delay period.
[0023] In the above scheme, both the first data input / output module 220 and the second data input / output module 230 are connected to the clock signal receiving module 210. The first data input / output module 220 outputs data to the data buffer module 240 after a first delay in receiving the clock control signal. The second data input / output module 230 causes the data buffer module 240 to receive the first latch signal after a second delay in receiving the clock control signal. The first delay is the same as the second delay. Therefore, the second data input / output module 230 enables the data buffer module 240 to latch data when the first data input / output module 220 outputs data to the data buffer module 240, thereby improving the accuracy of the data latched by the data buffer module 240. Furthermore, since the second delay duration of the second data input / output module 230 is set to be the same as the first delay duration of the first data input / output module 220, that is, the second delay duration of the second data input / output module 230 will dynamically change with the first delay duration when external conditions change, so that the second data input / output module 230 can match the delay of the clock control signal in the first data input / output module 220 under various conditions, thereby improving the correctness of data latching of the timing alignment circuit 200 under various conditions.
[0024] In some embodiments, the second data input / output module 230 contains the same number of logic gates as the first data input / output module 220. When electrical signals (e.g., clock control signals) are transmitted in the second data input / output module 230, the logic gates cause significant delays. Having the same number of logic gates in both the second and first data input / output modules allows for better matching of the clock control signal delays in both modules. Furthermore, by setting the number of logic gates in the second data input / output module 230 to be the same as that in the first data input / output module 220, the delays of both modules remain essentially the same even under different external conditions, thereby improving the accuracy of data latching by the timing alignment circuit 200 under different conditions.
[0025] In some embodiments, the length of the signal transmission path of the second data input / output module 230 is equal to the length of the signal transmission path in the first data input / output module 220. The transmission of electrical signals in the signal transmission path causes significant delays. Having the length of the signal transmission path of the second data input / output module 230 equal to the length of the signal transmission path in the first data input / output module 220 allows for better matching of the delay of the clock control signal in both the second data input / output module 230 and the first input / output module 220. Furthermore, by setting the length of the signal transmission path of the second data input / output module 230 to be equal to the length of the signal transmission path in the first data input / output module 220, the delays of both modules remain essentially the same even under different external conditions, thereby improving the accuracy of data latching by the timing alignment circuit 200 under different conditions.
[0026] In some embodiments, the length of the signal transmission path in the second data input / output module 230 is equal to the length of the signal transmission path in the first data input / output module 220, and the number of logic gates in the second data input / output module 230 is the same as that in the first data input / output module 220. By setting the number of logic gates in the second data input / output module 230 to be the same as that in the first data input / output module 220, and setting the length of the signal transmission path in the second data input / output module 230 to be equal to the length of the signal transmission path in the first data input / output module 220, the delays of both can remain essentially the same even under different external conditions, thereby improving the correctness of the data latching of the timing alignment circuit 200 under different conditions.
[0027] In some embodiments, please refer to Figure 3The first data input / output module 220 includes an address latch unit 221, a read / write control unit 222, and a storage array 223.
[0028] Continue to refer to Figure 3 The clock control signal generated by the clock signal receiving module 210 passes through the address latch unit 221, the read / write control unit 222, and the storage array 223 in sequence, and places the stored data from the storage array 223 onto the data bus so as to send the stored data to the data cache module 240 through the data bus.
[0029] In some embodiments, the number of logic gates in the second data input / output module 230 is the same as the number of logic gates in the address latch unit 221, the read / write control unit 222, and the storage array 223.
[0030] In some embodiments, the length of the signal transmission path of the second data input / output module 230 is equal to the length of the signal transmission paths in the address latch unit 221, the read / write control unit 222, and the storage array 223.
[0031] It is understood that the specific circuit structures in the address latch unit 221, the read / write control unit 222, and the storage array 223, such as the address latch unit 221 may include several latches, and the storage array 223 may include capacitors, transistors, etc., are well known in the art and will not be described in detail here.
[0032] In some embodiments, the first data input / output module 220 and the second data input / output module 230 may employ identical circuit structures to ensure that the length of the signal transmission path in the second data input / output module 230 is equal to the length of the signal transmission path in the first data input / output module 220, and that the number of logic gates in the second data input / output module 230 is the same as that in the first data input / output module 220. In other embodiments, the first data input / output module 220 and the second data input / output module 230 may not be identical; it is sufficient that the length of the signal transmission path and the number of logic gates are the same.
[0033] In some embodiments, the first data input / output module 220 and the second data input / output module 230 are disposed in the same data input / output device.
[0034] Please refer to Figure 4a The first data input / output module 220 and the second data input / output module 230 can be combined into the same data input / output device. After receiving the clock signal, the clock signal receiving module 210 generates a clock control signal (e.g., Figure 4aThe clock control signal (CLK) is split into two signals and sent to the first data input / output module 220 and the second data input / output module 230 respectively. These two signals are transmitted in the first data input / output module 220 and the second data input / output module 230 respectively (e.g., Figure 4a The control CLK transmitted in the first data input / output module 220 and the matching CLK transmitted in the second data input / output module 230.
[0035] In some embodiments, continue to refer to Figure 4a The data input / output device has a clock signal input terminal T1, a latch signal output terminal T3, and a stored data output terminal T2; the clock signal input terminal T1 is connected to the clock signal receiving module 210; the latch signal output terminal T3 is connected to the data buffer module 240 to output the first latch signal to the data buffer module 240; and the stored data output terminal T2 is connected to the data buffer module 240 to output stored data to the data buffer module 240.
[0036] In some embodiments, continue to refer to Figure 4a The data input / output device includes a command / address latch unit 221, a read / write control unit 222, and a storage array 223. The command / address latch unit 221 is connected to the clock signal receiving module 210 and is configured to receive the clock control signal (e.g., control CLK or match CLK) and transmit the clock control signal. The read / write control unit 222 is connected to the command / address latch unit 221, receives the clock control signal transmitted by the command / address latch unit 221, and continues to transmit the clock control signal. The storage array 223 is connected to the read / write control unit 222 and is configured to generate the first latch signal after receiving the clock control signal and output the first latch signal to the data cache module 240.
[0037] Please refer to Figure 4b , Figure 4b This is a schematic diagram of another embodiment of the timing alignment circuit of this application. The input / output interface 250 includes a receiver (not shown, used to receive clock / data, etc.) and an off-chip driver tuner (not shown, used to output data, etc.). Figure 4bThe solid unidirectional arrow represents the clock control signal (control CLK) generated by the clock signal receiving module 210 after receiving the clock signal (CLK) from the input / output interface 250 and used for transmission in the first input / output module 220. The dashed unidirectional arrow represents the clock control signal (match CLK) generated by the clock signal receiving module 210 after receiving the clock signal (CLK) from the input / output interface 250 and used for transmission in the second input / output module 230. The bold dashed unidirectional arrow represents the first latch signal generated by the second input / output module 230. The control CLK and match CLK generated by the clock signal receiving module 210 can be sent to the first data input / output module 220 and the second data input / output module 230. Figure 4b As shown, the first data input / output module 220 includes a command / address latch unit 221, a control logic unit 224, an I / O control unit 226, a row address / column address control logic unit 225, and a memory array 223. The control CLK starts from the clock signal receiving module 210, reaches the first data input / output module 220, and sequentially passes through the command / address latch unit 221, control logic unit 224, and row address / column address control logic unit 225 within the first data input / output module 220, eventually reaching the memory array 223 to enable the memory array 223 to output data to the data buffer module 240. Therefore, the matching CLK, starting from the clock signal receiving module 210, also travels through the same trace length and number of logic gates to reach the second data input / output module 230. Furthermore, within the second data input / output module 230, it also passes through the equivalent of the command / address latch unit 221, control logic unit 224, and row address / column address control logic unit 225, and then to the memory array 223, causing the memory array 223 to output data to the data buffer module 240. The number of logic gates and the length of the traces between the address / column address control logic unit 225 and the memory array 223 are determined. The memory array 223 in the first data input / output module 220 outputs data to the data cache module 240 according to the control CLK. As a result, the second data input / output module 230 also sends the first latch signal to the data cache module 240 after passing through a trace length and the number of logic gates equivalent to that between the memory array 223 and the data cache module 240. This causes the data cache module 240 to latch the data based on the first latch signal. As a result, the second delay between the first latch signal received by the data cache module 240 and the clock control signal (control CLK) generated by the clock signal receiving module 210 is equal to the first delay between the stored data received by the data cache module 240 and the clock control signal (matching CLK) generated by the clock signal receiving module 210. Therefore, the data cache module 240 can correctly cache the data.
[0038] The data cache module 240 may include several D flip-flops (DFFs) and multiplexers (MUXs). The specific circuit structure in the data cache module 240 is well known in the art and will not be described in detail here.
[0039] It is understood that the command / address latch unit 221 is used to latch command information / address information; the control logic unit 224 may have a command decoding function, capable of decoding the state of various control lines and translating it into specific memory access commands. For example, the control logic unit 224 may include a command decoder for processing various control signals and generating corresponding memory access commands; the row address / column address control logic unit 225 is used to select specific rows and columns in the memory array 223 to access the memory array. The specific structures of the command / address latch unit 221, the control logic unit 224, the I / O control unit 226, the row address / column address control logic unit 225, and the memory array 223 are well known in the art and will not be described in detail here.
[0040] In some embodiments, the timing alignment circuit 200 may further include an off-chip driver (OCD, also known as an offline driver adjuster) (not shown in the figure), which is connected to the data cache module 240. After the data cache module 240 sends data to the off-chip driver adjuster, the off-chip driver adjuster then outputs data to the outside.
[0041] This application also provides a memory 500, such as Figure 5 As shown, the memory 500 includes the timing alignment circuit 200 in any of the above embodiments.
[0042] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0043] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.
[0044] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.
[0045] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.
[0046] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0047] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0048] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.
Claims
1. A timing alignment circuit, characterized by, include: Data caching module; The clock signal receiving module is configured to generate a clock control signal based on the clock signal; The first data input / output module, connected to the clock signal receiving module, is configured to output data to the data buffer module after a first delay period of receiving the clock control signal; The second data input / output module, connected to the clock signal receiving module, is configured to, after a second delay period following the receipt of the clock control signal, cause the data buffer module to receive a first latch signal to instruct the data buffer module to latch the data output by the first data input / output module. The second delay duration is set to be the same as the first delay duration.
2. A timing alignment circuit as claimed in claim 1, characterized in that The second data input / output module contains the same number of logic gates as the first data input / output module.
3. A timing alignment circuit as claimed in claim 2, characterized in that The first data input / output module includes an address latch unit, a read / write control unit, and a storage array; The second data input / output module contains the same number of logic gates as the address latch unit, the read / write control unit, and the memory array.
4. A timing alignment circuit according to any one of claims 1-3, characterized in that, The length of the signal transmission path in the second data input / output module is equal to the length of the signal transmission path in the first data input / output module.
5. A timing alignment circuit as claimed in claim 4, characterized in that The first data input / output module includes an address latch unit, a read / write control unit, and a storage array; The length of the signal transmission path of the second data input / output module is equal to the length of the signal transmission paths in the address latch unit, the read / write control unit, and the storage array.
6. The timing alignment circuit of claim 1, wherein, The first data input / output module and the second data input / output module are located in the same data input / output device.
7. A timing alignment circuit as claimed in claim 6, characterized in that The data input / output device has a clock signal input terminal, a latch signal output terminal, and a stored data output terminal; the clock signal input terminal is connected to the clock signal receiving module; the latch signal output terminal is connected to the data buffer module to output the first latch signal to the data buffer module; and the stored data output terminal is connected to the data buffer module to output data to the data buffer module.
8. A timing alignment circuit as claimed in claim 7, characterized in that The data input / output device includes: The address latch unit is connected to the clock signal receiving module. The address latch unit is configured to receive the clock control signal and transmit the clock control signal. The read / write control unit is connected to the address latch unit, receives the clock control signal transmitted by the address latch unit, and continues to transmit the clock control signal. A storage array is connected to the read / write control unit. The storage array is configured to generate the first latch signal after receiving the clock control signal and output the first latch signal to the data cache module.
9. The timing alignment circuit of claim 1, wherein, The first data input / output module comprises a command / address latch unit, a control logic unit, a row address / column address control logic unit and a storage array, the clock control signal sequentially passes through the command / address latch unit, the control logic unit, the row address / column address control logic unit and reaches the storage array, so that the storage array outputs data to the data buffer module.
10. A memory, comprising: The timing alignment circuit of any one of claims 1-9.