Level conversion circuit and chip
By introducing cross-coupled output units and clamping unit structures into the level conversion circuit, the problem of large area in traditional level conversion circuits is solved, achieving efficient area utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2025-04-28
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional level conversion circuits use multiple high-voltage transistors, resulting in a large footprint.
The structure employs a cross-coupled output unit and a clamping unit. The first clamping unit clamps the first coupling end of the cross-coupled output unit, and the second clamping unit clamps the second coupling end of the cross-coupled output unit, thereby reducing the use of high-voltage tubes.
This effectively reduces the use of high-voltage transistors and lowers the chip's area cost.
Smart Images
Figure CN224154208U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to a level conversion circuit and chip. Background Technology
[0002] Traditional conversion circuits such as Figure 1 As shown, it uses a branch consisting of resistor R, high-voltage transistor M7, and low-voltage transistor M8 to bias high-voltage transistors M5 and M6. The input signal Vin is transmitted to the output terminal through high-voltage transistors M1 and M2. The output signal Vout at the output terminal is latched by low-voltage transistors M3 and M4. The structure and principle are simple, but it uses five high-voltage transistors to achieve the conversion. However, the area of high-voltage transistors is large, so this conversion circuit has a large area implementation cost.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0004] The purpose of this invention is to provide a level conversion circuit and chip that can greatly reduce the area occupied.
[0005] To achieve the above objectives, a specific embodiment of this utility model provides the following technical solution: a level conversion circuit, comprising: an input unit, a cross-coupled output unit, a first clamping unit, and a second clamping unit. The cross-coupled output unit has a first coupling terminal and a second coupling terminal. The input unit is connected to a first voltage and the first and second coupling terminals of the cross-coupled output unit. The input unit alternately controls the switching between the first coupling terminal of the cross-coupled output unit and the first voltage, and between the first coupling terminal of the cross-coupled output unit and the second voltage, based on an input signal. The cross-coupled output unit is simultaneously connected to the second voltage. The first clamping unit is connected to the second voltage and the first coupling terminal of the cross-coupled output unit to clamp the voltage at the first coupling terminal. The second clamping unit is connected to the second voltage and the second coupling terminal of the cross-coupled output unit to clamp the voltage at the second coupling terminal.
[0006] In one or more embodiments of this utility model, the input unit includes an inverter, a first transistor, and a second transistor. The input terminal of the inverter is used to receive an input signal. The output terminal of the inverter is connected to the control terminal of the first transistor. The control terminal of the second transistor is connected to the input terminal of the inverter. The first terminal of the first transistor and the first terminal of the second transistor are connected to a first voltage. The second terminal of the first transistor is connected to the first coupling terminal of the cross-coupled output unit. The second terminal of the second transistor is connected to the second coupling terminal of the cross-coupled output unit.
[0007] In one or more embodiments of the present invention, the cross-coupled output unit includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to a second voltage. The control terminal of the fourth transistor is connected to the second terminal of the third transistor to form a first coupling terminal. The control terminal of the third transistor is connected to the second terminal of the fourth transistor to form a second coupling terminal.
[0008] In one or more embodiments of this utility model, the first clamping unit includes a first resistor, a first terminal of the first resistor being connected to a second voltage, and a second terminal of the first resistor being connected to a first coupling terminal; and / or
[0009] The second clamping unit includes a second resistor, the first end of which is connected to a second voltage, and the second end of which is connected to a second coupling terminal.
[0010] In one or more embodiments of this utility model, the first clamping unit includes a first resistor and a fifth transistor, wherein the first resistor and the fifth transistor are connected in series or in parallel between the second voltage and the first coupling terminal; and / or
[0011] The second clamping unit includes a second resistor and a seventh transistor, which are connected in series or in parallel between the second voltage and the second coupling terminal.
[0012] In one or more embodiments of this utility model, the first clamping unit includes a first resistor, a fifth transistor, and a sixth transistor, wherein the first resistor is connected in parallel with the fifth transistor and simultaneously connected in series with the sixth transistor between the second voltage and the first coupling terminal; and / or
[0013] The second clamping unit includes a second resistor, a seventh transistor, and an eighth transistor, wherein the second resistor and the seventh transistor are connected in parallel and simultaneously connected in series with the eighth transistor between the second voltage and the second coupling terminal.
[0014] In one or more embodiments of the present invention, the level conversion circuit includes a tail load unit, the first end of the tail load unit is connected to the input unit, and the second end of the tail load unit is connected to a first voltage.
[0015] In one or more embodiments of the present invention, the tail load unit includes a third resistor, the first end of the third resistor is connected to the input unit, and the second end of the third resistor is connected to a first voltage.
[0016] In one or more embodiments of this utility model, the level conversion circuit includes a capacitor, the first end of the capacitor being connected to a first coupling terminal, and the second end of the capacitor being connected to a second coupling terminal.
[0017] This utility model also discloses a chip, including the aforementioned level conversion circuit.
[0018] Compared with the prior art, the level conversion circuit and chip of this utility model clamp the first coupling terminal of the cross-coupled output unit through the first clamping unit and clamp the second coupling terminal of the cross-coupled output unit through the second clamping unit, ensuring a smooth level conversion process. Compared with the prior art, it greatly reduces the use of high-voltage tubes and reduces area costs. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a circuit diagram of a level conversion circuit in the prior art.
[0021] Figure 2 This is a circuit diagram of a level conversion circuit in one embodiment of the present invention.
[0022] Figure 3 This is a circuit diagram of a level conversion circuit in another embodiment of the present invention.
[0023] Figure 4 This is a circuit diagram of a level conversion circuit in another embodiment of the present invention. Detailed Implementation
[0024] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0025] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.
[0026] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.
[0027] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0028] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0029] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.
[0030] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.
[0031] like Figure 2 As shown, a level conversion circuit in one embodiment of the present invention includes: an input unit 10, a cross-coupled output unit 20, a first clamping unit 30, a second clamping unit 40, and a tail load unit 50.
[0032] The cross-coupled output unit 20 has a first coupling terminal a and a second coupling terminal b. The input unit 10 is connected to the first voltage through the tail load unit 50. That is, the first terminal of the tail load unit 50 is connected to the input unit 10, and the second terminal of the tail load unit 50 is connected to the first voltage. The input unit 10 is simultaneously connected to the input signal Vin and the first coupling terminal a and the second coupling terminal b of the cross-coupled output unit 20. The input unit 10 alternately controls the on / off state between the first coupling terminal a of the cross-coupled output unit 20 and the first voltage, and between the first coupling terminal a of the cross-coupled output unit 20 and the second voltage, based on the input signal Vin.
[0033] The cross-coupled output unit 20 is simultaneously connected to a second voltage. A first clamping unit 30 is connected to both the second voltage and the first coupling terminal a of the cross-coupled output unit 20 to clamp the voltage at the first coupling terminal a. A second clamping unit 40 is connected to both the second voltage and the second coupling terminal b of the cross-coupled output unit 20 to clamp the voltage at the second coupling terminal b. In one embodiment, the first voltage is ground, and the second voltage is the power supply voltage VDD in the high power domain. In other embodiments, the first and second voltages can be other voltages.
[0034] like Figure 2 As shown, the input unit 10 includes an inverter NOT, a first transistor M1, and a second transistor M2, and the tail load unit 50 includes a third resistor R3. The input terminal of the inverter NOT is used to receive the input signal Vin, the output terminal of the inverter NOT is connected to the control terminal of the first transistor M1, and the control terminal of the second transistor M2 is connected to the input terminal of the inverter NOT.
[0035] The first terminal of the first transistor M1 and the first terminal of the second transistor M2 are connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the first voltage. The second terminal of the first transistor M1 is connected to the first coupling terminal a of the cross-coupled output unit 20, and the second terminal of the second transistor M2 is connected to the second coupling terminal b of the cross-coupled output unit 20 to form an output terminal to generate the output signal Vout. In other embodiments, the tail load unit 50 may not be provided.
[0036] The input signal Vin is inverted by the inverter NOT and then input to the control terminal of the first transistor M1. The input signal Vin is directly input to the control terminal of the second transistor M2. That is, the control terminals of the first transistor M1 and the second transistor M2 receive a set of inverted signals. Under the control of this set of inverted signals, the first transistor M1 and the second transistor M2 are alternately turned on and off, thereby controlling the on / off state between the second terminal of the first transistor M1 and the first voltage, and between the second terminal of the second transistor M2 and the first voltage.
[0037] like Figure 2 As shown, the cross-coupled output unit 20 includes a third transistor M3 and a fourth transistor M4. The first terminal of the third transistor M3 and the first terminal of the fourth transistor M4 are connected to a second voltage. The control terminal of the fourth transistor M4 is connected to the second terminal of the third transistor M3 to form a first coupling terminal a. The control terminal of the third transistor M3 is connected to the second terminal of the fourth transistor M4 to form a second coupling terminal b.
[0038] like Figure 2 As shown, the first clamping unit 30 includes a first resistor R1, a fifth transistor M5, and a sixth transistor M6. The first resistor R1 is connected in parallel with the fifth transistor M5 and simultaneously connected in series with the sixth transistor M6 between the second voltage and the first coupling terminal a. The second clamping unit 40 includes a second resistor R2, a seventh transistor M7, and an eighth transistor M8. The second resistor R2 and the seventh transistor M7 are connected in parallel and simultaneously connected in series with the eighth transistor M8 between the second voltage and the second coupling terminal b.
[0039] In one embodiment, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are P-channel MOSFETs. The first transistor M1 and the second transistor M2 are N-channel MOSFETs.
[0040] The first terminal of the first transistor M1, the first terminal of the second transistor M2, the first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, the first terminal of the sixth transistor M6, the first terminal of the seventh transistor M7, and the first terminal of the eighth transistor M8 are the sources; the second terminals of the first transistor M1, the second terminal of the second transistor M2, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, the second terminal of the sixth transistor M6, the second terminal of the seventh transistor M7, and the second terminal of the eighth transistor M8 are the drains; the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are the gates.
[0041] The first terminal of the fifth transistor M5 is connected to the second voltage, the second terminal of the fifth transistor M5 is connected to the control terminal of the fifth transistor M5, the first terminal of the first resistor R1 is connected to the first terminal of the fifth transistor M5, and the second terminal of the first resistor R1 is connected to the second terminal of the fifth transistor M5 to form a parallel connection between the first resistor R1 and the fifth transistor M5.
[0042] The first terminal of the sixth transistor M6 is connected to the second terminal of the first resistor R1 to form a series connection between the sixth transistor M6 and the first resistor R1. The second terminal of the sixth transistor M6 is connected to the control terminal of the sixth transistor M6 and the second terminal of the sixth transistor M6 is connected to the first coupling terminal a.
[0043] The first terminal of the seventh transistor M7 is connected to the second voltage, the second terminal of the seventh transistor M7 is connected to the control terminal of the seventh transistor M7, the first terminal of the second resistor R2 is connected to the first terminal of the seventh transistor M7, and the second terminal of the second resistor R2 is connected to the second terminal of the seventh transistor M7, forming a parallel connection between the second resistor R2 and the seventh transistor M7.
[0044] The first terminal of the eighth transistor M8 is connected to the second terminal of the second resistor R2, forming a series connection between the eighth transistor M8 and the second resistor R2. The second terminal of the eighth transistor M8 is connected to the control terminal of the eighth transistor M8, and the second terminal of the eighth transistor M8 is connected to the second coupling terminal b.
[0045] The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all connected in a diode configuration. In other embodiments, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may also be diodes.
[0046] In other embodiments, in the first clamping unit 30, only a first resistor R1 may be provided, which is connected in parallel between the second voltage and the first coupling terminal a; in the second clamping unit 40, only a second resistor R2 may be provided, which is connected in parallel between the second voltage and the second coupling terminal b.
[0047] In other embodiments, in the first clamping unit 30, only a first resistor R1 and a fifth transistor M5 or a sixth transistor M6 may be provided, with the first resistor R1 and the fifth transistor M5 or the sixth transistor M6 connected in parallel and then connected in parallel between the second voltage and the first coupling terminal a; in the second clamping unit 40, only a second resistor R2 and a seventh transistor M7 or an eighth transistor M8 may be provided, with the second resistor R2 and the seventh transistor M7 or the eighth transistor M8 connected in parallel and then connected in parallel between the second voltage and the second coupling terminal b.
[0048] In other embodiments, in the first clamping unit 30, only a first resistor R1 and a fifth transistor M5 or a sixth transistor M6 may be provided, with the first resistor R1 and the fifth transistor M5 or the sixth transistor M6 connected in series between the second voltage and the first coupling terminal a; in the second clamping unit 40, only a second resistor R2 and a seventh transistor M7 or an eighth transistor M8 may be provided, with the second resistor R2 and the seventh transistor M7 or the eighth transistor M8 connected in series between the second voltage and the second coupling terminal b.
[0049] In other embodiments, such as Figure 3 As shown, the position of the first resistor R1 can be changed. The first resistor R1 can be connected in parallel with the fifth transistor M5 and then in series with the sixth transistor M6, or it can be connected in parallel with the sixth transistor M6 and then in series with the fifth transistor M5. The position of the second resistor R2 can be changed. The second resistor R2 can be connected in parallel with the seventh transistor M7 and then in series with the eighth transistor M8, or it can be connected in parallel with the eighth transistor M8 and then in series with the seventh transistor M7.
[0050] In other embodiments, the number of fifth transistors M5 or sixth transistors M6 connected in parallel with the first resistor R1 can be selected as needed; that is, multiple fifth transistors M5 or sixth transistors M6 can be connected in series and then in parallel with the first resistor R1. Similarly, the number of seventh transistors M7 or eighth transistors M8 connected in parallel with the second resistor R2 can be selected as needed; that is, multiple seventh transistors M7 or eighth transistors M8 can be connected in series and then in parallel with the second resistor R2. For example... Figure 4 As shown, there are two sixth transistors M6 connected in parallel with the first resistor R1, and two eighth transistors M8 connected in parallel with the second resistor R2.
[0051] In other embodiments, the number of fifth transistors M5 or sixth transistors M6 connected in series with the first resistor R1 can be selected as needed, that is, multiple fifth transistors M5 or sixth transistors M6 can be connected in series and then connected in series with the first resistor R1; the number of seventh transistors M7 or eighth transistors M8 connected in series with the second resistor R2 can be selected as needed, that is, multiple seventh transistors M7 or eighth transistors M8 can be connected in series and then connected in series with the second resistor R2.
[0052] like Figure 2 As shown, the level conversion circuit includes a capacitor C. The first end of capacitor C is connected to the first coupling terminal a, and the second end of capacitor C is connected to the second coupling terminal b. Capacitor C is used for filtering, ensuring that when the second voltage fluctuates or changes, the logic relationship between the output signal Vout and the second voltage does not change significantly, thus preventing any impact on the circuit output.
[0053] When the input signal Vin is low (e.g., 0V), the first transistor M1 is turned on, the second transistor M2 is turned off, the voltage at the first coupling terminal a is pulled low, and due to the presence of the first clamping unit 30, the voltage at the first coupling terminal a is clamped to a value that enables the fourth transistor M4 to turn on. The voltage at the second coupling terminal b is pulled high, the third transistor M3 is turned off, and the output voltage at the output terminal is the voltage of the high power supply domain.
[0054] When the input signal Vin transitions from a low level to a high level in the low power supply domain (e.g., 5V), the first transistor M1 turns off and the second transistor M2 turns on. At this time, the voltage at the first coupling terminal a is pulled high. Due to the presence of the first clamping unit 30, the voltage at the first coupling terminal a is pulled up to near the second voltage (power supply voltage VDD), causing the fourth transistor M4 to be in a weakly conducting state. The voltage at the second coupling terminal b is pulled down, and the third transistor M3 turns on, causing the voltage at the first coupling terminal a to be pulled up again to completely turn off the fourth transistor M4.
[0055] The first clamping unit 30 can limit the voltage difference between the first and second terminals of the third transistor M3, preventing the voltage difference between the first and second terminals of the third transistor M3 from becoming too large and burning out the third transistor M3 during level conversion. The fifth transistor M5 and the sixth transistor M6 do not need to use high-voltage transistors. The second clamping unit 40 works in the same way. Compared with the prior art, this embodiment only uses the first transistor M1 and the second transistor M2 as high-voltage transistors, without the need to use other high-voltage transistors, thereby greatly reducing the chip area occupied.
[0056] The tail load unit 50 can limit current and reduce the pull-down capability of the first transistor M1 and the second transistor M2. When the first transistor M1 or the second transistor M2 needs to be pulled down, it plays a buffering and mitigating role, ensuring that the first coupling terminal a or the second coupling terminal b will not see high voltage, and further reducing the power consumption of the overall circuit.
[0057] By setting the first resistor R1, it can be ensured that when the voltage at the first coupling terminal a needs to be pulled up to turn off the fourth transistor M4, the voltage at the first coupling terminal a can be pulled up to at least make the fourth transistor M4 weakly conduct, so as to cause the fourth transistor M4 to be turned off subsequently (if only the fifth transistor M5 and the sixth transistor M6 are set, when the voltage at the first coupling terminal a needs to rise to turn off the fourth transistor M4, the voltage generated by the fifth transistor M5 and the sixth transistor M6 is not enough to raise the voltage at the first coupling terminal a to turn off the fourth transistor M4, causing the fourth transistor M4 to remain on). The second resistor R2 works in the same way.
[0058] This invention also provides a chip, including the level conversion circuit described above.
[0059] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0060] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A level shifting circuit, characterized by, include: The system comprises an input unit, a cross-coupled output unit, a first clamping unit, and a second clamping unit. The cross-coupled output unit has a first coupling terminal and a second coupling terminal. The input unit is connected to a first voltage and the first and second coupling terminals of the cross-coupled output unit. The input unit alternately controls the switching between the first coupling terminal of the cross-coupled output unit and the first voltage, and between the first coupling terminal of the cross-coupled output unit and the second voltage, based on an input signal. The cross-coupled output unit is also connected to the second voltage. The first clamping unit is connected to the second voltage and the first coupling terminal of the cross-coupled output unit to clamp the voltage at the first coupling terminal. The second clamping unit is connected to the second voltage and the second coupling terminal of the cross-coupled output unit to clamp the voltage at the second coupling terminal.
2. The level shifting circuit of claim 1, wherein, The input unit includes an inverter, a first transistor, and a second transistor. The input terminal of the inverter is used to receive an input signal. The output terminal of the inverter is connected to the control terminal of the first transistor. The control terminal of the second transistor is connected to the input terminal of the inverter. The first terminal of the first transistor and the first terminal of the second transistor are connected to a first voltage. The second terminal of the first transistor is connected to the first coupling terminal of the cross-coupled output unit. The second terminal of the second transistor is connected to the second coupling terminal of the cross-coupled output unit.
3. The level shifting circuit of claim 1, wherein, The cross-coupled output unit includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to a second voltage. The control terminal of the fourth transistor is connected to the second terminal of the third transistor to form a first coupling terminal. The control terminal of the third transistor is connected to the second terminal of the fourth transistor to form a second coupling terminal.
4. The level shifting circuit of claim 1, wherein, The first clamping unit includes a first resistor, a first terminal of which is connected to a second voltage, and a second terminal of which is connected to a first coupling terminal; and / or The second clamping unit includes a second resistor, the first end of which is connected to a second voltage, and the second end of which is connected to a second coupling terminal.
5. The level shifting circuit of claim 1, wherein, The first clamping unit includes a first resistor and a fifth transistor, the first resistor and the fifth transistor being connected in series or in parallel between the second voltage and the first coupling terminal; and / or The second clamping unit includes a second resistor and a seventh transistor, which are connected in series or in parallel between the second voltage and the second coupling terminal.
6. The level shifting circuit of claim 1, wherein, The first clamping unit includes a first resistor, a fifth transistor, and a sixth transistor, wherein the first resistor is connected in parallel with the fifth transistor and simultaneously connected in series with the sixth transistor between the second voltage and the first coupling terminal; and / or The second clamping unit includes a second resistor, a seventh transistor, and an eighth transistor, wherein the second resistor and the seventh transistor are connected in parallel and simultaneously connected in series with the eighth transistor between the second voltage and the second coupling terminal.
7. The level shifting circuit of claim 1, wherein, The level conversion circuit includes a tail load unit, the first end of which is connected to the input unit, and the second end of which is connected to a first voltage.
8. The level shifting circuit of claim 7, wherein, The tail load unit comprises a third resistor, a first end of the third resistor being connected with the input unit, and a second end of the third resistor being connected with the first voltage.
9. The level shifting circuit of claim 1, wherein, The level conversion circuit comprises a capacitor, a first end of the capacitor being connected with the first coupling end, and a second end of the capacitor being connected with the second coupling end.
10. A chip, characterized by The level conversion circuit comprises a capacitor, a first end of the capacitor being connected with the first coupling end, and a second end of the capacitor being connected with the second coupling end.