Chip electrical performance test platform of FPGA (Field Programmable Gate Array)

Abstract

The utility model discloses an FPGA chip electrical performance test platform which comprises a base, a stand column is fixedly installed on the base, a test probe is arranged on the stand column, a disc is arranged on the base, a chip seat is movably installed on the disc, side grooves are formed in the two sides of the chip seat, a round rod is fixedly installed on the disc, and the round rod is fixedly installed on the base. The two sides of the outer surface of the round rod are movably sleeved with square rods, and clamping blocks are arranged on the square rods. According to one embodiment of the invention, through the arrangement of the square rods, the clamping blocks and the driving assembly, when a worker needs to dismount the chip seat for replacement, the two square rods can drive the two clamping blocks to move oppositely through the driving assembly, so that the two clamping blocks can be pulled out from the interior of the side groove, and then the limiting of the chip seat can be quickly relieved; compared with the prior art that a plurality of bolts are disassembled to replace the chip seat, the scheme is convenient and fast, and the overall test efficiency can be improved.

Description

An FPGA chip electrical performance testing platform Technical Field

[0001] This utility model relates to the field of chip testing technology, and more specifically, to an FPGA chip electrical performance testing platform. Background Technology

[0002] An FPGA chip is a programmable logic device. Its biggest feature is that its hardware functions can be flexibly defined by the user. It is widely used in scenarios that require rapid prototyping, flexible hardware configuration, or small-batch customization. Through semi-custom integrated circuits, users can program and define the functions of its internal logic circuits, realizing flexible design from simple logic gates to complex systems. During the production process of FPGA chips, workers need to test its electrical performance using an electrical performance testing platform.

[0003] However, existing technologies have some problems: when testing FPGA chips, existing electrical performance testing platforms require inserting the chip's pins into the electrical sockets of the chip socket on the platform before conducting electrical tests. Furthermore, staff often need to test chips of different sizes, which requires changing the chip socket to the corresponding size. However, the chip sockets of existing testing platforms are usually fixed with bolts, which makes disassembly cumbersome and affects the overall testing efficiency. Therefore, we propose an FPGA chip electrical performance testing platform. Summary of the Invention

[0004] One objective of this invention is to provide a new technical solution for an FPGA chip electrical performance testing platform.

[0005] According to a first aspect of this utility model, an FPGA chip electrical performance testing platform is provided, including a base, a column fixedly mounted on the base, a test probe disposed on the column, a disk disposed on the base, a chip holder movably mounted on the disk, side grooves being formed on both sides of the chip holder, a round rod fixedly mounted on the disk, and square rods movably sleeved on both sides of the outer surface of the round rod, with a locking block disposed on the square rod, one end of the locking block extending into the side groove, and the square rod and the disk being connected by a driving component, the driving component enabling the square rod to drive the locking block to move and release the chip holder from its limiting position.

[0006] Optionally, the drive assembly includes a handle rotatably connected to a disc, a disc fixedly sleeved on the outer surface of the handle, arc-shaped holes on both sides of the disc, a connecting rod fixedly mounted on the square rod, and a circular block located inside the arc-shaped hole fixedly mounted on the connecting rod.

[0007] Optionally, the circular block is slidably connected inside the arc-shaped hole, and the inner wall of the arc-shaped hole is coated with a lubricating layer.

[0008] Optionally, a spring is movably sleeved on the outer surface of the round rod, and the two ends of the spring are respectively fixedly connected to two square rods.

[0009] Optionally, a lead screw is threaded onto the square rod, one end of which is rotatably connected to a locking block. A guide rod is fixedly installed on the side of the locking block near the square rod, and the other end of the guide rod passes through the square rod.

[0010] Optionally, a brake motor is fixedly installed at the bottom of the base, and the output shaft of the brake motor is connected to a rotating shaft via a coupling. The top of the rotating shaft passes through the base and is connected to a disc.

[0011] According to one embodiment of this disclosure, by setting up square rods, locking blocks, and a drive assembly, when the operator needs to remove the chip socket for replacement, the drive assembly can cause the two square rods to drive the two locking blocks to move in opposite directions, thereby allowing the two locking blocks to be pulled out from the inside of the side slot, thus quickly releasing the restriction on the chip socket. Compared with the existing method of removing multiple bolts to replace the chip socket, this solution is convenient and quick, and can improve the overall testing efficiency.

[0012] Other features and advantages of the present invention will become clear from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present invention and, together with their description, serve to explain the principles of the present invention.

[0014] Figure 1 is a schematic diagram of the overall structure of an FPGA chip electrical performance testing platform in one embodiment;

[0015] Figure 2 is a schematic diagram of the top structure of an FPGA chip electrical performance testing platform in one embodiment;

[0016] Figure 3 is a front cross-sectional view of an FPGA chip electrical performance testing platform in one embodiment.

[0017] Figure 4 is a cross-sectional view of the internal structure of the chip socket of an FPGA chip electrical performance testing platform in one embodiment.

[0018] Figure 5 is a partial structural diagram of the top of the disk of an FPGA chip electrical performance testing platform in one embodiment.

[0019] The following are marked in the diagram: 1. Base; 2. Column; 3. Test probe; 4. Disc; 5. Chip holder; 6. Side groove; 7. Round rod; 8. Square rod; 9. Locking block; 10. Rotating handle; 11. Turntable; 12. Arc hole; 13. Connecting rod; 14. Round block; 15. Spring; 16. Lead screw; 17. Guide rod; 18. Brake motor; 19. Rotating shaft. Detailed Implementation

[0020] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0021] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0022] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0023] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0024] As shown in Figures 1-5, an FPGA chip electrical performance testing platform includes a base 1, a column 2 fixedly mounted on the base 1, a test probe 3 mounted on the column 2, a disk 4 mounted on the base 1, a chip holder 5 movably mounted on the disk 4, side slots 6 on both sides of the chip holder 5, a round rod 7 fixedly mounted on the disk 4, and square rods 8 movably sleeved on both sides of the outer surface of the round rod 7, with a locking block 9 mounted on the square rod 8, one end of the locking block 9 extending into the side slot 6. The square rod 8 and the disk 4 are also connected by a driving component, which enables the square rod 8 to drive the locking block 9 to move and release the chip holder 5 from its limit.

[0025] It should be noted that the test probe 3 can move on the column 2 via a drive component such as an electric slide rail, thereby contacting the test point on the chip holder 5 for testing. This is an existing mature technology and will not be elaborated here. By inserting the chip's pins into the electrical sockets on the chip holder 5, the electrical performance of the chip can be tested by the test probe 3.

[0026] The aforementioned FPGA chip electrical performance testing platform includes a drive component comprising a handle 10, which is rotatably connected to a disk 4. A turntable 11 is fixedly sleeved on the outer surface of the handle 10. Arc-shaped holes 12 are provided on both sides of the turntable 11. A connecting rod 13 is fixedly installed on a square rod 8, and a circular block 14 located inside the arc-shaped hole 12 is fixedly installed on the connecting rod 13.

[0027] By rotating the handle 10, the turntable 11 can be rotated, which causes the inner wall of the arc-shaped hole 12 to press against the outer surface of the round block 14. This causes the two round blocks 14 to drive the two connecting rods 13 to move in opposite directions, which in turn causes the two square rods 8 to drive the two locking blocks 9 to move in opposite directions. This allows one end of the locking block 9 to be pulled out from the side groove 6, thereby quickly releasing the restriction on the chip holder 5. This makes it easier for staff to replace chip holders 5 of different sizes to test different types of chips, thus improving work efficiency.

[0028] In the aforementioned FPGA chip electrical performance testing platform, the circular block 14 is slidably connected inside the arc-shaped hole 12, and the inner wall of the arc-shaped hole 12 is coated with a lubricating layer.

[0029] In the aforementioned FPGA chip electrical performance testing platform, a spring 15 is movably sleeved on the outer surface of the round rod 7, and the two ends of the spring 15 are respectively fixedly connected to two square rods 8.

[0030] By setting the spring 15 to a stretched state, the spring 15's elasticity will cause the two square rods 8 to tend to move towards each other, thereby keeping one end of the locking block 9 in the side groove 6 and keeping the rotating handle 10 stable, thus maintaining the limiting effect on the chip holder 5.

[0031] The above-mentioned FPGA chip electrical performance testing platform has a lead screw 16 threadedly connected to a square rod 8. One end of the lead screw 16 is rotatably connected to a clamping block 9. A guide rod 17 is fixedly installed on the side of the clamping block 9 near the square rod 8, and the other end of the guide rod 17 passes through the square rod 8.

[0032] When the chip holder 5 is small and the distance between the two square rods 8 is minimal, it is still impossible to insert the locking block 9 into the side slot 6 to limit the chip holder 5. The operator can rotate the lead screw 16 to adjust the distance between the two locking blocks 9, thereby limiting the chip holder 5 to a smaller size and improving its applicability.

[0033] The above-mentioned FPGA chip electrical performance testing platform has a brake motor 18 fixedly installed at the bottom of the base 1. The output shaft of the brake motor 18 is connected to a rotating shaft 19 through a coupling. The top of the rotating shaft 19 passes through the base 1 and is connected to the disk 4.

[0034] While a chip on one chip socket 5 is being tested, the operator can install another chip to be tested on another chip socket 5. After one chip has been tested, the operator can start the brake motor 18, which causes the rotating shaft 19 to drive the disk 4 to rotate, thereby swapping the positions of the two chips and continuing the testing work. The tested chip can then be removed. This process can be repeated to improve the overall testing efficiency.

[0035] Working principle and usage process of this utility model:

[0036] During testing, the operator can install the chip onto chip socket 5 and then perform electrical performance testing via test probe 3. While one chip on chip socket 5 is being tested, the operator can install another chip to be tested onto another chip socket 5. After one chip has finished testing, the operator can activate brake motor 18, causing shaft 19 to rotate disk 4, thereby swapping the positions of the two chips and continuing the testing process. The tested chip can then be removed. This process can be repeated to improve overall testing efficiency. When it is necessary to change chip socket 5 to test chips of different models and sizes, [the following steps can be taken]. Rotating the handle 10 causes the turntable 11 to rotate, which in turn causes the inner wall of the arc-shaped hole 12 to press against the outer surface of the round block 14. This causes the two round blocks 14 to move in opposite directions along the two connecting rods 13. Consequently, the two square rods 8 move in opposite directions along the two locking blocks 9 and stretch the spring 15. This allows one end of the locking block 9 to be pulled out from the side groove 6, thus quickly releasing the chip holder 5 from its position. After replacing the chip holder 5, the locking block 9 is inserted back into the side groove 6 to reposition the chip holder 5. This facilitates the replacement of chip holders 5 of different sizes and models for testing different types of chips, improving work efficiency.

[0037] Although specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An FPGA chip electrical performance testing platform, comprising a base (1), wherein a column (2) is fixedly mounted on the base (1), and test probes (3) are disposed on the column (2), characterized in that: A disc (4) is provided on the base (1), and a chip holder (5) is movably installed on the disc (4). Side grooves (6) are provided on both sides of the chip holder (5). A round rod (7) is fixedly installed on the disc (4). A square rod (8) is movably sleeved on both sides of the outer surface of the round rod (7). A locking block (9) is provided on the square rod (8). One end of the locking block (9) extends into the side groove (6). The square rod (8) and the disc (4) are also connected by a drive assembly. The drive assembly enables the square rod (8) to drive the locking block (9) to move and release the limiting position on the chip holder (5).

2. The FPGA chip electrical performance testing platform according to claim 1, characterized in that: The drive assembly includes a handle (10) which is rotatably connected to a disc (4). A turntable (11) is fixedly sleeved on the outer surface of the handle (10). Arc-shaped holes (12) are provided on both sides of the turntable (11). A connecting rod (13) is fixedly installed on the square rod (8). A round block (14) located inside the arc-shaped hole (12) is fixedly installed on the connecting rod (13).

3. The chip electrical performance test platform of claim 2, wherein: The circular block (14) is slidably connected inside the arc-shaped hole (12), the inner wall of which is coated with a lubricating layer.

4. The chip electrical performance test platform of claim 1, wherein: A spring (15) is movably sleeved on the outer surface of the round rod (7), and the two ends of the spring (15) are respectively fixedly connected to two square rods (8).

5. The FPGA chip electrical performance testing platform according to claim 1, characterized in that: A lead screw (16) is threaded onto the square rod (8). One end of the lead screw (16) is rotatably connected to the locking block (9). A guide rod (17) is fixedly installed on the side of the locking block (9) near the square rod (8). The other end of the guide rod (17) passes through the square rod (8).

6. The chip electrical performance test platform of claim 1, wherein: A brake motor (18) is fixedly installed at the bottom of the base (1). The output shaft of the brake motor (18) is connected to a rotating shaft (19) via a coupling. The top of the rotating shaft (19) passes through the base (1) and is connected to the disc (4).

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