Super capacitor charging circuit and computer equipment

Abstract

The utility model discloses a super capacitor charging circuit and a computer device. The super capacitor charging circuit comprises an SEPIC control circuit, a multi-path super capacitor module, a voltage-sharing loop, a voltage feedback loop and a current feedback loop. The input end of the SEPIC control circuit receives input voltage, and the output end of the SEPIC control circuit is connected with the multi-channel super capacitor module; the voltage-sharing loop is connected with the multi-path super capacitor module and the SEPIC control circuit; the voltage feedback loop is connected with the multi-path super capacitor module and the SEPIC control circuit; the current feedback loop is connected with the multi-path super capacitor module and the SEPIC control circuit. According to the embodiment of the utility model, the SEPIC control circuit can charge the plurality of super capacitors connected in series in the multi-path super capacitor module in a voltage-sharing and constant-current manner by using the input voltage provided by the input power supply, so that the charging efficiency is improved, the service life of the super capacitors is prolonged, and the circuit is low in complexity and low in cost.

Description

Technical Field

[0001] This utility model relates to the field of supercapacitor charging technology, specifically to supercapacitor charging circuits and computer equipment. Background Technology

[0002] In industrial environments where high computer data security is required, computers need to remain powered for a period of time after the adapter power is disconnected. During this period, a backup power supply should be activated promptly or data should be saved in an emergency to ensure no data loss. This technology is called delayed power supply or time-delay power supply. Supercapacitors, as highly efficient energy storage components, are well-suited for use as delayed power supplies for computers due to their high power density, rapid charging and discharging characteristics, and long lifespan.

[0003] Currently, the commonly used supercapacitor charging scheme involves directly charging the supercapacitor using current-limiting resistors. This scheme uses multiple sets of current-limiting resistors to control the charging process, thereby allowing multiple supercapacitors to be charged in series. However, existing supercapacitor charging schemes generally suffer from the following problems:

[0004] 1) Constant current charging is difficult to achieve. That is, existing charging circuit designs usually provide high current in the early stage of supercapacitor charging, but as the voltage rises, the charging current gradually decreases, resulting in reduced charging efficiency.

[0005] 2) Voltage equalization problem: When multiple supercapacitors are charged in parallel, the voltage imbalance between the capacitors may cause some capacitors to be overcharged or undercharged, affecting the stability of the system and the lifespan of the supercapacitors.

[0006] 3) Circuit design complexity: Achieving constant current charging and equal voltage charging typically requires additional control circuitry or dedicated ICs, which increases circuit complexity and cost. 。 Summary of the Invention

[0007] This invention provides a supercapacitor charging circuit and computer equipment, aiming to solve the problems in the prior art where constant current and voltage equalization charging are difficult to achieve when using a current-limiting resistor to directly charge a supercapacitor, and the complexity of the circuit leads to increased equipment costs.

[0008] In a first aspect, this utility model proposes a supercapacitor charging circuit, comprising: a SEPIC control circuit, a multi-channel supercapacitor module, a voltage equalization loop, a voltage feedback loop, and a current feedback loop; the input terminal of the SEPIC control circuit receives an input voltage, and the output terminal of the SEPIC control circuit is connected to the multi-channel supercapacitor module; the voltage equalization loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit; the voltage feedback loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit; the current feedback loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit; the SEPIC control circuit is used to perform voltage equalization and constant current charging of multiple supercapacitors connected in series in the multi-channel supercapacitor module using the input voltage provided by the input power supply.

[0009] Furthermore, the SEPIC control circuit includes a SEPIC controller, a filter, a SEPIC inductor, a SEPIC controller back-end network, a MOS switch, and a precision resistor. The input terminal of the SEPIC controller is connected to the input voltage through the filter. The input terminal of the SEPIC inductor is connected to the input voltage through the filter, and the output terminal of the SEPIC inductor is connected to the SEPIC controller back-end network. The output terminal of the SEPIC inductor is also grounded through the MOS switch and the precision resistor. The number of SEPIC controller back-end circuits included in the SEPIC controller back-end network is the same as the number of supercapacitors included in the multi-channel supercapacitor module, and the two ends of each SEPIC controller back-end circuit are respectively connected to the two ends of a supercapacitor uniquely corresponding to the multi-channel supercapacitor module.

[0010] Furthermore, the SEPIC control circuit also includes a first resistor, a first capacitor, a first diode, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a second capacitor; the VCC pin of the SEPIC controller is connected to the output terminal of the filter through the first resistor, and the VCC pin of the SEPIC controller is also grounded through the first capacitor; the GND pin of the SEPIC controller is grounded; the Gate pin of the SEPIC controller is connected to the gate of the MOS switch through the second resistor; the cathode of the first diode is connected to the Gate pin of the SEPIC controller, and the anode of the first diode is connected to the gate of the MOS switch; the ISENSE pin of the SEPIC controller is grounded through the precision resistor; the FB pin of the SEPIC controller is connected to the first end of the third resistor and the first end of the second capacitor, and is also grounded through the fifth resistor; the second end of the third resistor is connected to the voltage equalization circuit; the second end of the second capacitor is connected to the voltage equalization circuit through the fourth resistor; the drain of the MOS switch is connected to the output terminal of the SEPIC inductor, and the source of the MOS switch is grounded through the precision resistor.

[0011] Furthermore, the filter is a π-type filter, and the π-type filter includes a first inductor, a third capacitor, a fourth capacitor, and a fifth capacitor; the first terminal of the first inductor is connected to the input voltage, the second terminal of the first inductor is connected to the input terminal of the SEPIC inductor, and the second terminal of the first inductor is also connected to the VCC pin of the SEPIC controller through the first resistor; the first terminal of the third capacitor is connected to the first terminal of the first inductor, and the second terminal of the third capacitor is grounded; the first terminal of the fourth capacitor is connected to the second terminal of the first inductor, and the second terminal of the fourth capacitor is grounded; the first terminal of the fifth capacitor is connected to the second terminal of the first inductor, and the second terminal of the fifth capacitor is grounded.

[0012] Furthermore, the voltage equalization circuit is a voltage equalization diode; the positive terminal of the voltage equalization diode is connected to the second terminal of the third resistor, and the negative terminal of the voltage equalization diode is connected to the input terminal of the SEPIC inductor.

[0013] Furthermore, the multi-channel supercapacitor module includes a first supercapacitor, a second supercapacitor, a third supercapacitor, a fourth supercapacitor, a fifth supercapacitor, a sixth resistor, and a sixth capacitor; the input terminal of the first supercapacitor is connected to the second terminal of the third resistor, and the input terminal of the first supercapacitor is also grounded through the sixth capacitor; the output terminal of the first supercapacitor is connected to the input terminal of the second supercapacitor; the output terminal of the second supercapacitor is connected to the input terminal of the third supercapacitor; the output terminal of the third supercapacitor is connected to the input terminal of the fourth supercapacitor; the output terminal of the fourth supercapacitor is connected to the input terminal of the fifth supercapacitor; and the output terminal of the fifth supercapacitor is grounded through the sixth resistor.

[0014] Furthermore, the input terminal of the first supercapacitor is also connected to the input terminal of the first SEPIC controller back-end circuit in the SEPIC controller back-end network, and the output terminal of the first supercapacitor is also connected to the output terminal of the first SEPIC controller back-end circuit; the input terminal of the second supercapacitor is also connected to the input terminal of the second SEPIC controller back-end circuit in the SEPIC controller back-end network, and the output terminal of the second supercapacitor is also connected to the output terminal of the second SEPIC controller back-end circuit; the input terminal of the third supercapacitor is also connected to the input terminal of the third SEPIC controller back-end circuit in the SEPIC controller back-end network, and the output terminal of the third supercapacitor is also connected to the output terminal of the third SEPIC controller back-end circuit; the input terminal of the fourth supercapacitor is also connected to the input terminal of the fourth SEPIC controller back-end circuit in the SEPIC controller back-end network, and the output terminal of the fourth supercapacitor is also connected to the output terminal of the fourth SEPIC controller back-end circuit; the input terminal of the fifth supercapacitor is also connected to the input terminal of the fifth SEPIC controller back-end circuit in the SEPIC controller back-end network, and the output terminal of the fifth supercapacitor is also connected to the output terminal of the fifth SEPIC controller back-end circuit.

[0015] Furthermore, the voltage feedback loop includes a voltage comparator and an error amplifier; the positive input terminal of the voltage comparator is connected to the FB pin of the SEPIC controller, and the negative input terminal of the voltage comparator receives a preset upper limit voltage; the negative input terminal of the error amplifier receives a preset lower limit voltage, and the positive input terminal of the error amplifier is connected to the FB pin of the SEPIC controller.

[0016] Furthermore, the current feedback loop includes an amplifier circuit and a comparison integrator circuit; the positive input terminal of the amplifier circuit is connected to the first terminal of the sixth resistor, and the negative input terminal of the amplifier circuit is connected to the second terminal of the sixth resistor; the output terminal of the amplifier circuit is connected to the positive input terminal of the comparison integrator circuit, and also to the output terminal of the fifth supercapacitor; a reference voltage is input to the negative input terminal of the comparison integrator circuit, and the output terminal of the comparison integrator circuit is connected to the FB pin of the SEPIC controller.

[0017] Secondly, this utility model also proposes a computer device, including the supercapacitor charging circuit described in the first aspect.

[0018] Compared with existing technologies, this invention provides a supercapacitor charging circuit and computer equipment, including a SEPIC control circuit, a multi-channel supercapacitor module, a voltage equalization loop, a voltage feedback loop, and a current feedback loop. The input terminal of the SEPIC control circuit receives the input voltage, and the output terminal of the SEPIC control circuit is connected to the multi-channel supercapacitor module. The voltage equalization loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit. The voltage feedback loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit. The current feedback loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit. In the embodiments of this invention, the SEPIC control circuit can use the input voltage provided by the input power supply to perform equal-voltage constant-current charging on multiple supercapacitors connected in series in the multi-channel supercapacitor module, thereby improving charging efficiency, extending the service life of the supercapacitors, and having low circuit complexity and low cost. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic block diagram of the supercapacitor charging circuit provided by this utility model;

[0021] Figure 2 The circuit structure diagram of the SEPIC control circuit in the supercapacitor charging circuit provided by this utility model;

[0022] Figure 3 The circuit structure diagram of the multi-channel supercapacitor module in the supercapacitor charging circuit provided by this utility model is shown.

[0023] Figure 4This is a schematic block diagram of the back-end network of the SEPIC control circuit in the supercapacitor charging circuit provided by this utility model.

[0024] Figure 5 The circuit structure diagram of the back-end circuit of the first SEPIC control circuit in the supercapacitor charging circuit provided by this utility model;

[0025] Figure 6 The circuit structure diagram of the voltage feedback loop in the supercapacitor charging circuit provided by this utility model is shown.

[0026] Figure 7 This is a schematic block diagram of the current feedback loop in the supercapacitor charging circuit provided by this utility model. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0028] The directional terms used in this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for explanation and understanding of this invention, and not for limiting it. Furthermore, in the accompanying drawings, structures that are similar or identical are indicated by the same reference numerals.

[0029] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0030] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0031] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0032] Please see Figure 1 This is a schematic block diagram of the supercapacitor charging circuit provided by this utility model. Figure 1 As shown, the supercapacitor charging circuit 10 provided in this embodiment of the present invention is applied to computer equipment. It includes: a SEPIC control circuit 11, a multi-channel supercapacitor module 12, a voltage equalization loop 13, a voltage feedback loop 14, and a current feedback loop 15. The input terminal of the SEPIC control circuit 11 receives the input voltage, and the output terminal of the SEPIC control circuit 11 is connected to the multi-channel supercapacitor module 12. The voltage equalization loop 13 is connected to both the multi-channel supercapacitor module 12 and the SEPIC control circuit 11. The voltage feedback loop 14 is connected to both the multi-channel supercapacitor module 12 and the SEPIC control circuit 11. The current feedback loop 15 is connected to both the multi-channel supercapacitor module 12 and the SEPIC control circuit 11. The SEPIC control circuit 11 is used to perform voltage equalization and constant current charging of the multiple supercapacitors connected in series in the multi-channel supercapacitor module 12 using the input voltage provided by the input power supply 20.

[0033] In this embodiment, the SEPIC control circuit 11 may include multiple protection circuits, the total number of which is the same as the total number of supercapacitors connected in series in the multi-channel supercapacitor module 12. Specifically, each supercapacitor is connected in parallel to a protection circuit. After a single supercapacitor is fully charged and its voltage reaches a protection voltage value, the protection circuit connected in parallel with it is activated, causing the current to bypass the independent line where the supercapacitor is located and stopping the charging of that supercapacitor. Furthermore, the protection circuit provides power to the subsequent supercapacitors. Moreover, the voltage equalization circuit 13, voltage feedback circuit 14, and current feedback circuit 15 ensure that the charging voltage of each supercapacitor in the multi-channel supercapacitor module 12 is within a set voltage range, and the charging current fluctuates around a set value. This achieves simultaneous equalized constant-current charging of multiple supercapacitors, improving charging efficiency while protecting the supercapacitors and reducing their lifespan. The input voltage received at the input terminal of the SEPIC control circuit 11 is provided by an adapter. Specifically, the adapter can be connected to mains power to convert AC power to DC power.

[0034] In one embodiment, such as Figure 1 and Figure 2As shown, the SEPIC control circuit 11 includes a SEPIC controller U1, a filter 111, a SEPIC inductor L0, a SEPIC controller back-end network 112, a MOS switch Q1, and a precision resistor R0. The input terminal of the SEPIC controller U1 is connected to the input voltage (which can be represented by VCC12_IN) through the filter 11. The input terminal of the SEPIC inductor L0 is connected to the input voltage through the filter 111. The output terminal of the SEPIC inductor L0 is connected to the SEPIC controller back-end network, and the output terminal of the SEPIC inductor L0 is also grounded through the MOS switch Q1 and the precision resistor R0. The number of SEPIC controller back-end circuits included in the SEPIC controller back-end network 112 is the same as the number of supercapacitors included in the multi-channel supercapacitor module 12, and the two ends of each SEPIC controller back-end circuit are respectively connected to the two ends of a supercapacitor uniquely corresponding to the multi-channel supercapacitor module.

[0035] In this embodiment, the SEPIC control circuit 11 is the main control part of the entire circuit. It is used to realize DC-DC voltage conversion (i.e., DC to DC voltage conversion), and also to receive input voltage, voltage control signal, current control signal and voltage equalization control, and output multiple SEPIC voltages to charge multiple supercapacitors. The front end of the SEPIC control circuit 11 consists of SEPIC controller U1, filter 111, SEPIC inductor L0, MOS switch Q1 and precision resistor R0, etc., while the back end is the SEPIC controller back-end network 112. The input voltage provided by the adapter is filtered and then supplies power to SEPIC inductor L0. One output of SEPIC inductor L0 is connected to ground through MOS switch Q1 (in specific implementation, NMOS transistor, etc.) and precision resistor R0. MOS switch Q1 is controlled by SEPIC controller U1. The positive terminal of precision resistor R0 is connected to the ISENSE pin of SEPIC controller U1 for overcurrent protection. The other output of SEPIC inductor L0 is connected to the SEPIC controller back-end network 112 through PH_SEPIC network. The SEPIC controller backend network 112 is also connected to the VIIN pin of the SEPIC controller U1 via a voltage equalization loop 13. During the period when the MOS switch Q1 is closed, voltage is released to the VIIN pin of the SEPIC controller U1 through the voltage equalization loop 13. At the start of the next switching cycle, the MOS switch Q1 opens, reallocating the charging voltage to each supercapacitor in the multi-channel supercapacitor module 12, allowing each supercapacitor to recharge. The MOS switch Q1 closes again, and the supercapacitors transfer their internal energy to the subsequent circuitry. Given the relatively small tolerances of the multi-channel supercapacitors, the energy transferred to the subsequent circuitry will be roughly the same. Through the continuous switching process of the MOS switch Q1, the energy distribution among the multi-channel supercapacitors is made more uniform, ultimately achieving a balanced distribution of the voltage values ​​of each supercapacitor during charging.

[0036] In one embodiment, such as Figure 1-2As shown, the SEPIC control circuit 11 further includes a first resistor R1, a first capacitor C1, a first diode D1, a second resistor R2, a third resistor R4, a fourth resistor R5, a fifth resistor R5, and a second capacitor C2; the VCC pin of the SEPIC controller U1 is connected to the output terminal of the filter 111 through the first resistor R1, and the VCC pin of the SEPIC controller U1 is also grounded through the first capacitor C1; the GND pin of the SEPIC controller U1 is grounded; the Gate pin of the SEPIC controller U1 is connected to the gate of the MOS switch Q1 through the second resistor R2; the cathode of the first diode D1 is connected to the SEPIC controller U1. The Gate pin of the first diode D1 is connected to the gate of the MOS switch Q1; the ISENSE pin of the SEPIC controller U1 is grounded through the precision resistor R0; the FB pin of the SEPIC controller U1 is connected to the first end of the third resistor R3 and the first end of the second capacitor C2, and is also grounded through the fifth resistor R5; the second end of the third resistor R3 is connected to the voltage equalization circuit; the second end of the second capacitor C2 is connected to the voltage equalization circuit through the fourth resistor R4; the drain of the MOS switch Q1 is connected to the output terminal of the SEPIC inductor L0, and the source of the MOS switch Q1 is grounded through the precision resistor R0.

[0037] In this embodiment, the SEPIC controller backend network 112 is also connected to the FB pin of the SEPIC controller U1 through the third resistor R3 and the fifth resistor R5, so as to control the charging voltage by providing the voltage of up to multiple supercapacitors within the target voltage range through the voltage feedback loop 14, thereby completing the voltage feedback loop.

[0038] In one embodiment, such as Figure 2 As shown, the filter 111 is a π-type filter, and the π-type filter includes a first inductor L1, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5; the first terminal of the first inductor L1 is connected to the input voltage, the second terminal of the first inductor L1 is connected to the input terminal of the SEPIC inductor L0, and the second terminal of the first inductor L1 is also connected to the VCC pin of the SEPIC controller U1 through the first resistor R1; the first terminal of the third capacitor C3 is connected to the first terminal of the first inductor L1, and the second terminal of the third capacitor C3 is grounded; the first terminal of the fourth capacitor C4 is connected to the second terminal of the first inductor L1, and the second terminal of the fourth capacitor C4 is grounded; the first terminal of the fifth capacitor C5 is connected to the second terminal of the first inductor L1, and the second terminal of the fifth capacitor C5 is grounded.

[0039] In this embodiment, when filter 111 adopts a π-type filter with the above circuit structure, both its input and output have low impedance, which can effectively filter the input voltage to provide a more stable voltage to the subsequent circuit.

[0040] In specific implementation, such as Figure 1 and Figure 2 As shown, the SEPIC control circuit 11 further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a seventh capacitor C7, and an eighth capacitor C8. The first end of the seventh resistor is connected to the second end of the first inductor L1, and the second end of the seventh resistor is connected to the EN / SYNC pin of the SEPIC controller U1. The first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor is grounded. The first end of the ninth resistor R9 is connected to the RT pin of the SEPIC controller U1, and the second end of the ninth resistor is grounded. The first end of the seventh capacitor C7 is connected to the SS pin of the SEPIC controller U1, and the second end of the seventh capacitor C7 is grounded. The first end of the eighth capacitor C8 is connected to the COMP pin of the SEPIC controller U1, and the second end of the eighth capacitor C8 is grounded through the tenth resistor R10. This circuit structure enables the SEPIC control circuit to provide more stable control functions.

[0041] In one embodiment, such as Figure 1 and Figure 2 As shown, the voltage equalization circuit 13 is a voltage equalization diode D0; the positive terminal of the voltage equalization diode D0 is connected to the second terminal of the third resistor R3, and the negative terminal of the voltage equalization diode D0 is connected to the input terminal of the SEPIC inductor L0.

[0042] In this embodiment, the voltage distribution of the output to the SEPIC inductor L0 and the VIN pin of the SEPIC controller U1 is made uniform by the voltage equalization diode D0 in the voltage equalization circuit 13, which prevents some components from being subjected to excessive voltage, thereby protecting the entire circuit and improving its stability and reliability.

[0043] In one embodiment, such as Figures 1-3As shown, the multi-channel supercapacitor module 12 includes a first supercapacitor CE1, a second supercapacitor CE2, a third supercapacitor CE3, a fourth supercapacitor CE4, a fifth supercapacitor CE5, a sixth resistor R6, and a sixth capacitor C6. The input terminal of the first supercapacitor CE1 is connected to the second terminal of the third resistor R3, and the input terminal of the first supercapacitor CE1 is also grounded through the sixth capacitor C6. The output terminal of the first supercapacitor CE1 is connected to the input terminal of the second supercapacitor CE2. The output terminal of the second supercapacitor CE2 is connected to the input terminal of the third supercapacitor CE3. The output terminal of the third supercapacitor CE3 is connected to the input terminal of the fourth supercapacitor CE4. The output terminal of the fourth supercapacitor CE4 is connected to the input terminal of the fifth supercapacitor CE5. The output terminal of the fifth supercapacitor CE5 is grounded through the sixth resistor R6.

[0044] In this embodiment, the purpose of this application, as the target control object (i.e., the target control circuit), is to achieve equalized constant current charging of the multi-channel supercapacitor module 12. To achieve this purpose, taking the multi-channel supercapacitor module 12 as an example, which includes a first supercapacitor CE1, a second supercapacitor CE2, a third supercapacitor CE3, a fourth supercapacitor CE4, and a fifth supercapacitor CE5 connected in series, both ends of the above five supercapacitors can be connected to a SEPIC controller back-end circuit. Moreover, the input end of the first supercapacitor CE1 is connected to the output end of the SEPIC inductor L0, which is used as the voltage output end of the supercapacitor discharge circuit. The input end of the first supercapacitor CE1 is also connected to the output voltage node and the equalized voltage circuit node of the voltage feedback loop 14. The sixth resistor R6 connected to the output end of the fifth supercapacitor CE5 serves as a sampling resistor. By taking points at both ends of the sampling resistor, current sampling can be achieved and input to the current feedback loop 15 for corresponding current control. The second end of the fifth supercapacitor CE5 is also connected to the first short-circuit copper foil SP1 and the first current limiting resistor (in Figure 3 (Not shown in the figure) is connected to the current feedback loop 15. The second end of the fifth supercapacitor CE5 is also connected to the current feedback loop 15 through the second short-circuit copper foil SP2 and the second current limiting resistor, and the current is sampled through the current feedback loop 15.

[0045] In one embodiment, such as Figures 1-4As shown, the input terminal of the first supercapacitor CE1 is also connected to the input terminal of the first SEPIC controller back-end circuit 1121 in the SEPIC controller back-end network 112, and the output terminal of the first supercapacitor CE1 is also connected to the output terminal of the first SEPIC controller back-end circuit 1121; the input terminal of the second supercapacitor CE2 is also connected to the input terminal of the second SEPIC controller back-end circuit 1122 in the SEPIC controller back-end network 112, and the output terminal of the second supercapacitor CE2 is also connected to the output terminal of the second SEPIC controller back-end circuit 1122; the input terminal of the third supercapacitor CE3 is also connected to the input terminal of the third SEPIC controller back-end circuit 1122 in the SEPIC controller back-end network 112. The input terminal of the third supercapacitor CE3 is connected to the input terminal of the third SEPIC controller back-end circuit 1123; the input terminal of the fourth supercapacitor CE4 is connected to the input terminal of the fourth SEPIC controller back-end circuit 1124 in the SEPIC controller back-end network 112, and the output terminal of the fourth supercapacitor CE4 is connected to the output terminal of the fourth SEPIC controller back-end circuit 1124; the input terminal of the fifth supercapacitor CE5 is connected to the input terminal of the fifth SEPIC controller back-end circuit 1125 in the SEPIC controller back-end network 112, and the output terminal of the fifth supercapacitor CE5 is connected to the output terminal of the fifth SEPIC controller back-end circuit 1125.

[0046] In this embodiment, when the five supercapacitors of the multi-channel supercapacitor module 12 are connected in series sequentially, the five SEPIC controller back-end circuits included in the SEPIC controller back-end network 112 are each connected to the two ends of one supercapacitor. The voltage equalization loop 13, voltage feedback loop 14, and current feedback loop 15 are connected to the output terminal of the first supercapacitor CE1. The voltage equalization loop 13 feeds back the voltage to the FB pin of the SEPIC controller U1 through a voltage equalization diode. The voltage feedback loop 14 includes an output voltage control signal, an output voltage node, and an output voltage feedback node. The current feedback loop 15 is connected to the output terminal of the fifth supercapacitor CE5, connected in series with a sampling resistor and then grounded. Current is sampled from both ends of the sampling resistor. Therefore, the SEPIC control circuit used in this application is a single-switch control multi-output SEPIC controller, which can simultaneously perform equal-voltage constant-current charging on multiple supercapacitors in the multi-channel supercapacitor module, improving charging efficiency while protecting the supercapacitors and reducing their lifespan.

[0047] In specific embodiments, such as Figure 2 , Figure 3and Figure 5 As shown, taking the specific circuit structure of the first SEPIC controller back-end circuit 1121 in the SEPIC controller back-end network 112 as an example, the first SEPIC controller back-end circuit 1121 includes a ninth capacitor C9, an eleventh resistor R11, a first voltage equalizing diode D2, a second inductor L2, a tenth capacitor C10, an eleventh capacitor C11, and a twelfth capacitor C12; the first terminal of the ninth capacitor C9 is connected to the output terminal of the SEPIC inductor L0, and the second terminal of the ninth capacitor C9 is connected to the first terminal of the eleventh resistor R11; the second terminal of the eleventh resistor R11 is connected to the positive terminal of the first voltage equalizing diode D2, and the second terminal of the eleventh resistor R11 is also connected to the first terminal of the eleventh resistor D2. The first terminal of the second inductor L2 is connected; the cathode of the first voltage equalizing diode D2 is connected to the second terminal of the third resistor R3; the second terminal of the second inductor L2 is connected to the output terminal of the fourth supercapacitor CE4; the first terminal of the tenth capacitor C10 is connected to the cathode of the first voltage equalizing diode D2, and the second terminal of the tenth capacitor C10 is connected to the second terminal of the second inductor L2; the first terminal of the eleventh capacitor C11 is connected to the cathode of the first voltage equalizing diode D2, and the second terminal of the eleventh capacitor C11 is connected to the second terminal of the second inductor L2; the first terminal of the twelfth capacitor C12 is connected to the cathode of the first voltage equalizing diode D2, and the second terminal of the twelfth capacitor C12 is connected to the second terminal of the second inductor L2. Through the above-described SEPIC controller back-end circuit, the energy distribution of multiple supercapacitors can be more evenly distributed by combining the continuous switching process of the MOS switch, ultimately achieving a balanced distribution of the voltage values ​​of each supercapacitor during charging. The circuit structure of the remaining four SEPIC controller back-end circuits in the SEPIC controller back-end network 112 is exactly the same as the specific circuit structure and working principle of the first SEPIC controller back-end circuit 1121, and will not be described again here.

[0048] In one embodiment, such as Figure 1 , Figure 2 and Figure 6 As shown, the voltage feedback loop 14 includes a voltage comparator COMP1 and an error amplifier EA; the positive input terminal of the voltage comparator COMP1 is connected to the FB pin of the SEPIC controller U1, and the negative input terminal of the voltage comparator COMP1 receives a preset upper limit voltage; the negative input terminal of the error amplifier EA receives a preset lower limit voltage, and the positive input terminal of the error amplifier EA is connected to the FB pin of the SEPIC controller U1.

[0049] In this embodiment, the voltage comparator COMP1 and error amplifier EA in the voltage feedback loop 14 ensure that the voltage supplied to multiple supercapacitors is within the target voltage range, thereby achieving charging voltage control and completing the voltage feedback loop. For example, if the target voltage range is 1.237V to 1.438V, the voltage feedback loop 14 can ensure that the voltage supplied to multiple supercapacitors is within this range. When the voltage fed back from the FB pin of the SEPIC controller U1 does not reach 1.237V, the SEPIC controller U1 controls the duty cycle of the MOS switch Q1, causing the output voltage to continuously increase until the voltage fed back from the FB pin reaches 1.237V.

[0050] In one embodiment, such as Figure 1 , Figure 2 , Figure 3 and Figure 7 As shown, the current feedback loop 15 includes an amplifier circuit 151 and a comparison integrator circuit 152; the positive input terminal of the amplifier circuit 151 is connected to the first terminal of the sixth resistor R6, and the negative input terminal of the amplifier circuit 151 is connected to the second terminal of the sixth resistor R6; the output terminal of the amplifier circuit 151 is connected to the positive input terminal of the comparison integrator circuit 152, and also to the output terminal of the fifth supercapacitor CE5; the negative input terminal of the comparison integrator circuit 152 receives a reference voltage, and the output terminal of the comparison integrator circuit is connected to the FB pin of the SEPIC controller.

[0051] In this embodiment, the current feedback loop 15 is used to control the charging current of the multi-channel supercapacitor module 12 to achieve constant current charging. The voltage signals of Isense+ and Isense- are sampled, and the operational amplifier corresponding to the amplifier circuit 151 amplifies the voltage signals to obtain the Icap_DET voltage signal. The Icap_DET voltage signal is then connected to the positive input terminal of the comparison integrator circuit 152, and a reference voltage is connected to the negative input terminal of the comparison integrator circuit 152 for comparison and integration. When the voltage input to the positive input terminal of the comparison integrator circuit 152 is higher than that to the negative input terminal, the output operational amplifier is set to a high level. The output terminal of the comparison integrator circuit 152 is connected to the FB pin of the SEPIC controller. When the voltage value at the FB pin of the SEPIC controller exceeds a certain voltage, the overvoltage protection function inside the chip is triggered, limiting the output. When the voltage input to the positive input terminal of the comparison integrator circuit 152 is lower than that to the negative input terminal, the output operational amplifier is set to a low level, the voltage at the FB pin of the SEPIC controller returns to normal, and the SEPIC controller resumes normal operation. The output current will fluctuate around the reference voltage, thereby achieving the effect of current control.

[0052] This invention also provides a computer device, including the supercapacitor charging circuit described in the foregoing embodiments.

[0053] In this embodiment, the computer device of the present invention includes a supercapacitor charging circuit, wherein the supercapacitor charging circuit can refer to the above embodiments. Since the computer device includes the technical solutions of all embodiments of the supercapacitor charging circuit, the computer device has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0054] This invention provides a supercapacitor charging circuit and computer equipment, including a SEPIC control circuit, a multi-channel supercapacitor module, a voltage equalization loop, a voltage feedback loop, and a current feedback loop. The SEPIC control circuit receives the input voltage at its input terminal and its output terminal is connected to the multi-channel supercapacitor module. The voltage equalization loop is connected to both the multi-channel supercapacitor module and the SEPIC control circuit. The voltage feedback loop is also connected to both the multi-channel supercapacitor module and the SEPIC control circuit. In this embodiment, the SEPIC control circuit can use the input voltage provided by the input power supply to perform equal-voltage constant-current charging on multiple supercapacitors connected in series in the multi-channel supercapacitor module, improving charging efficiency, extending the lifespan of the supercapacitors, and exhibiting low circuit complexity and low cost.

[0055] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A supercapacitor charging circuit, characterized by, The application relates to a SEPIC control circuit, a multi-path super capacitor module, a voltage equalization circuit, a voltage feedback circuit and a current feedback circuit; the input end of the SEPIC control circuit receives an input voltage, the output end of the SEPIC control circuit is connected with the multi-path super capacitor module; the voltage equalization circuit is connected with the multi-path super capacitor module and the SEPIC control circuit; the voltage feedback circuit is connected with the multi-path super capacitor module and the SEPIC control circuit; the current feedback circuit is connected with the multi-path super capacitor module and the SEPIC control circuit; and the SEPIC control circuit is used for equalizing the voltage and constant-current charging of a plurality of super capacitors arranged in series in the multi-path super capacitor module by using the input voltage provided by an input power supply.

2. The supercapacitor charging circuit of claim 1, wherein, The SEPIC control circuit comprises a SEPIC controller, a filter, a SEPIC inductor, a SEPIC controller rear-end network, a MOS switch and a precision resistor; the input end of the SEPIC controller is connected with the input voltage through the filter; the input end of the SEPIC inductor is connected with the input voltage through the filter, the output end of the SEPIC inductor is connected with the SEPIC controller rear-end network, and the output end of the SEPIC inductor is further connected with the ground through the MOS switch and the precision resistor; the number of SEPIC controller rear-end circuits included in the SEPIC controller rear-end network is the same as the number of super capacitors included in the multi-path super capacitor module, and the two ends of each SEPIC controller rear-end circuit are respectively connected with the two ends of a unique corresponding super capacitor in the multi-path super capacitor module.

3. The supercapacitor charging circuit of claim 2, wherein, The SEPIC control circuit further comprises a first resistor, a first capacitor, a first diode, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a second capacitor; the VCC pin of the SEPIC controller is connected with the output end of the filter through the first resistor, and the VCC pin of the SEPIC controller is further connected with the ground through the first capacitor; the GND pin of the SEPIC controller is connected with the ground; the Gate pin of the SEPIC controller is connected with the gate of the MOS switch through the second resistor; the negative electrode of the first diode is connected with the Gate pin of the SEPIC controller, and the positive electrode of the first diode is connected with the gate of the MOS switch; the ISENSE pin of the SEPIC controller is connected with the ground through the precision resistor; the FB pin of the SEPIC controller is connected with the first end of the third resistor and the first end of the second capacitor, and is further connected with the ground through the fifth resistor; the second end of the third resistor is connected with the voltage equalization circuit; the second end of the second capacitor is connected with the voltage equalization circuit through the fourth resistor; the drain of the MOS switch is connected with the output end of the SEPIC inductor, and the source of the MOS switch is connected with the ground through the precision resistor.

4. The supercapacitor charging circuit of claim 3, wherein, The filter is a π type filter, and the π type filter comprises a first inductor, a third capacitor, a fourth capacitor and a fifth capacitor; a first end of the first inductor is connected to the input voltage, a second end of the first inductor is connected to an input end of the SEPIC inductor, and the second end of the first inductor is also connected to a VCC pin of the SEPIC controller through the first resistor; a first end of the third capacitor is connected to the first end of the first inductor, and a second end of the third capacitor is grounded; a first end of the fourth capacitor is connected to the second end of the first inductor, and a second end of the fourth capacitor is grounded; a first end of the fifth capacitor is connected to the second end of the first inductor, and a second end of the fifth capacitor is grounded.

5. The supercapacitor charging circuit of claim 3, wherein, The voltage equalization circuit is a voltage equalization diode; a positive electrode of the voltage equalization diode is connected to the second end of the third resistor, and a negative electrode of the voltage equalization diode is connected to the input end of the SEPIC inductor.

6. The supercapacitor charging circuit of claim 3, wherein, The multi-way super capacitor module comprises a first super capacitor, a second super capacitor, a third super capacitor, a fourth super capacitor, a fifth super capacitor, a sixth resistor and a sixth capacitor; an input end of the first super capacitor is connected to the second end of the third resistor, the input end of the first super capacitor is also grounded through the sixth capacitor, and an output end of the first super capacitor is connected to an input end of the second super capacitor; An output end of the second super capacitor is connected to an input end of the third super capacitor; An output end of the third super capacitor is connected to an input end of the fourth super capacitor; An output end of the fourth super capacitor is connected to an input end of the fifth super capacitor; and an output end of the fifth super capacitor is grounded through the sixth resistor.

7. The supercapacitor charging circuit of claim 6, wherein, The input end of the first super capacitor is further connected with the input end of the first SEPIC controller rear-end circuit in the SEPIC controller rear-end network, and the output end of the first super capacitor is further connected with the output end of the first SEPIC controller rear-end circuit; the input end of the second super capacitor is further connected with the input end of the second SEPIC controller rear-end circuit in the SEPIC controller rear-end network, and the output end of the second super capacitor is further connected with the output end of the second SEPIC controller rear-end circuit; the input end of the third super capacitor is further connected with the input end of the third SEPIC controller rear-end circuit in the SEPIC controller rear-end network, and the output end of the third super capacitor is further connected with the output end of the third SEPIC controller rear-end circuit; the input end of the fourth super capacitor is further connected with the input end of the fourth SEPIC controller rear-end circuit in the SEPIC controller rear-end network, and the output end of the fourth super capacitor is further connected with the output end of the fourth SEPIC controller rear-end circuit; the input end of the fifth super capacitor is further connected with the input end of the fifth SEPIC controller rear-end circuit in the SEPIC controller rear-end network, and the output end of the fifth super capacitor is further connected with the output end of the fifth SEPIC controller rear-end circuit.

8. The supercapacitor charging circuit of claim 3, wherein, The voltage feedback loop comprises a voltage comparator and an error amplifier; the positive input end of the voltage comparator is connected with the FB pin of the SEPIC controller, and the negative input end of the voltage comparator inputs a preset upper limit voltage; the negative input end of the error amplifier inputs a preset lower limit voltage, and the positive input end of the error amplifier is connected with the FB pin of the SEPIC controller.

9. The supercapacitor charging circuit of claim 6, wherein, The current feedback loop comprises an amplification circuit and a comparison integration circuit; the positive input end of the amplification circuit is connected with the first end of the sixth resistor, and the negative input end of the amplification circuit is connected with the second end of the sixth resistor; the output end of the amplification circuit is connected with the positive input end of the comparison integration circuit and the output end of the fifth super capacitor; the negative input end of the comparison integration circuit inputs a reference voltage, and the output end of the comparison integration circuit is connected with the FB pin of the SEPIC controller.

10. A computer device, comprising: The super capacitor charging circuit comprises the super capacitor charging circuit according to any one of claims 1-9.

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