Laminated ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component capable of providing a laminated ceramic capacitor capable of improving the fixing force between a laminated body and a base electrode layer without increasing the ESR in an external electrode. In the laminated ceramic electronic component, a plurality of laminated ceramic layers are mainly composed of Ca and Zr, and a first external electrode and a second external electrode have a first base electrode layer and a second base electrode layer, and a plating layer formed so as to cover a part of the first base electrode layer and the second base electrode layer. The first base electrode layer and the second base electrode layer are mainly composed of Cu, a first compound region extending toward the first end surface and a second compound region extending toward the second end surface are disposed at an edge portion in the lamination direction of the laminate, the first compound region is bonded to the first base electrode layer, and the second compound region is bonded to the second base electrode layer. The second compound region is bonded to the second base electrode layer, and the first compound region and the second compound region are not bonded.

Description

Technical Field

[0001] This utility model relates to multilayer ceramic electronic components, and particularly to multilayer ceramic capacitors. Background Technology

[0002] In recent years, with the miniaturization of electronic devices incorporating multilayer ceramic electronic components (MLCs), the size of these components has also decreased. However, when the MLC is a multilayer ceramic capacitor, a problem arises where the external electrode may peel off when a device such as a smartphone equipped with a multilayer ceramic capacitor is dropped from a certain height, or when deflection from the substrate is transmitted to the MLC. As a countermeasure to this problem, Patent Document 1, among others, describes a method to improve the bonding strength between the multilayer chip and the external electrode by providing a glass component layer between the chip and the external electrode.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-182107 Utility Model Content

[0006] Problems to be solved by utility models

[0007] However, when a glass component layer is incorporated, the equivalent series resistance (ESR) of the multilayer ceramic capacitor increases due to the insulating nature of glass. Therefore, the object of this application is to provide multilayer ceramic electronic components, such as multilayer ceramic capacitors, that can improve the bonding strength between the multilayer and the base electrode layer without increasing the ESR within the external electrodes.

[0008] Technical solutions for solving the problem

[0009] The present invention discloses a stacked ceramic electronic component comprising: a stacked body comprising a plurality of stacked ceramic layers, wherein the plurality of ceramic layers are mainly composed of Ca and Zr; the stacked body comprising a first main surface and a second main surface opposite to each other in a stacking direction; a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction; a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface; and a second internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the second end surface; a first external electrode configured to extend from the first end surface to the first main surface and the second main surface; and a second external electrode. The first and second external electrodes are configured to extend from the second end face to the first and second main faces. Each electrode has a first base electrode layer and a second base electrode layer, and a plating layer formed to cover a portion of the first and second base electrode layers. The first and second base electrode layers are primarily composed of Cu. At the edge of the laminate in the lamination direction, the following regions are configured: a first compound region extending toward the first end face; and a second compound region extending toward the second end face. The first compound region is bonded to the first base electrode layer, and the second compound region is bonded to the second base electrode layer. The first compound region and the second compound region are not bonded.

[0010] Utility Model Effect

[0011] According to this invention, a laminated ceramic electronic component can be provided that improves the fixation force of the laminate and the substrate electrode layer without increasing the ESR in the external electrode. Attached Figure Description

[0012] Figure 1 This is a perspective view of a stacked ceramic electronic component according to an embodiment of the present invention.

[0013] Figure 2 yes Figure 1 Sectional view along line I-I.

[0014] Figure 3 yes Figure 1 Sectional view along line II-II.

[0015] Figure 4 yes Figure 1 Sectional view along line III-III.

[0016] Figure 5 The diagram illustrates the relationship between the dummy electrode layer and... Figure 1 The figure corresponding to the I-I line sectional view.

[0017] Figure 6 This is a diagram illustrating the characteristics of a stacked ceramic electronic component.

[0018] Explanation of reference numerals in the attached figures

[0019] 1. Laminated Ceramic Electronic Components

[0020] 2-layered body

[0021] 4 Ceramic layer

[0022] 7. Edges of the laminated body

[0023] 8. Compound region

[0024] 10 Internal Electrode Layer

[0025] 11 Opposed Electrode Section

[0026] 12 Lead-out Electrode Section

[0027] 14. Dummy Electrode Layer

[0028] 20 external electrodes

[0029] 21 Substrate Electrode Layer

[0030] 23 plating layers

[0031] 24 inner plating layers

[0032] 25 Surface coating

[0033] 27 End Face External Electrode

[0034] 28 Main surface external electrodes

[0035] 29 Side External Electrodes

[0036] 50 Electrode Opposing Section

[0037] 51L gap

[0038] 52W gap

[0039] 53 Inner Layer

[0040] 54 outer layer

[0041] 61 Main side

[0042] 62 end face

[0043] 63 side view

[0044] Central position of 70-layer stack

[0045] 71 Area Front End

[0046] 72 Base Anterior End

[0047] 73 Internal electrode front end

[0048] 74. Dummy Electrode Layer Front End

[0049] 80-83 endpoints

[0050] T stacking direction

[0051] L (length direction)

[0052] W represents the width direction. Detailed Implementation

[0053] Hereinafter, an example of an embodiment of the multilayer ceramic electronic component 1 of the present invention will be described with reference to the accompanying drawings. In the following description, the multilayer ceramic electronic component 1 will be described as a multilayer ceramic capacitor. Furthermore, the same reference numerals will be used to denote the same or equivalent parts in each of the drawings.

[0054] (Outline of a laminated ceramic electronic component)

[0055] based on Figure 1 A brief description of the appearance of the stacked ceramic electronic component 1 is provided. Figure 1 This is a perspective view showing the stacked ceramic electronic component 1 according to this embodiment. The stacked ceramic electronic component 1 includes a laminate 2 and external electrodes 20. The external electrodes 20 include a first external electrode 20a and a second external electrode 20b.

[0056] (Definition of direction)

[0057] In the accompanying drawings, the L-direction, W-direction, and T-direction are appropriately shown. The L-direction is the length direction L of the stacked ceramic electronic component 1. The W-direction is the width direction W of the stacked ceramic electronic component 1. The T-direction is the stacking direction T of the stacked ceramic electronic component 1. Thus, Figure 2 The cross-section shown is called the LT section. Figure 3 The cross-section shown is called the WT section. Figure 4 The cross-section shown is called the LW section. The length direction L, width direction W, and stacking direction T do not necessarily have to be orthogonal to each other. The length direction L, width direction W, and stacking direction T can also be intersecting.

[0058] (The shape of the stacked body)

[0059] The laminate 2 has a generally rectangular parallelepiped shape. The laminate 2 has two main faces 61, two end faces 62, and two side faces 63. The main faces 61 are faces opposite each other in the lamination direction T. The end faces 62 are faces opposite each other in the length direction L. The side faces 63 are faces opposite each other in the width direction W. One of the two main faces 61 is designated as the first main face 61a, and the other as the second main face 61b. One of the two end faces 62 is designated as the first end face 62a, and the other as the second end face 62b. One of the two side faces 63 is designated as the first side face 63a, and the other as the second side face 63b.

[0060] Preferably, the edges and corners of the laminate 2 are rounded. An edge is the intersection of two faces of the laminate 2. A corner is the intersection of three faces of the laminate 2. Furthermore, the size of the laminate 2 is not particularly limited.

[0061] (Structure of layered structures)

[0062] The laminate 2 comprises multiple ceramic layers 4 and multiple internal electrode layers 10. The structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2.

[0063] (Internal structure of the laminate (LT section))

[0064] based on Figure 2 The internal structure of the laminate 2 will be explained. Figure 2 yes Figure 1 The cross-sectional view along line I-I of the stacked ceramic electronic component 1 is shown. Figure 2 The LT cross-section of the laminated ceramic electronic component 1 is shown. Figure 2 As shown, the laminate 2 includes multiple ceramic layers 4 and multiple internal electrode layers 10. The multiple ceramic layers 4 and multiple internal electrode layers 10 are stacked on top of each other in the stacking direction T.

[0065] (Inner layer and outer layer)

[0066] The laminate 2 is divided into an inner layer 53 and two outer layers 54 in the lamination direction T. The outer layers 54 include a first outer layer 54a and a second outer layer 54b. The first outer layer 54a and the second outer layer 54b are located in the lamination direction T, sandwiching the inner layer 53.

[0067] A portion of a plurality of ceramic layers 4 and a plurality of internal electrode layers 10 are disposed in the inner layer portion 53. In the inner layer portion 53, the plurality of internal electrode layers 10 are positioned opposite each other, separated by the ceramic layers 4. Therefore, an electrostatic capacitor is formed in the inner layer portion 53. Thus, the inner layer portion 53 is the portion in the laminate 2 that substantially functions as a capacitor. Therefore, the inner layer portion 53 is also referred to as the effective portion.

[0068] The first outer layer 54a is the portion of the outer layer 54 located on the first main surface 61a side of the laminate 2. The second outer layer 54b is the portion of the outer layer 54 located on the second main surface 61b side of the laminate 2. Specifically, the first outer layer 54a is the portion of the plurality of inner electrode layers 10 closest to the first main surface 61a between the inner electrode layer 10 and the first main surface 61a. The second outer layer 54b is the portion of the plurality of inner electrode layers 10 closest to the second main surface 61b between the inner electrode layer 10 and the second main surface 61b. No inner electrode layers 10 are disposed in the first outer layer 54a and the second outer layer 54b. The first outer layer 54a and the second outer layer 54b are provided with the remaining ceramic layers 4 of the plurality of ceramic layers 4, excluding the ceramic layer 4 used in the inner layer 53. The first outer layer 54a and the second outer layer 54b function as protective layers for the inner layer 53.

[0069] (Ceramic layer)

[0070] As described above, the ceramic layer 4 can be classified into a ceramic layer 4 disposed in the inner layer portion 53 and a ceramic layer 4 disposed in the outer layer portion 54. The ceramic layer 4 disposed in the inner layer portion 53 is designated as the inner ceramic layer 4a. The ceramic layer 4 disposed in the outer layer portion 54 is designated as the outer ceramic layer 4b.

[0071] (Inner ceramic layer)

[0072] The inner ceramic layer 4a is located between the inner electrode layers 10. Specifically, the inner ceramic layer 4a is located between the first inner electrode layer 10a and the second inner electrode layer 10b. Moreover, the inner ceramic layer 4a and the inner electrode layers 10 together constitute the inner layer portion 53.

[0073] (Outer ceramic layer)

[0074] The outer ceramic layer 4b is located between the first main surface 61a and the inner electrode layer 10 closest to the first main surface 61a, and between the second main surface 61b and the inner electrode layer 10 closest to the second main surface 61b. The outer ceramic layer 4b constitutes the first outer layer portion 54a and the second outer layer portion 54b.

[0075] (Number of ceramic layers)

[0076] The number of ceramic layers 4 stacked in the laminate 2 can be set to, for example, 5 or more and 2000 or less. The number of ceramic layers 4 includes the number of inner ceramic layers 4a and the number of outer ceramic layers 4b.

[0077] (Material of the ceramic layer)

[0078] For example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used as the material for ceramic layer 4. Alternatively, materials with secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components can also be used.

[0079] The ceramic layer 4 may also contain multiple grains, which are perovskite-type compounds with a basic structure of BaTiO3. When the ceramic layer 4 is thin, the capacitance as a capacitor increases. Therefore, the grain size is preferably 1 μm or less. On the other hand, as the ceramic layer becomes thinner, the grains become smaller. If the grains become too small, the relative permittivity decreases due to the size effect. Therefore, the grain size is preferably designed appropriately according to the thickness of the ceramic layer.

[0080] When piezoelectric ceramics are used in the laminate 2, the laminated ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include, for instance, PZT (lead zirconate titanate) based ceramic materials.

[0081] When semiconductor ceramics are used in the laminate 2, the laminated ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include, for instance, spinel-based ceramic materials.

[0082] When magnetic ceramics are used in laminates, the laminated ceramic electronic components function as inductor elements. Furthermore, when the laminated ceramic electronic components function as inductor elements, the internal electrode layer becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for instance, ferrite ceramic materials.

[0083] (Thickness of the ceramic layer)

[0084] The thickness of the ceramic layer 4 can be set to, for example, 0.3 μm or more and 100 μm or less. In addition, the outer ceramic layer 4b can be multiple layers or a single layer.

[0085] (Internal electrode layer)

[0086] The internal electrode layer 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is the internal electrode layer 10 connected to the first external electrode 20a. The second internal electrode layer 10b is the internal electrode layer 10 connected to the second external electrode 20b. The first internal electrode layer 10a extends from the first end face 62a toward the second end face 62b. The second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.

[0087] (opposite part and lead-out part)

[0088] The first internal electrode layer 10a and the second internal electrode layer 10b each have a counter electrode portion 11 and an lead-out electrode portion 12.

[0089] The opposing electrode portion 11 is the portion of the inner electrode layer 10 in which the first inner electrode layer 10a and the second inner electrode layer 10b are opposed to each other in the stacking direction T. The lead-out electrode portion 12 is the portion of the inner electrode layer 10 that extends from the opposing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.

[0090] The opposing electrode portion 11 of the first internal electrode layer 10a is designated as the first opposing electrode portion 11a. The lead-out electrode portion 12 of the first internal electrode layer 10a is designated as the first lead-out electrode portion 12a. The first lead-out electrode portion 12a is the portion that extends from the first opposing electrode portion 11a to the first end face 62a of the laminate 2.

[0091] Similarly, the counter electrode portion 11 of the second internal electrode layer 10b is designated as the second counter electrode portion 11b. The lead-out electrode portion 12 of the second internal electrode layer 10b is designated as the second lead-out electrode portion 12b. The second lead-out electrode portion 12b is the portion that extends from the second counter electrode portion 11b to the second end face 62b of the laminate 2.

[0092] (Number of internal electrode layers)

[0093] The number of internal electrode layers 10 can be set to, for example, 10 or more and 2000 or less. The number of internal electrode layers 10 includes the number of first internal electrode layers 10a and the number of second internal electrode layers 10b.

[0094] (Thickness of the internal electrode layer)

[0095] The thickness of the inner electrode layer 10 can be set to, for example, 0.1 μm or more and 5.0 μm or less, preferably 0.2 μm or more and 2.0 μm or less. When the thickness of the inner electrode layer 10 is 0.5 μm or more, the plating film becomes easier to grow when the metal layer of the outer electrode 20 is formed by plating.

[0096] (Material of the internal electrode layer)

[0097] The material of the inner electrode layer 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the inner electrode layer 10 may also contain dielectric particles with the same composition as the ceramic contained in the ceramic layer 4.

[0098] (Electrode opposing section)

[0099] The division of the laminate 2 along the length direction L will be explained. The laminate 2 can be divided along the length direction L into an electrode opposing portion 50 and an L-gap 51. The electrode opposing portion 50 in the division along the length direction L is designated as an L-gap portion 50a. Furthermore, the L-gap 51 includes a first L-gap 51a and a second L-gap 51b.

[0100] The L-opposing portion 50a corresponds to the portion of the first inner electrode layer 10a and the second inner electrode layer 10b that are opposed to each other in the lamination direction T. The L-opposing portion 50a is located in the central portion of the laminate 2 in the longitudinal direction L. In the L-opposing portion 50a, the first opposing electrode portion 11a and the second opposing electrode portion 11b are opposed to each other in the lamination direction T through the inner ceramic layer 4a. Therefore, a capacitor is formed in the L-opposing portion 50a. Thus, the L-opposing portion 50a is also referred to as the effective portion.

[0101] (L-gap)

[0102] L-gap 51 is the portion of the laminate 2 in the length direction L where the first internal electrode layer 10a and the second internal electrode layer 10b are not opposite each other in the stacking direction T. Furthermore, within L-gap 51, the first L-gap 51a is the portion in the stacking direction T where the first internal electrode layer 10a is disposed but the second internal electrode layer 10b is not disposed. Similarly, within L-gap 51, the second L-gap 51b is the portion in the stacking direction T where the second internal electrode layer 10b is disposed but the first internal electrode layer 10a is not disposed.

[0103] The L-gap 51 is located between the L-opposite portion 50a and the first end face 62a, and between the L-opposite portion 50a and the second end face 62b, along the length L of the laminate 2. The first L-gap 51a is between the L-opposite portion 50a and the first end face 62a. The second L-gap 51b is between the L-opposite portion 50a and the second end face 62b. The first L-gap 51a corresponds to the position where the first lead-out electrode portion 12a is disposed. Therefore, the first L-gap 51a functions as a lead-out portion of the first internal electrode layer 10a to the first end face 62a. The second L-gap 51b corresponds to the position where the second lead-out electrode portion 12b is disposed. Therefore, the second L-gap 51b functions as a lead-out portion of the second internal electrode layer 10b to the second end face 62b.

[0104] The length of the longitudinal direction L of the gap 51 can be set to, for example, 10% or more and 30% or less of the length of the longitudinal direction L of the laminate 2. Furthermore, the length of the longitudinal direction L of the gap 51 can be set to, for example, 5 μm or more and 30 μm or less. The length of the longitudinal direction L of the gap 51 will be explained in detail later.

[0105] Furthermore, the specific structure of the internal electrode layer 10, etc., can be modified in various ways. For example, while the shape of the first opposing electrode portion 11a of the first internal electrode layer 10a is not particularly limited, it is preferably rectangular. However, its corners can also be rounded. In addition, the corners can also be formed at an angle. That is, the corners can also be conical. Furthermore, the conical shape can also be a shape that is inclined towards any edge of the first opposing electrode portion 11a.

[0106] Similarly, while the shape of the second opposing electrode portion 11b of the second inner electrode layer 10b is not particularly limited, it is preferably rectangular. However, its corners may also be rounded. Furthermore, the corners may also be formed at an angle. That is, the corners may also be conical. Moreover, the conical shape may also be a shape that is inclined towards any edge of the second opposing electrode portion 11b.

[0107] Similarly, while the shape of the first lead-out electrode portion 12a of the first internal electrode layer 10a is not particularly limited, it is preferably rectangular. However, its corners may also be rounded. Furthermore, the corners may also be formed at an angle. That is, the corners may also be conical. Moreover, the conical shape may also be a shape that is inclined towards any edge of the first lead-out electrode portion 12a.

[0108] Similarly, while the shape of the second lead-out electrode portion 12b of the second inner electrode layer 10b is not particularly limited, it is preferably rectangular. However, its corners may also be rounded. Furthermore, the corners may also be formed at an angle. That is, the corners may also be conical. Moreover, the conical shape may also be a shape that is inclined towards any edge of the second lead-out electrode portion 12b.

[0109] The width of the first opposing electrode portion 11a of the first internal electrode layer 10a and the width of the first lead-out electrode portion 12a of the first internal electrode layer 10a can also be formed to be the same width. Alternatively, the width of either one can be formed to be narrower.

[0110] The width of the second opposing electrode portion 11b of the second internal electrode layer 10b and the width of the second lead-out electrode portion 12b of the second internal electrode layer 10b can be formed to be the same width, or either of them can be formed to be narrower.

[0111] The first lead-out electrode portion 12a of the first internal electrode layer 10a can also be bent toward the center of the first end face 62a of the laminate 2.

[0112] The second lead-out electrode portion 12b of the second internal electrode layer 10b can also be bent toward the center of the second end face 62b of the laminate 2.

[0113] The distance between the inner electrode layer 10 closest to the first main surface 61a and the inner electrode layer 10 closest to the second main surface 61b, which are led out to each end face 62, can also be shorter than the distance between the opposing electrode portion 11 closest to the first main surface 61a and the opposing electrode portion 11 closest to the second main surface 61b.

[0114] In the stacked ceramic electronic component 1 of this embodiment, the opposing electrode portions 11 of the inner electrode layer 10 are positioned opposite each other with a gap between them and the ceramic layer 4, thereby forming a capacitor. This exhibits the characteristics of a capacitor. To achieve a high capacitance, the surface area of ​​the inner electrode layer 10 needs to be increased. Therefore, the coverage of the LW surface of the inner electrode layer 10 is preferably 90% or more. The coverage of the LW surface, when viewed from the LW surface, is defined as the ratio of the area remaining after subtracting the area of ​​the gap from the area inside the edge of the inner electrode layer 10 to the area inside the edge of the inner electrode layer 10.

[0115] When the LW plane coverage is high, the capacitance of the capacitor increases. Conversely, when the LW plane coverage is low, the ceramic layers 4 are bonded to each other through the voids. Therefore, the interlayer bonding strength increases. Consequently, interlayer delamination becomes less likely to occur.

[0116] Furthermore, the internal electrode layer 10 preferably has a uniform thickness. However, it is also possible that the thickness of the edge portion in the width direction W is greater than the thickness of the center portion in the width direction W.

[0117] (Insulating layer)

[0118] Insulating layers may also be disposed on the first side 63a and the second side 63b of the laminate 2. If insulating layers are disposed, the interface between the internal electrode layer 10 and the ceramic layer 4 is covered by the insulating layer. This prevents moisture from penetrating the interface between the internal electrode layer 10 and the ceramic layer 4. The insulating layer is preferably of the same composition as the ceramic layer 4. However, the material of the insulating layer is not limited to this.

[0119] The insulating layer can also be configured to bond to the inner electrode layer 10. In this case, the laminate 2 preferably does not have the W gap 52 described later. This is because the insulating layer and the inner electrode layer 10 become easier to bond.

[0120] (Step level)

[0121] Furthermore, a stepped layer may also be provided in the L-gap 51. The stepped layer is a ceramic layer 4 added to the L-gap 51 to reduce the length difference in the lamination direction T between the L-gap 51 and the L-opposite portion 50a. The stepped layer may also be configured such that the inner electrode layer 10 covers a portion of the stepped layer. Alternatively, it may be configured such that the stepped layer covers a portion of the inner electrode layer 10. Preferably, the stepped layer has the same thickness as the inner electrode layer 10. Furthermore, the stepped layer preferably has the same composition as the ceramic layer 4. However, the composition of the ceramic layer 4 is not limited thereto.

[0122] (Dummy electrode layer)

[0123] A dummy electrode layer may also be disposed in the L-gap 51. The dummy electrode layer can be disposed in at least one of the inner layer portion 53 and the outer layer portion 54. Here, the outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b. When the dummy electrode layer is disposed in the outer layer portion 54, it is preferably disposed in a position corresponding to the position after the L-gap 51 is moved parallel to the lamination direction T. That is, the dummy electrode layer is preferably disposed at a position corresponding to the L-gap 51 in the length direction L of the outer layer portion 54.

[0124] The dummy electrode layer can include a first dummy electrode layer and a second dummy electrode layer.

[0125] A dummy electrode layer disposed on the same plane as the first internal electrode layer 10a and exposed on the second end face 62b is designated as the first dummy electrode layer. The first dummy electrode layer preferably has the same thickness as the sum of the thicknesses of the first internal electrode layers 10a. That is, the first dummy electrode layer preferably has the same thickness as the value obtained by multiplying the thickness of the first internal electrode layer 10a by the number of sheets of the first internal electrode layer 10a.

[0126] Furthermore, the first dummy electrode layer can be disposed on the same plane as the first internal electrode layer 10a that is closest to either the first main surface 61a or the second main surface 61b.

[0127] Alternatively, the first dummy electrode layer can be configured on both the same plane as the first internal electrode layer 10a closest to the first main surface 61a and the same plane as the first internal electrode layer 10a closest to the second main surface 61b.

[0128] A dummy electrode layer disposed on the same plane as the second internal electrode layer 10b and exposed on the first end face 62a is designated as the second dummy electrode layer. The second dummy electrode layer is also the same as the first dummy electrode layer. That is, the second dummy electrode layer preferably has the same thickness as the sum of the thicknesses of the second internal electrode layers 10b. In other words, the second dummy electrode layer preferably has the same thickness as the value obtained by multiplying the thickness of the second internal electrode layer 10b by the number of sheets of the second internal electrode layer 10b.

[0129] Furthermore, the second dummy electrode layer can also be configured in the same way as the first dummy electrode layer.

[0130] Furthermore, both the first dummy electrode layer and the second dummy electrode layer can be disposed in the outer layer 54.

[0131] (External electrode)

[0132] The external electrode 20 includes a first external electrode 20a and a second external electrode 20b.

[0133] (First external electrode)

[0134] The first external electrode 20a is an external electrode 20 disposed on the first end face 62a of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a.

[0135] (Second external electrode)

[0136] The second external electrode 20b is an external electrode 20 disposed on the second end face 62b of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0137] (External electrodes on each facet)

[0138] The external electrode 20 extends from one end face 62 to a portion of two main faces 61 and a portion of two side faces 63. The portion of the external electrode 20 disposed on the end face 62 is designated as the end face external electrode 27. The portion of the external electrode 20 disposed on a portion of the main faces 61 is designated as the main face external electrode 28. The portion of the external electrode 20 disposed on a portion of the side faces 63 is designated as the side face external electrode 29.

[0139] Specifically, the portion of the first external electrode 20a disposed on the first end face 62a is designated as the first end face external electrode 27a. The portion of the first external electrode 20a disposed on a portion of the first main surface 61a or a portion of the second main surface 61b is designated as the first main surface external electrode 28a. The portion of the first external electrode 20a disposed on a portion of the first side surface 63a or a portion of the second side surface 63b is designated as the first side surface external electrode 29a.

[0140] Furthermore, regarding the second external electrode 20b, similarly to the first external electrode 20a, the portion of the second external electrode 20b disposed on the second end face 62b is designated as the second end face external electrode 27b. The portion of the second external electrode 20b disposed on a portion of the first main surface 61a or a portion of the second main surface 61b is designated as the second main surface external electrode 28b. The portion of the second external electrode 20b disposed on a portion of the first side surface 63a or a portion of the second side surface 63b is designated as the second side surface external electrode 29b.

[0141] (Layer structure of external electrodes)

[0142] based on Figure 2 The layer structure of the external electrode 20 will be described. The external electrode 20 includes a base electrode layer 21 and a plating layer 23. The plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged from the end face 62 of the laminate 2 in the order of base electrode layer 21, inner plating layer 24, and surface plating layer 25. Specifically, the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a. The first plating layer 23a includes a first inner plating layer 24a and a first surface plating layer 25a. Similarly, the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b. The second plating layer 23b includes a second inner plating layer 24b and a second surface plating layer 25b.

[0143] (Base electrode layer)

[0144] The first base electrode layer 21a is disposed on the first end face 62a of the laminate 2, covering the first end face 62a. The first base electrode layer 21a extends from the first end face 62a to a portion of the first main face 61a, a portion of the second main face 61b, a portion of the first side face 63a, and a portion of the second side face 63b.

[0145] Similarly, the second base electrode layer 21b is disposed on the second end face 62b of the laminate 2, covering the second end face 62b. The second base electrode layer 21b extends from the second end face 62b to a portion of the first main face 61a, a portion of the second main face 61b, a portion of the first side face 63a, and a portion of the second side face 63b.

[0146] (burnt coating)

[0147] The first base electrode layer 21a and the second base electrode layer 21b constitute a sintered layer. The sintered layer contains a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer can also be multilayered. The sintered layer is obtained by applying a conductive paste containing a glass component and a metal to the laminate 2 and then sintering it. This sintering, i.e., firing, can be performed simultaneously with the firing of the inner electrode layer 10, or it can be performed separately after the firing of the inner electrode layer 10.

[0148] The thickness of the first sintered layer and the second sintered layer located at the center of the stacking direction T of the first base electrode layer 21a located on the first end face 62a and the second base electrode layer 21b located on the second end face 62b is preferably, for example, 3 μm or more and 25 μm or less.

[0149] When a sintered layer is provided on the first main surface 61a and the second main surface 61b, and the first side surface 63a and the second side surface 63b, the thickness of the sintered layer at the center of the base electrode layer 21 in the longitudinal direction on each surface is preferably, for example, 3 μm or more and 25 μm or less.

[0150] (plating layer)

[0151] The plating layer 23 on the substrate electrode layer 21 will be described. As previously mentioned, in this embodiment, the plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. That is, the plating layer 23 includes two layers. However, the plating layer 23 can be a single layer or multiple layers.

[0152] When the plating layer 23 is configured as two layers, it is preferable to configure it in the order of Ni plating layer and Sn plating layer from the bottom layer. Furthermore, when the plating layer is configured as three layers, it is preferable to configure it in the order of Sn plating layer, Ni plating layer, and Sn plating layer from the bottom layer. Among these, the preferred layer structure is a two-layer structure consisting of Ni plating layer and Sn plating layer. Hereinafter, the case where the plating layer 23 consists of two layers: inner plating layer 24 and surface plating layer 25, will be described.

[0153] (Inner plating layer)

[0154] The inner plating layer 24 is disposed on the base electrode layer 21 and covers at least a portion of the base electrode layer 21.

[0155] (Surface coating)

[0156] The surface plating layer 25 is disposed on the inner plating layer 24, covering at least a portion of the inner plating layer 24.

[0157] Including the inner plating layer 24 and the surface plating layer 25, the plating layer 23 preferably comprises at least one metal selected from, for example, Cu, Ni, Ag, Pd, Au, and Sn, and an alloy such as an Ag-Pd alloy. The inner plating layer 24 is preferably a Ni plating layer, and the surface plating layer 25 is preferably a Sn plating layer.

[0158] The Ni plating layer prevents the base electrode layer 21 from being eroded by solder during the mounting of the multilayer ceramic electronic component 1. The Sn plating layer improves the wettability of the solder during the mounting of the multilayer ceramic electronic component 1, making mounting easier. Therefore, by making the surface plating layer 25 a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved. The thickness of each plating layer is preferably 3 μm or more and 9 μm or less.

[0159] (Internal structure of the laminate (WT section))

[0160] based on Figure 3 The internal structure of the laminate 2 will be explained. Figure 3 yes Figure 1 The cross-sectional view along line II-II of the stacked ceramic electronic component 1 shown. Figure 3 The internal structure shown is the internal structure viewed from the second end face 62b. The laminate 2 is divided into an electrode opposing portion 50 and a W gap 52 in the width direction W. The electrode opposing portion 50 in the width direction W is designated as the W opposing portion 50b. Furthermore, the W gap 52 includes a first W gap 52a and a second W gap 52b.

[0161] The W-opposing portion 50b is the portion of the internal electrode layer 10 that is opposed to each other in the stacking direction T. The W-gap 52 is the portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is disposed in the stacking direction T.

[0162] The W gap 52 is located between the W opposing portion 50b and the first side surface 63a, and between the W opposing portion 50b and the second side surface 63b, in the width direction W of the laminate 2. Specifically, the first W gap 52a is located between the W opposing portion 50b and the first side surface 63a. The second W gap 52b is located between the W opposing portion 50b and the second side surface 63b.

[0163] In other words, the first W gap 52a is located between the end of the inner electrode layer 10 on the first side surface 63a and the first side surface 63a. Furthermore, the second W gap 52b is located between the end of the inner electrode layer 10 on the second side surface 63b and the second side surface 63b.

[0164] The first W gap 52a and the second W gap 52b are configured to sandwich the W opposing portion 50b. The first W gap 52a and the second W gap 52b do not contain the internal electrode layer 10, but only the ceramic layer 4. The first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.

[0165] The length of the width direction W of the gap 52 can be set to, for example, 20% or more and 30% or less of the length of the width direction W of the laminate 2. Furthermore, the length of the width direction W of the gap 52 can be set to, for example, 5 μm or more and 50 μm or less. The length of the width direction W of the gap 52 will be explained in detail later.

[0166] (Size of stacked ceramic electronic components)

[0167] The size of the stacked ceramic electronic component 1 is not particularly limited. The size of the stacked ceramic electronic component 1 can be set as follows: The length direction L of the stacked ceramic electronic component 1, including the stack body 2 and the external electrode 20, is defined as dimension L. Dimension L is preferably 0.25 mm or more and 1.0 mm or less. The stacking direction T of the stacked ceramic electronic component 1, including the stack body 2 and the external electrode 20, is defined as dimension T. Dimension T is preferably 0.125 mm or more and 0.5 mm or less. The width direction W of the stacked ceramic electronic component 1, including the stack body 2 and the external electrode 20, is defined as dimension W. Dimension W is preferably 0.125 mm or more and 0.5 mm or less. Furthermore, the lengths of each part of the stack body 2 and the external electrode 20 can be measured using a micrometer or an optical microscope.

[0168] Furthermore, in this embodiment, the example described is a two-terminal multilayer ceramic capacitor. However, the multilayer ceramic electronic component 1 is not limited to a two-terminal multilayer ceramic capacitor, and can also be a multi-terminal multilayer ceramic capacitor with three or more terminals.

[0169] (Compound region)

[0170] The multilayer ceramic electronic component 1 of this embodiment is characterized in that a compound region 8 is provided in the multilayer body 2. The compound region 8 is provided at the edge 7 of the multilayer body 2. The edge 7 of the multilayer body 2 refers to the portion near the surface of the multilayer body 2. The compound region 8 is provided in a part of the ceramic layer 4. Specifically, the compound region 8 is provided in the ceramic layer 4 constituting the edge 7 of the multilayer body 2. The edge 7 means the portion near the surface of the multilayer body 2. The compound region 8 refers to a region in the ceramic layer 4 with a higher Cu content compared to other parts.

[0171] based on Figure 2 The description focuses on compound region 8. Figure 2 A compound region 8 is shown provided at a first edge 7a of the edge 7 in the stacking direction T of the laminate 2. Furthermore, a second edge 7b of the edge 7 in the width direction W of the laminate 2 is also provided for the compound region 8. Based on this... Figure 4 The explanation will follow.

[0172] like Figure 2 As shown, a first compound region 8a extending toward a first end face 62a is provided at the first edge 7a of the laminate 2. The first compound region 8a is respectively provided on the first main surface 61a and the second main surface 61b of the laminate 2. In addition, a second compound region 8b extending toward a second end face 62b is provided at the first edge 7a of the laminate 2. The second compound region 8b is similarly provided on the first main surface 61a and the second main surface 61b of the laminate 2.

[0173] (Gathering of compound regions)

[0174] The first compound region 8a is preferably bonded to the first substrate electrode layer 21a. Furthermore, the second compound region 8b is preferably bonded to the second substrate electrode layer 21b.

[0175] Furthermore, the first compound region 8a is not bonded to the second compound region 8b. This is because if the first compound region 8a were bonded to the second compound region 8b, the first external electrode 20a and the second external electrode 20b would be connected, thereby causing a short circuit in the stacked ceramic electronic component 1.

[0176] More preferably, the first compound region 8a is not located at a position 70 relative to the center of the first base electrode layer 21a disposed on the first main surface 61a and the second main surface 61b in the length direction L of the laminate 2. This central position 70 is designated as the center position 70 of the laminate. Similarly, more preferably, the second compound region 8b is not located at a position relative to the center position 70 of the laminate of the second base electrode layer 21b disposed on the first main surface 61a and the second main surface 61b.

[0177] exist Figure 2 In this diagram, the front end portion of the laminate containing the first compound region 8a at the center position 70 is shown as the first region front end portion 71a. Furthermore, the front end portion of the laminate containing the first substrate electrode layer 21a at the center position 70 is shown as the first substrate front end portion 72a. Figure 2 As shown, the front end portion 71a of the first region is located closer to the first end face 62a than the front end portion 72a of the first base.

[0178] The same applies to region 8b of the second compound. Figure 2In this diagram, the front end portion of the laminate at the central position 70 of the second compound region 8b is shown as the front end portion 71b of the second region. Furthermore, the front end portion of the laminate at the central position 70 of the second substrate electrode layer 21b is shown as the front end portion 72b of the second substrate. Figure 2 As shown, the front end portion 71b of the second region is located closer to the second end face 62b than the front end portion 72b of the second base.

[0179] exist Figure 2 In this diagram, distance d1 represents the distance in the longitudinal direction L between the front end portion 71a of the first region and the front end portion 72a of the first substrate. Furthermore, distance d2 represents the distance in the longitudinal direction L between the front end portion 71b of the second region and the front end portion 72b of the second substrate. Distances d1 and d2 are preferably set to, for example, 3 μm or more and 1000 μm or less.

[0180] The front end portion 71a of the first region is located closer to the first end face 62a than the front end portion 72a of the first substrate, and the front end portion 71b of the second region is located closer to the second end face 62b than the front end portion 72b of the second substrate. This allows for a sufficient measurement of the distance L along the length direction between the first compound region 8a and the second compound region 8b. Consequently, the risk of short-circuit defects caused by short circuits in the first compound region 8a and the second compound region 8b is reduced.

[0181] As previously mentioned, compound region 8 is a region in the ceramic layer 4 with a higher Cu content compared to other parts. By providing such compound region 8 at the edge 7 of the laminate 2, the adhesion between the ceramic layer 4 and the base electrode layer 21 is increased due to the mutual diffusion between them, thereby reducing the risk of peeling.

[0182] (Thickness of the compound region)

[0183] exist Figure 2 In this design, the thickness of the first compound region 8a in the direction orthogonal to the first substrate electrode layer 21a is denoted as thickness d3. Thickness d3 is preferably 4 μm or more and 25 μm or less. Similarly, the thickness of the second compound region 8b in the direction orthogonal to the second substrate electrode layer 21b is defined as thickness d4. Thickness d4 is preferably 4 μm or more and less than 25 μm.

[0184] If the thickness d3 of the first compound region 8a and the thickness d4 of the second compound region 8b are set to 4 μm or less, sufficient fixation of the first compound region 8a and the first substrate electrode layer 21a, as well as the second compound region 8b and the second substrate electrode layer 21b, cannot be achieved. On the other hand, if the thickness d3 of the first compound region 8a and the thickness d4 of the second compound region 8b are set to 25 μm or more, dielectric loss will occur, and the ESR will increase. For the above reasons, the thickness d3 of the first compound region 8a and the thickness d4 of the second compound region 8b are preferably 4 μm or more and less than 25 μm.

[0185] (Components of the compound region)

[0186] The primary component of the first compound region 8a is preferably Cu. Similarly, the primary component of the second compound region 8b is preferably Cu. By setting the primary component of the compound region 8 to Cu, the fixation force between the laminate 2 and the substrate electrode layer 21 can be further improved due to interdiffusion with the substrate electrode layer 21.

[0187] Regarding the composition of compound region 8, it is more preferable that compound region 8 is 80% or more Cu. More preferably, it is preferable that compound region 8 is 60% or more Cu.

[0188] (Component Analysis)

[0189] The method for determining the main components of compound region 8 is explained. The main components can be determined by the following steps (1) to (3).

[0190] (1) The laminate 2 is cross-sectionally ground in a direction that is approximately parallel to the direction that connects the first side surface 63a and the second side surface 63b of the laminate 2.

[0191] (2) For the exposed cross-section, perform elemental analysis using EDX (Energy Dispersive X-ray Spectroscopy) or WDX (Wavelength Dispersive X-ray Spectroscopy).

[0192] (3) The component that is most abundant in each unit area is taken as the main component.

[0193] As mentioned above, the main component of compound region 8 is Cu. Furthermore, compound region 8 preferably contains more than 60% Cu. This further enhances the bonding strength between the ceramic layer 4 and the substrate electrode layer 21, and even the bonding strength between the laminate 2 and the substrate electrode layer 21.

[0194] (Methods for measuring thickness)

[0195] The method for measuring the thickness of compound region 8 is described. The thickness can be determined by the following steps (1) to (3).

[0196] (1) The laminate 2 is cross-sectionally ground in a direction that is approximately parallel to the direction that connects the first side surface 63a and the second side surface 63b of the laminate 2.

[0197] (2) The thickness of the substrate electrode layer 21 was measured using a digital microscope.

[0198] (3) Based on the aforementioned component analysis, SEM (Scanning Electron Microscope) was used to identify areas containing more than 60% Cu.

[0199] (4) Subtract the thickness of the base electrode layer 21 measured by (2) from the region determined by (3) to calculate the thickness of the compound region 8.

[0200] (Compound region in the width direction)

[0201] As previously described, the compound region 8 is also provided in the second edge 7b of the edge 7 in the width direction W of the laminate 2. Based on Figure 4 Please provide an explanation. Figure 4 yes Figure 1 The section view along line III-III is a diagram showing the WL section of the stacked ceramic electronic component 1. (See diagram below.) Figure 4 As shown, a third compound region 8c extending toward the first end face 62a is provided at the second edge 7b of the laminate 2. The third compound region 8c is respectively provided on the first side face 63a and the second side face 63b of the laminate 2. Furthermore, a fourth compound region 8d extending toward the second end face 62b is provided at the second edge 7b of the laminate 2. The fourth compound region 8d, like the third compound region 8c, is also provided on the first side face 63a and the second side face 63b of the laminate 2.

[0202] The third compound region 8c and the fourth compound region 8d have the same structure and properties as the first compound region 8a and the second compound region 8b mentioned above.

[0203] (Length of the L-gap)

[0204] The length of gap L51 is explained. For example... Figure 2As shown, the length of the laminate 2 in the longitudinal direction L is set to d6. Furthermore, the length of the laminate 2 in the longitudinal direction L of the first L-gap 51a and the second L-gap 51b is set to d5. The length d5 ​​of the L-gap 51 is preferably 10% or more and 30% or less of the length d6 of the laminate 2. In other words, (length d5 ​​of the laminate 2 in the longitudinal direction L of the L-gap 51) / (length d6 of the laminate 2 in the longitudinal direction L) is preferably 0.10 or more and 0.30 or less. If this ratio is less than 0.1, the internal electrode layer 10 and the external electrode 20 may conduct at undesirable locations. On the other hand, if this ratio is greater than 0.3, the L-gap 51 becomes too large, potentially leading to structural defects due to steps.

[0205] (Dummy electrode layer)

[0206] The case where a dummy electrode layer 14 is configured on the L gap 51 will be explained. Figure 4 The structure in which a dummy electrode layer 14 is configured in the second L gap 51b is shown. Figure 4 In this design, the front end portion of the first internal electrode layer 10a on the second end face 62b side is shown as the internal electrode front end portion 73. Furthermore, the front end portion of the dummy electrode layer 14 on the first end face 62a side is shown as the dummy electrode layer front end portion 74. The length L in the longitudinal direction between the internal electrode front end portion 73 and the dummy electrode layer front end portion 74 is defined as d7. This length d7 is preferably 10% or more and 30% or less of the length d6 in the longitudinal direction L of the laminate 2. Additionally, the dummy electrode layer 14 need not be disposed in all layers of the inner layer portion 53 of the laminate 2. For example, it may be disposed only in the outermost layer of the inner layer portion 53. The outermost layer refers to the layer closest to any main face 61 among the layers in which the internal electrode layer 10 is disposed.

[0207] based on Figure 5 An example of the configuration of the dummy electrode layer 14 will be explained. Figure 5 The diagram illustrates the relationship between the dummy electrode layer 14 and... Figure 1 The diagram corresponding to the I-I line sectional view. For example... Figure 5 As shown, the dummy electrode layer 14 may include at least one of a second dummy electrode layer 14c / 14d disposed on the same plane as the first internal electrode layer 10a and exposed on the second end face 62b, and a first dummy electrode layer 14a / 14b disposed on the same plane as the second internal electrode layer 10b and exposed on the first end face 62a.

[0208] Regarding the length L of the dummy electrode layer 14, the length of the outermost dummy electrode layer 14, that is, the dummy electrode layer 14 closest to the first main surface 61a or the second main surface 61b, is longer than the lengths of the other dummy electrode layers 14.

[0209] Furthermore, regarding the length L of the inner electrode layer 10, the length of the inner electrode layer 10 disposed on the same plane as the outermost dummy electrode layer 14 is shorter than the length of the other inner electrode layers 10.

[0210] In addition, the so-called same plane here means a stacked plane that is parallel to the LW plane.

[0211] exist Figure 5 Here is one example.

[0212] The second dummy electrode layer 14c is the dummy electrode layer 14 closest to the second main surface 61b. The length L of the second dummy electrode layer 14c in the length direction is set as length d11.

[0213] The second dummy electrode layer 14d is a dummy electrode layer 14 located after the second dummy electrode layer 14c, closer to the first main surface 61a than the second dummy electrode layer 14c. The length L of the second dummy electrode layer 14d is defined as length d12.

[0214] The length d11 is longer than the length d12.

[0215] The length of the longitudinal direction L of the first internal electrode layer 10a will be explained. The length of the longitudinal direction L of the first internal electrode layer 10a, which is disposed on the same plane as the second dummy electrode layer 14c, is defined as length d13. Furthermore, the length of the longitudinal direction L of the first internal electrode layer 10a, which is disposed on the same plane as the second dummy electrode layer 14d, is defined as length d14.

[0216] The length d13 is shorter than the length d14.

[0217] In addition, Figure 5 In this configuration, the length L of the first dummy electrode layers 14a / 14b is the same. Furthermore, the length L of the second internal electrode layers 10b disposed on the same plane as them is also the same. However, the first dummy electrode layers 14a / 14b and the second internal electrode layers 10b disposed on the same plane as them can also be configured in the same way as the second dummy electrode layers 14c / 14d described above.

[0218] (W gap)

[0219] The length of the W gap 52 is explained. For example... Figure 3As shown, the length of the width direction W of the laminate 2 is set to d8. Furthermore, the length of the width direction W of the laminate 2 for both the first W gap 52a and the second W gap 52b is set to d9. The length d8 of the W gap 52 is preferably 20% or more and 30% or less of the length d9 of the width direction W of the laminate 2. In other words, (the length d9 of the width direction W of the laminate 2 for the W gap 52) / (the length d8 of the width direction W of the laminate 2) is preferably 0.20 or more and 0.30 or less.

[0220] (Method for determining gap length)

[0221] The lengths of gaps L51 and W52, etc., can be measured by grinding the laminate 2 in a direction parallel to the LW plane down to the outermost layer of the laminate 2, exposing the inner electrode layer 10, and observing the exposed surface using a digital microscope. In the case of a dummy electrode layer 14, the same method is used: grinding down to the outermost layer, and measuring the length d7 in the outermost layer.

[0222] (Path length regulations)

[0223] The path length specification is explained. The lengths of the internal electrode layer 10 and the dummy electrode layer 14, etc., can be measured as follows: The boundary line of the internal electrode layer 10 is set within a range of 92% to 103% of the ideal boundary line of the internal electrode layer 10. By setting the path length within this range, the path length is not excessively long, and as a result, the influence on ESR can be suppressed. Furthermore, by setting the path length within this range, the path length is not excessively short, and as a result, excessive capacitance reduction can be suppressed. The boundary line is measured by grinding the laminate 2 in a direction parallel to the LW plane down to the outermost layer of the laminate 2, exposing the internal electrode layer 10, and observing the exposed surface using a digital microscope. At this time, the internal electrode layer 10 and the ceramic layer 4 are distinguished by binarization using conductive components and components other than conductive components. Figure 4 As shown, an ideal boundary line is calculated by connecting the two endpoints 80 and 81 of the exposed portion of the internal electrode layer 10 extending to the end face 62 in the width direction W, and the two endpoints 82 and 83 of the internal electrode layer 10 located at the center position 70 of the laminate in the length direction L of the laminate 2, in the width direction W. At this time, neither the actual boundary line nor the ideal boundary line includes the boundary line when the exposed endpoints 80 and 81 of the internal electrode layer 10 are connected to each other. Furthermore, when a dummy electrode layer 14 is configured, grinding is performed up to the outermost layer, and the path length of the internal electrode layer 10 at this location is measured.

[0224] (Manufacturing method of laminated ceramic electronic components)

[0225] Next, taking the laminated ceramic electronic component 1 as an example, the manufacturing method of the laminated ceramic electronic component will be explained.

[0226] In the following description, the manufacturing method of the laminated ceramic electronic component 1 of this embodiment will be described with a focus on the characteristic parts.

[0227] (Creating stacked blocks)

[0228] Prepare a conductive paste for the ceramic sheet and the internal electrode layer. The conductive paste for the ceramic sheet and the internal electrode layer contains an adhesive and a solvent. Known organic adhesives and solvents can be used. The conductive paste for the internal electrode layer is printed on the ceramic sheet in a given pattern, for example, by screen printing, gravure printing, etc., to form the pattern of the internal electrode layer 10. A given number of ceramic sheets for the outer layer 54 without the pattern of the internal electrode layer 10 are stacked, and ceramic sheets with the pattern of the internal electrode layer 10 are sequentially stacked on top of each other. Another given number of ceramic sheets for the outer layer 54 are then stacked on top of each other to create a laminated sheet. A laminated block is produced by pressing the laminated sheet in the stacking direction using isostatic pressing or other methods.

[0229] (The creation of layered small pieces)

[0230] The laminated block is cut to a given size, resulting in laminated pieces. At this point, the corners and edges of the laminated pieces can be rounded using methods such as tumble grinding. The laminated pieces are then fired to form laminate 2.

[0231] (Firing)

[0232] Next, the stacked pieces are fired to produce the stacked body 2. Although the firing temperature also depends on the materials of the ceramic layer 4 and the internal electrode layer 10, it is preferably 900°C or higher and 1400°C or lower.

[0233] (External electrode)

[0234] Next, the formation of the external electrode 20 will be explained.

[0235] (Base electrode layer)

[0236] A conductive paste, serving as the base electrode layer 21, is applied to both end faces 62 of the laminate 2 to form the base electrode layer 21. To form the sintered layer, a conductive paste containing glass components and metal is applied, for example, by dipping, and then a sintering process is performed to form the base electrode layer 21. The sintering temperature is preferably 500°C or higher and 900°C or lower. Furthermore, the sintering time is preferably 30 minutes or more and 2 hours or less. The sintering atmosphere is preferably a reducing atmosphere, for example, containing H₂O or H₂. The higher the sintering temperature and the longer the sintering time, the greater the thickness of the compound region 8 can be achieved. Then, if necessary, plating can be performed on the surface of the sintered layer.

[0237] Next, a plating layer 23 is formed on the surface of the base electrode layer 21. In this embodiment, a Ni plating layer is formed on the sintered layer. This Ni plating layer becomes the inner plating layer 24. Next, a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the surface plating layer 25. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a roller plating method. In this way, a multilayer ceramic capacitor 1 can be obtained.

[0238] (Characteristic evaluation of laminated ceramic electronic components)

[0239] The characteristics of the laminated ceramic electronic component 1 are described.

[0240] (1) Evaluate short films

[0241] • Multilayer ceramic capacitors, which are multilayer ceramic electronic components, are used as evaluation samples.

[0242] Regarding dimensions, the length L is set to 0.62mm, the width W to 0.31mm, and the stacking T to 0.31mm.

[0243] • The ceramic material is set as CaZrO3.

[0244] • The capacitor is set to 4.7pF, and the rated voltage is set to 25V.

[0245] (2) Construction of external electrodes

[0246] Substrate electrode layer: This is an electrode layer containing Cu, which is a conductive metal, and glass.

[0247] • The film thickness at end face 62 is set to 10 μm.

[0248] The thickness of the substrate electrode layer 21 located at the center of the length direction L on the first main surface 61a, the second main surface 61b, the first side surface 63a, and the second side surface 63b is set to 6 μm.

[0249] Metal layer: This is defined as a metal layer containing the plating layers. As plating layers, two layers are formed: a Ni plating layer and a Sn plating layer.

[0250] The thickness of the Ni plating layer is set as follows.

[0251] • The film thickness at end face 62 is 4 μm.

[0252] • The thickness of the Ni plating layer located at the center of the length direction L on the first main surface 61a, the second main surface 61b, the first side surface 63a, and the second side surface 63b is set to 4 μm.

[0253] The thickness of the Sn plating layer is set as follows.

[0254] • The film thickness at end face 62 is 4 μm.

[0255] • The film thickness at the center of the Sn plating layer along the length direction L on the first main surface 61a, the second main surface 61b, the first side surface 63a, and the second side surface 63b is set to 4 μm.

[0256] (3) Evaluation content

[0257] based on Figure 6 The evaluation results of the characteristics of the evaluation piece are explained. Figure 6 This is a graph showing the evaluation results of the characteristics. For example... Figure 6 As shown, seven evaluation pieces with different thicknesses of compound region 8 were prepared. Among the seven evaluation pieces, one was a comparative example and six were exemplary examples. The evaluation items were tape peel test and ESR determination.

[0258] • Tape peel test

[0259] Two hundred laminated ceramic electronic components were pressed and peeled off with adhesive tape (Made by Nichiban, CT-24) with an adhesion force of 10N per 25mm. The number of peels that occurred was then counted.

[0260] ESR measurement

[0261] Prior to ESR measurement, the laminated ceramic electronic components were heat-treated at 150°C for 1 hour in air. Then, they were mounted on the measurement substrate. 24 ± 2 hours after the heat treatment, the measurement frequency was set to 1 MHz, and the ESR was measured using a network analyzer. One hundred samples were measured, and their average values ​​were evaluated. In the evaluation, using sample number 1 as the benchmark, the ESR was measured...

[0262] ◎: ESR of sample number 1 is less than 105%

[0263] 〇: For sample number 1, 105% < ESR ≤ 110%

[0264] △: For sample number 1, 110% < ESR ≤ 115%

[0265] ×: Greater than 115% of the ESR of sample number 1

[0266] ESR was determined.

[0267] In Examples 1 to 6, where compound region 8 was formed, the number of peeling samples was suppressed to less than 5 out of 200 in the tape peel test. Furthermore, good ESR measurements were obtained within the range where the thickness of the compound region was 25 μm or less. Moreover, particularly good results were obtained in ESR measurements in Example 1, where the thickness of the compound region was 4 μm, and in Example 2, where the thickness of the compound region was 5 μm.

[0268] The embodiments of this utility model have been described above, but this utility model is not limited to the aforementioned embodiments and can be modified and varied in various ways.

[0269] <1>

[0270] A stacked ceramic electronic component, comprising:

[0271] A laminate comprising multiple stacked ceramic layers, wherein the multiple ceramic layers are mainly composed of Ca and Zr, the laminate comprising a first main surface and a second main surface opposite each other in the stacking direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the stacking direction, a first end surface and a second end surface opposite each other in the length direction orthogonal to the stacking direction and the width direction, a first internal electrode layer alternately stacked with the multiple ceramic layers and exposed on the first end surface, and a second internal electrode layer alternately stacked with the multiple ceramic layers and exposed on the second end surface;

[0272] A first external electrode is configured to extend from the first end face to the first main face and the second main face; and

[0273] The second external electrode is configured to be wound from the second end face to the first main face and the second main face.

[0274] The first external electrode and the second external electrode have:

[0275] The first substrate electrode layer and the second substrate electrode layer; and

[0276] A plating layer is formed to cover a portion of both the first substrate electrode layer and the second substrate electrode layer.

[0277] Both the first and second base electrode layers are primarily composed of Cu.

[0278] In the laminated body, the following region is configured at the edge in the lamination direction:

[0279] The first compound region extends toward the first end face; and

[0280] The second compound region extends toward the second end face.

[0281] The first compound region is bonded to the first substrate electrode layer.

[0282] The second compound region is bonded to the second substrate electrode layer.

[0283] The first compound region and the second compound region are not bonded.

[0284] <2>

[0285] According to the laminated ceramic electronic component described in <1>, wherein...

[0286] The first compound region and the second compound region are not located on the central side of the first base electrode layer and the second base electrode layer disposed on the first main surface and the second main surface, in the length direction of the laminate.

[0287] <3>

[0288] According to the laminated ceramic electronic component described in <1> or <2>, wherein,

[0289] The thickness of the first compound region and the thickness of the second compound region in a direction orthogonal to the first base electrode layer and the second base electrode layer are 4 μm or more and 25 μm or less.

[0290] <4>

[0291] The laminated ceramic electronic component according to any one of <1> to <3>, wherein,

[0292] The main component of the first compound region and the second compound region is Cu.

[0293] <5>

[0294] The laminated ceramic electronic component according to any one of <1> to <4>, wherein,

[0295] In the laminated body, the following region is configured at the edge in the width direction:

[0296] The third compound region extends toward the first end face; and

[0297] The fourth compound region extends toward the second end face.

[0298] The third compound region is bonded to the first substrate electrode layer.

[0299] The fourth compound region is bonded to the second substrate electrode layer.

[0300] The third compound region and the fourth compound region are not bonded.

[0301] <6>

[0302] The laminated ceramic electronic component according to any one of <1> to <5>, wherein,

[0303] The portions of the first internal electrode layer and the second internal electrode layer that are opposite each other in the stacking direction are designated as electrode opposing portions.

[0304] The gaps along the length of the laminate, between the electrode-opposing portion and the first end face, and between the electrode-opposing portion and the second end face, are respectively defined as L-shaped gaps.

[0305] The length of the L-gap in the longitudinal direction of the laminate is more than 10% and less than 30% of the length of the laminate in the longitudinal direction.

[0306] <7>

[0307] The laminated ceramic electronic component according to any one of <1> to <6>, wherein,

[0308] The laminate has a first dummy electrode layer disposed on the same plane as the first internal electrode layer and exposed on the second end face.

[0309] The distance between the front end of the second end face of the first internal electrode layer and the front end of the first end face of the first dummy electrode layer in the length direction of the laminate is more than 10% and less than 30% of the length of the laminate in the length direction.

[0310] <8>

[0311] According to the laminated ceramic electronic component described in <7>, wherein...

[0312] The first dummy electrode layer is disposed on the same plane as the first internal electrode layer that is closest to either the first main surface or the second main surface.

[0313] <9>

[0314] The laminated ceramic electronic component according to any one of <1> to <6>, wherein,

[0315] The laminate has:

[0316] A second dummy electrode layer is disposed on the same plane as the first internal electrode layer and exposed on the second end face; and

[0317] The first dummy electrode layer is disposed on the same plane as the second internal electrode layer and exposed at the first end face.

[0318] The distance between the front end of the second end face of the first internal electrode layer and the front end of the first end face of the second dummy electrode layer in the length direction of the laminate is more than 10% and less than 30% of the length of the laminate in the length direction.

[0319] <10>

[0320] According to the laminated ceramic electronic component described in <9>, wherein...

[0321] In the first dummy electrode layers, the first dummy electrode layer closest to the first main surface or the second main surface is longer in the length direction than other first dummy electrode layers adjacent to it in the stacking direction.

[0322] The second internal electrode layer, which is disposed on the same plane as the first dummy electrode layer closest to the first main surface or the second main surface, is shorter in length direction than other second internal electrode layers disposed on the same plane as other first dummy electrode layers adjacent to the first dummy electrode layer in the stacking direction.

[0323] <11>

[0324] According to the laminated ceramic electronic component described in <9>, wherein...

[0325] In the second dummy electrode layers, the second dummy electrode layer closest to the first main surface or the second main surface is longer in the length direction than other second dummy electrode layers adjacent to it in the stacking direction.

[0326] The first internal electrode layer, which is disposed on the same plane as the second dummy electrode layer closest to the first main surface or the second main surface, is shorter in length direction than other first internal electrode layers disposed on the same plane as other second dummy electrode layers adjacent to the second dummy electrode layer in the stacking direction.

[0327] <12>

[0328] The laminated ceramic electronic component according to any one of <1> to <11>, wherein,

[0329] The portions of the first internal electrode layer and the second internal electrode layer that are opposite each other in the stacking direction are designated as electrode opposing portions.

[0330] The gaps between the electrode-opposing portion and the first side surface, and between the electrode-opposing portion and the second side surface, are respectively designated as W gaps in the width direction of the laminate.

[0331] The length of the W gap in the width direction of the laminate is more than 20% and less than 30% of the length in the width direction of the laminate.

[0332] <13>

[0333] The laminated ceramic electronic component according to any one of <1> to <12>, wherein,

[0334] The actual boundary line of the first internal electrode layer or the second internal electrode layer is more than 92% and less than 103% of the ideal path length of the corresponding first internal electrode layer or the second internal electrode layer.

[0335] <14>

[0336] According to the laminated ceramic electronic component described in <1> or <4>, wherein,

[0337] The main component is the component that is most abundant in a given area.

Claims

1. A laminated ceramic electronic component, characterized in that, have: A laminate comprising multiple stacked ceramic layers, wherein the multiple ceramic layers are mainly composed of Ca and Zr, the laminate comprising a first main surface and a second main surface opposite each other in the stacking direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the stacking direction, a first end surface and a second end surface opposite each other in the length direction orthogonal to the stacking direction and the width direction, a first internal electrode layer alternately stacked with the multiple ceramic layers and exposed on the first end surface, and a second internal electrode layer alternately stacked with the multiple ceramic layers and exposed on the second end surface; The first external electrode is configured to be wound from the first end face to the first main face and the second main face; as well as The second external electrode is configured to be wound from the second end face to the first main face and the second main face. The first external electrode and the second external electrode have: The first substrate electrode layer and the second substrate electrode layer; and A plating layer is formed to cover a portion of both the first substrate electrode layer and the second substrate electrode layer. Both the first and second base electrode layers are primarily composed of Cu. In the laminated body, the following region is configured at the edge in the lamination direction: The first compound region extends toward the first end face; and The second compound region extends toward the second end face. The first compound region is bonded to the first substrate electrode layer. The second compound region is bonded to the second substrate electrode layer. The first compound region and the second compound region are not bonded.

2. The laminated ceramic electronic component according to claim 1, characterized in that, The first compound region and the second compound region are not located on the central side of the first base electrode layer and the second base electrode layer disposed on the first main surface and the second main surface, in the length direction of the laminate.

3. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The thickness of the first compound region and the thickness of the second compound region in a direction orthogonal to the first base electrode layer and the second base electrode layer are 4 μm or more and 25 μm or less.

4. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The main component of the first compound region and the second compound region is Cu.

5. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, In the laminated body, the following region is configured at the edge in the width direction: The third compound region extends toward the first end face; as well as The fourth compound region extends toward the second end face. The third compound region is bonded to the first substrate electrode layer. The fourth compound region is bonded to the second substrate electrode layer. The third compound region and the fourth compound region are not bonded.

6. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The portions of the first internal electrode layer and the second internal electrode layer that are opposite each other in the stacking direction are designated as electrode opposing portions. The gaps along the length of the laminate, between the electrode-opposing portion and the first end face, and between the electrode-opposing portion and the second end face, are respectively defined as L-shaped gaps. The length of the L-gap in the longitudinal direction of the laminate is more than 10% and less than 30% of the length of the laminate in the longitudinal direction.

7. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The laminate has a first dummy electrode layer disposed on the same plane as the first internal electrode layer and exposed on the second end face. The distance between the front end of the second end face of the first internal electrode layer and the front end of the first end face of the first dummy electrode layer in the length direction of the laminate is more than 10% and less than 30% of the length of the laminate in the length direction.

8. The laminated ceramic electronic component according to claim 7, characterized in that, The first dummy electrode layer is disposed on the same plane as the first internal electrode layer that is closest to either the first main surface or the second main surface.

9. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The laminate has: A second dummy electrode layer is disposed on the same plane as the first internal electrode layer and exposed on the second end face; and The first dummy electrode layer is disposed on the same plane as the second internal electrode layer and exposed at the first end face. The distance between the front end of the second end face of the first internal electrode layer and the front end of the first end face of the second dummy electrode layer in the length direction of the laminate is more than 10% and less than 30% of the length of the laminate in the length direction.

10. The laminated ceramic electronic component according to claim 9, characterized in that, In the first dummy electrode layers, the first dummy electrode layer closest to the first main surface or the second main surface is longer in the length direction than other first dummy electrode layers adjacent to it in the stacking direction. The second internal electrode layer, which is disposed on the same plane as the first dummy electrode layer closest to the first main surface or the second main surface, is shorter in length direction than other second internal electrode layers disposed on the same plane as other first dummy electrode layers adjacent to the first dummy electrode layer in the stacking direction.

11. The laminated ceramic electronic component according to claim 9, characterized in that, In the second dummy electrode layers, the second dummy electrode layer closest to the first main surface or the second main surface is longer in the length direction than other second dummy electrode layers adjacent to it in the stacking direction. The first internal electrode layer, which is disposed on the same plane as the second dummy electrode layer closest to the first main surface or the second main surface, is shorter in length direction than other first internal electrode layers disposed on the same plane as other second dummy electrode layers adjacent to the second dummy electrode layer in the stacking direction.

12. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The portions of the first internal electrode layer and the second internal electrode layer that are opposite each other in the stacking direction are designated as electrode opposing portions. The gaps between the electrode-opposing portion and the first side surface, and between the electrode-opposing portion and the second side surface, are respectively designated as W gaps in the width direction of the laminate. The length of the W gap in the width direction of the laminate is more than 20% and less than 30% of the length in the width direction of the laminate.

13. The laminated ceramic electronic component according to claim 1 or 2, characterized in that, The actual boundary line of the first internal electrode layer or the second internal electrode layer is more than 92% and less than 103% of the ideal path length of the corresponding first internal electrode layer or the second internal electrode layer.

14. The laminated ceramic electronic component according to claim 1, characterized in that, The main component is the component that is most abundant in a given area.

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