Control isolation output circuit and charger

Abstract

According to the control isolation output circuit and the charger, the BMS charging circuit is controlled through the front-end AFE chip U1, the charging MOS tube and the isolation MOS tube are controlled at the same time, and isolation output of the charging end is achieved. When the charger is powered on and the BMS is in a charging state, the CHG pin of the front-end AFE chip U1 outputs a high-level signal to drive the charging primary MOS tube Q1 to be switched on, so that the c pole and the e pole of the triode Q12 are switched on, the charging isolation MOS tube Q2 is further driven to be switched on, and the charger starts to charge the battery pack. When the charger is disconnected and the BMS quits the charging state, the CHG pin voltage of the front-end AFE chip U1 returns to the VBAT voltage, the single MOS tube Q1 is closed, the triode Q12 is not conducted, the triode Q9 is conducted through the clamping effect of the diode D8, the loop voltage of the charging circuit is rapidly discharged, the isolation MOS tube Q2 is closed, and the charger stops charging the battery. By accurately controlling the current, the voltage spike and misoperation in the charging process are protected, and a safe, efficient and low-cost charging solution is provided.

Description

Technical Field

[0001] This application belongs to the field of battery protection technology, specifically relating to a control isolation output circuit and a charger. Background Technology

[0002] In existing technologies, many BMS circuit designs for charging circuits employ diode isolation or a separate PMOS transistor controlled by an MCU to meet the requirement of isolated output at the charging end. The diode isolation solution is prone to overheating during charging, and the reverse leakage current of the diode is relatively high; the MCU-controlled PMOS transistor solution is costly and inflexible. Utility Model Content

[0003] To address the shortcomings of the existing technology, this application provides a control isolation output circuit and charger. Charging is achieved by simultaneously controlling the charging MOSFET Q1 and the isolation MOSFET Q2 through the front-end AFE chip U1, thus meeting the requirement of isolated output at the charging end. This is a relatively low-cost and flexible solution for circuit application.

[0004] In a first aspect, this application provides a control isolation output circuit, including a front-end AFE chip U1, a rechargeable MOSFET Q1, an isolation MOSFET Q2, a fuse F1, a fuse F2, a sampling resistor, and a battery pack.

[0005] The CHG pin of the front-end AFE chip U1 is connected to the gate of a first-charge MOSFET Q1, and the CHG pin of the front-end AFE chip U1 is also connected to the gate of an isolation MOSFET Q2.

[0006] The drain of the primary charging MOSFET Q1 is connected to the drain of the isolation MOSFET Q2, and the source of the primary charging MOSFET Q1 is connected to the battery pack through the fuse F1.

[0007] The source terminal of the isolation MOSFET Q2 is connected to the positive power supply terminal C+ through fuse F2;

[0008] One end of the sampling resistor is connected to the battery pack, and the other end is connected to the negative terminal P- / C- of the power supply.

[0009] The circuit proposed in this application achieves electrical isolation between the battery pack and the power supply through the configuration of the isolation MOSFET Q2, ensuring their independence and protection. The switching states of the primary charging MOSFET Q1 and the isolation MOSFET Q2 are adjusted by the control signal on the CHG pin of the front-end AFE chip U1. Through the coordinated operation of the primary charging MOSFET Q1 and the isolation MOSFET Q2, precise control of the current flow during the charging process is achieved. The isolation MOSFET Q2 also effectively isolates the battery pack from the power supply, avoiding direct electrical contact between the battery and the power supply, thus increasing the electrical stability and anti-interference capability of the system.

[0010] Preferably, the control isolation output circuit proposed in this application further includes:

[0011] The CHG pin of the front-end AFE chip U1 is connected in series with the isolation MOSFET Q2, along with transistor Q12, diode D7, diode D8, resistor R36, and resistor R26.

[0012] The emitter of transistor Q12 is connected to resistors R36 and R35, respectively.

[0013] The other end of the resistor R35 is connected to the base of the transistor Q12;

[0014] The collector (c) of transistor Q12 is connected to the anode of diode D7, and the cathode of diode D7 is also connected to the base (b) of transistor Q9.

[0015] The base of transistor Q9 is connected to fuse F2 via resistor R19;

[0016] The collector of transistor Q9 is connected to fuse F2 via resistor R16;

[0017] The emitter (e) of transistor Q9 is connected to the cathode of diode D8.

[0018] Preferably, the control isolation output circuit further includes: the negative terminal of the diode D8 is connected to resistor R26, and one end of resistor R18 and Zener diode Z4 are connected respectively;

[0019] The other end of the resistor R18 and the Zener diode Z4 is connected to the fuse F2;

[0020] The other end of the resistor R26 is connected to the gate of the isolation MOSFET Q2.

[0021] Preferably, the control isolation output circuit further includes:

[0022] The CHG pin of the front-end AFE chip U1 is also connected in series with resistors R33 and R23 to the first-charge MOSFET Q1.

[0023] The other end of the resistor R33 is connected to the Zener diode Z3;

[0024] The other end of the Zener diode Z3 is connected to the fuse F1;

[0025] The resistor R23 is also connected in parallel with the resistor R17.

[0026] Preferably, the control isolation output circuit further includes:

[0027] The base of transistor Q12 is connected in series with resistors R25 and R109 and then connected to the VBAT pin of the front-end AFE chip U1.

[0028] Transistors Q12 and Q9 connected in series enable more precise current flow control, effectively regulating the current through the isolation MOSFET Q2 to ensure that the current and voltage between the battery and the power supply remain within set threshold ranges. Diodes D7 and D8 provide current paths, preventing reverse current flow and protecting the circuit from reverse current damage, thus avoiding component failure or unsafe situations during charging. Zener diodes Z3 and Z4 stabilize the voltage, protecting the battery from the effects of power supply fluctuations during charging. The isolation MOSFET Q2 provides excellent electrical isolation between the battery and the power supply. The front-end AFE chip U1, through its connection with multiple resistors, transistors, and diodes, precisely controls the signal flow during battery charging.

[0029] Preferably, the control isolation output circuit proposed in this application further includes:

[0030] The drain of the first-charge MOSFET Q1 and the drain of the isolation MOSFET Q2 are connected in series.

[0031] A capacitor C12 and a capacitor C13 are connected in series between the source of the first-charge MOSFET Q1 and the source of the isolation MOSFET Q2.

[0032] Preferably, the control isolation output circuit proposed in this application further includes: a filter circuit connected to the positive terminal C+ and the negative terminal C- of the power supply;

[0033] The filter circuit includes capacitor C23 and capacitor C29, which are connected in series.

[0034] Preferably, a control isolation output circuit further includes: a protection circuit connected to the positive terminal C+ and the negative terminal C- of the power supply;

[0035] The protection circuit includes a Schottky diode D3.

[0036] Preferably, the control isolation output circuit proposed in this application includes: the sampling resistor includes resistor R38 and resistor R40;

[0037] The resistor R40 is connected to the battery pack, and its other end is connected to the negative terminal C- of the power supply.

[0038] The resistor R40 and the resistor R38 are connected in parallel.

[0039] A capacitor C12 and a capacitor C13 are connected in series between the source (S) of the primary charging MOSFET Q1 and the source (S) of the isolation MOSFET Q2. This reduces voltage fluctuations during charging, improves charging stability, and prevents irregular current from damaging the battery or load. The series design of capacitors C12 and C13 effectively filters noise and high-frequency signals at the power input, reducing the risk of equipment failure due to power supply noise. Furthermore, a Schottky diode D3 provides bidirectional protection for the circuit's power supply.

[0040] Connecting resistors R38 and R40 in parallel effectively manages the current during charging, preventing overcharging and overheating of the battery due to excessive current. By limiting the current, battery damage or system malfunctions are avoided, which helps improve charging efficiency and protect battery safety.

[0041] In a second aspect, a charger includes: the charger employing a control isolation output circuit as described in any of the first aspects.

[0042] This application offers significant advantages in improving the efficiency and safety of battery management systems through precise current and voltage monitoring, overcurrent protection, voltage regulation, isolation, and multiple protection mechanisms. It is suitable for efficient and stable battery charging and management, providing strong technical support, particularly in battery voltage and current control, power supply stability, and battery safety protection. It is applicable to various application scenarios, with broad application potential, especially in energy management systems.

[0043] Compared with the prior art, the advantages of this application are as follows:

[0044] This application provides a control isolation output circuit and charger. The isolation MOSFET Q2 effectively isolates the power supply from the load, preventing direct electrical connection between the power supply and the battery pack. Fuses F1 and F2 provide overcurrent protection, rapidly disconnecting the circuit when the current exceeds a predetermined safe value. Resistors R38 and R40 enable precise current or voltage sampling, allowing real-time monitoring of the battery pack's voltage and current status. A secondary charging MOSFET Q1 controls the charging process, precisely regulating the battery charging flow by controlling the MOSFET's switching. Attached Figure Description

[0045] Figure 1 This is a flowchart of a control isolation output circuit according to one embodiment of this application.

[0046] Figure 2 This is a circuit diagram of a control isolation output circuit in one embodiment of this application.

[0047] Figure 3 This is a schematic diagram of a front-end AFE chip U1 for controlling an isolated output circuit in one embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0049] Example 1, as Figure 1 As shown, this application provides a control isolation output circuit, including a front-end AFE chip U1, a recharge MOSFET Q1, an isolation MOSFET Q2, a fuse F1, a fuse F2, a sampling resistor, and a battery pack.

[0050] The CHG pin of the front-end AFE chip U1 is connected to the gate of a first-charge MOSFET Q1, and the CHG pin of the front-end AFE chip U1 is also connected to the gate of an isolation MOSFET Q2.

[0051] The drain of the primary charging MOSFET Q1 is connected to the drain of the isolation MOSFET Q2, and the source of the primary charging MOSFET Q1 is connected to the battery pack through the fuse F1.

[0052] The source terminal of the isolation MOSFET Q2 is connected to the positive power supply terminal C+ through fuse F2;

[0053] One end of the sampling resistor is connected to the battery pack, and the other end is connected to the negative terminal P- / C- of the power supply.

[0054] When power is connected, the BMS is in charging mode. Electrical isolation between the battery pack and the power supply is achieved through the use of isolation MOSFET Q2, ensuring that the battery pack and power supply are not directly connected and reducing the risk of interference between them. A secondary charging MOSFET Q1 is used to control the charging process, precisely regulating the battery charging current to ensure that overvoltage or overcurrent problems do not occur during battery charging. The GHC pin of the front-end AFE chip U1 controls the switching of the MOSFETs, thereby achieving dynamic adjustment of the charging process. Overcurrent protection is also provided through fuses F1 and F2 to prevent further damage or fire risks.

[0055] Preferred, such as Figure 2 , Figure 3As shown, the control isolation output circuit further includes:

[0056] The CHG pin of the front-end AFE chip U1 is connected in series with the isolation MOSFET Q2, along with transistor Q12, diode D7, diode D8, resistor R36, and resistor R26.

[0057] The emitter of transistor Q12 is connected to resistors R36 and R35, respectively.

[0058] The other end of the resistor R35 is connected to the base of the transistor Q12;

[0059] The collector (c) of transistor Q12 is connected to the anode of diode D7, and the cathode of diode D7 is also connected to the base (b) of transistor Q9.

[0060] The base of transistor Q9 is connected to fuse F2 via resistor R19;

[0061] The collector of transistor Q9 is connected to fuse F2 via resistor R16;

[0062] The emitter (e) of transistor Q9 is connected to the cathode of diode D8.

[0063] Preferably, the control isolation output circuit further includes: the negative terminal of the diode D8 is connected to resistor R26, and one end of resistor R18 and Zener diode Z4 are connected respectively;

[0064] The other end of the resistor R18 and the Zener diode Z4 is connected to the fuse F2;

[0065] The other end of the resistor R26 is connected to the gate of the isolation MOSFET Q2.

[0066] Preferably, the control isolation output circuit further includes:

[0067] The CHG pin of the front-end AFE chip U1 is also connected in series with resistors R33 and R23 to the first-charge MOSFET Q1.

[0068] The other end of the resistor R33 is connected to the Zener diode Z3;

[0069] The other end of the Zener diode Z3 is connected to the fuse F1;

[0070] The resistor R23 is also connected in parallel with the resistor R17.

[0071] Preferably, the control isolation output circuit further includes:

[0072] The base of transistor Q12 is connected in series with resistors R25 and R109 and then connected to the VBAT pin of the front-end AFE chip U1.

[0073] The circuit precisely controls the operating state of transistor Q12 by connecting resistors R25 and R36 in parallel via the VBAT pin of the front-end AFE chip U1. The circuit formed by resistors R25 and R36 and transistor Q12 regulates the transistor's on / off state. Zener diode Z3 is connected to the source (S) of a rechargeable MOSFET Q1 to stabilize current changes during charging. Diodes D7 and D8 form a reverse voltage protection circuit, while Zener diode Z3 provides overvoltage protection. Connecting it in parallel with resistor R17 further improves voltage stability. Resistors R25, R36, and R35 precisely control the conduction state of transistor Q12.

[0074] Preferably, a control isolation output circuit further includes:

[0075] The drain of the first-charge MOSFET Q1 and the drain of the isolation MOSFET Q2 are connected in series.

[0076] A capacitor C12 and a capacitor C13 are connected in series between the source of the first-charge MOSFET Q1 and the source of the isolation MOSFET Q2.

[0077] The source (S) of the first-stage charging MOSFET Q1 is connected to capacitor C12, which is then connected in series with capacitor C13 to form a charging path. The series connection of capacitors C12 and C13 smooths voltage fluctuations, filters power supply noise, and optimizes current control during charging. This series connection also improves circuit stability and reduces high-frequency power supply noise. Connecting the source (S) of the isolation MOSFET Q2 to capacitor C13 provides isolation, preventing unnecessary feedback or voltage interference, while simultaneously achieving stable voltage regulation.

[0078] Preferably, a control isolation output circuit further includes: a filter circuit connected to the positive terminal C+ and the negative terminal C- of the power supply;

[0079] The filter circuit includes capacitor C23 and capacitor C29, which are connected in series.

[0080] Preferably, a control isolation output circuit further includes: a protection circuit connected to the positive terminal C+ and the negative terminal C- of the power supply;

[0081] The protection circuit includes a Schottky diode D3.

[0082] The gate (G) of the first-stage charging MOSFET Q1 is connected to the circuit via resistor R23, providing an appropriate gate drive voltage for the MOSFET. Resistor R23 regulates the switching on and off of the MOSFET, enabling more precise control of current and voltage during charging, thereby improving charging efficiency and protecting battery safety.

[0083] When an overcurrent or short circuit occurs in the circuit, the combined action of diode D3 and capacitor C23 effectively filters and stabilizes the current, preventing equipment damage caused by overcurrent. Capacitor C23 buffers instantaneous current fluctuations, while diode D3 provides directional protection, preventing reverse current from flowing in.

[0084] Preferably, the control isolation output circuit includes: the sampling resistor includes resistor R38 and resistor R40;

[0085] The resistor R40 is connected to the battery pack, and its other end is connected to the negative terminal C- of the power supply.

[0086] The resistor R40 and the resistor R38 are connected in parallel.

[0087] Resistors R38 and R40 are used as sampling resistors to monitor current changes. Resistor R40 is connected to the battery pack and to the negative terminal C- of the power supply to measure the current in real time, further enhancing the power supply's isolation protection and ensuring the stability and protection of the power system against external loads.

[0088] Example 2: A charger, comprising: the charger employing a control isolation output circuit as described in any of Examples 1.

[0089] The solution provided in this application achieves efficient overcurrent and overvoltage protection for the battery charging circuit, ensuring safe isolation between the battery pack and the power source. It also provides monitoring and optimization of the battery charging process through precise current sampling, and enhances circuit stability and reduces interference by utilizing voltage regulation and isolation mechanisms. This supports the efficient operation of the battery management system and improves the safety of the charging process. When applied in vehicle battery management, it enhances intelligence and safety, and is suitable for battery management, charging systems, and battery protection and optimization in intelligent vehicles.

[0090] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0091] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] Although the description of this application has been given in conjunction with the specific embodiments described above, it will be apparent to those skilled in the art that many substitutions, modifications, and variations can be made based on the foregoing. Therefore, all such substitutions, modifications, and variations are included within the spirit and scope of the appended claims.

Claims

1. A control isolation output circuit, characterized in that: This includes the front-end AFE chip U1, the primary charging MOSFET Q1, the isolation MOSFET Q2, the fuse F1, the fuse F2, the sampling resistor, and the battery pack. The CHG pin of the front-end AFE chip U1 is connected to the gate of a first-charge MOSFET Q1, and the CHG pin of the front-end AFE chip U1 is also connected to the gate of an isolation MOSFET Q2. The drain of the primary charging MOSFET Q1 is connected to the drain of the isolation MOSFET Q2, and the source of the primary charging MOSFET Q1 is connected to the battery pack through the fuse F1. The source terminal of the isolation MOSFET Q2 is connected to the positive power supply terminal C+ through fuse F2; One end of the sampling resistor is connected to the battery pack, and the other end is connected to the negative terminal P- / C- of the power supply.

2. The control isolation output circuit according to claim 1, characterized in that, Also includes: The CHG pin of the front-end AFE chip U1 is connected in series with the isolation MOSFET Q2, along with transistor Q12, diode D7, diode D8, resistor R36, and resistor R26. The emitter of transistor Q12 is connected to resistors R36 and R35, respectively. The other end of the resistor R35 is connected to the base of the transistor Q12; The collector (c) of transistor Q12 is connected to the anode of diode D7, and the cathode of diode D7 is also connected to the base (b) of transistor Q9. The base of transistor Q9 is connected to fuse F2 via resistor R19; The collector of transistor Q9 is connected to fuse F2 via resistor R16; The emitter (e) of transistor Q9 is connected to the cathode of diode D8.

3. The control isolation output circuit according to claim 2, characterized in that, Also includes: The negative terminal of diode D8 is connected to resistor R26, resistor R18 and one end of Zener diode Z4 respectively. The other end of the resistor R18 and the Zener diode Z4 is connected to the fuse F2; The other end of the resistor R26 is connected to the gate of the isolation MOSFET Q2.

4. A control isolation output circuit according to claim 3, characterized in that, Also includes: The CHG pin of the front-end AFE chip U1 is also connected in series with resistors R33 and R23 to the first-charge MOSFET Q1. The other end of the resistor R33 is connected to the Zener diode Z3; The other end of the Zener diode Z3 is connected to the fuse F1; The resistor R23 is also connected in parallel with the resistor R17.

5. A control isolation output circuit according to claim 4, characterized in that, Also includes: The base of transistor Q12 is connected in series with resistors R25 and R109 and then connected to the VBAT pin of the front-end AFE chip U1.

6. A control isolation output circuit according to claim 5, characterized in that, Also includes: The drain of the first-charge MOSFET Q1 and the drain of the isolation MOSFET Q2 are connected in series. A capacitor C12 and a capacitor C13 are connected in series between the source of the first-charge MOSFET Q1 and the source of the isolation MOSFET Q2.

7. A control isolation output circuit according to claim 1, characterized in that, Also includes: A filter circuit connected to the positive terminal C+ and the negative terminal C- of the power supply; The filter circuit includes capacitor C23 and capacitor C29, which are connected in series.

8. A control isolation output circuit according to claim 7, characterized in that, Also includes: A protection circuit connected to the positive terminal C+ and the negative terminal C- of the power supply; The protection circuit includes a Schottky diode D3.

9. A control isolation output circuit according to claim 1, characterized in that: The sampling resistors include resistor R38 and resistor R40; The resistor R40 is connected to the battery pack, and its other end is connected to the negative terminal C- of the power supply. The resistor R40 and the resistor R38 are connected in parallel.

10. A charger, characterized in that: The charger employs a control isolation output circuit as described in any one of claims 1-9.

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