Anti-electromagnetic interference electronic chip high-density wiring structure

Abstract

The utility model discloses an anti-electromagnetic interference electronic chip high-density wiring structure, and belongs to the field of electronic chips. An anti-electromagnetic interference electronic chip high-density wiring structure comprises a circuit substrate, a space expansion mechanism is arranged on the surface of a wire carrier plate, an anti-electromagnetic interference mechanism is arranged in the wire carrier plate, and an efficient heat dissipation mechanism is arranged on the surfaces of the wire carrier plate and a carrier plate body. When the wiring structure is used, the performance and the power efficiency of equipment are improved, meanwhile, the size and the weight of the wiring structure are reduced, the first chip and the second chip can keep stable operation in a complex environment when the wiring structure is used, meanwhile, high-frequency noise is restrained, the crosstalk phenomenon is reduced, and the wiring structure is suitable for large-scale popularization and application. And moreover, when the wiring structure is used, adverse effects on the performance and physical structures of the first chip and the second chip caused by overheating are prevented, and meanwhile, the phenomenon that equipment frequently breaks down due to overheating is avoided.

Description

Technical Field

[0001] This utility model relates to the field of electronic chip technology, and in particular to a high-density wiring structure for electronic chips that resists electromagnetic interference. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, refers to a silicon wafer containing integrated circuits. The main purpose of chip wiring is to achieve efficient signal transmission and connection to ensure the performance and function of the chip. Existing wiring structures have shortcomings such as noise and interference that may cause signal distortion. These problems may affect the performance, reliability, and manufacturing cost of the chip. In order to meet market needs, a high-density wiring structure for electronic chips that is resistant to electromagnetic interference is required.

[0003] A search revealed Chinese patent authorization number 202420153687.1, which discloses a high-density wiring packaging structure for chips, including a circuit substrate; an upper carrier board disposed above the circuit substrate, the upper carrier board comprising multiple sets of carrier boards, adjacent sets of carrier boards being connected by wire bonding; all sets of carrier boards are connected to the upper end of the circuit substrate. The high-density wiring packaging structure in the aforementioned patent has the following shortcomings: the existing wiring structure has insufficient electromagnetic interference resistance during use, which prevents the first and second chips from maintaining stable operation in complex environments, and also increases high-frequency noise and crosstalk; in addition, the existing wiring structure has insufficient heat dissipation efficiency during use, which makes it prone to overheating, adversely affecting the performance and physical structure of the first and second chips, and easily leading to frequent device failures due to overheating. Utility Model Content

[0004] The purpose of this invention is to solve the problems of insufficient wiring space, poor electromagnetic interference resistance, and low heat dissipation efficiency in the existing wiring structure, and to propose a high-density wiring structure for electronic chips with electromagnetic interference resistance.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An electromagnetic interference-resistant high-density wiring structure for electronic chips includes a circuit substrate, a conductor carrier plate disposed on top of the circuit substrate, a carrier plate body mounted on the bottom surface of the conductor carrier plate, and second metal ball pins with equal spacing mounted on the bottom surface of the carrier plate body. The bottom surfaces of the second metal ball pins are in contact with the surface of the circuit substrate. A packaging plate is mounted on the top surface of the conductor carrier plate. An expansion space mechanism is provided on the surface of the conductor carrier plate. An electromagnetic interference-resistant mechanism is provided inside the conductor carrier plate. High-efficiency heat dissipation mechanisms are provided on the surfaces of the conductor carrier plate and the carrier plate body.

[0007] As a preferred technical solution of this application, a first die is disposed inside the packaging board, and a second die is disposed inside the packaging board. The surfaces of the bottom positions of both the first and second dies are equipped with equally spaced first metal ball pins. The surfaces of the bottom positions of the first metal ball pins are in contact with the surface of the conductor carrier. The first and second dies are connected to the conductor carrier via the first metal ball pins. The conductor carrier and the carrier body are connected to the circuit board via the second metal ball pins. A first chip is disposed on the surface of the top position of the second die, and a second chip is disposed on the surface of the top position of the first die. A silicon interposer for signal enhancement is disposed at the center of the surface of the conductor carrier. The surfaces of the bottom positions of the first metal ball pins are in contact with the surface of the silicon interposer. Signals between the first and second dies are connected through the silicon interposer, and external signals are connected to the circuit board through the silicon interposer.

[0008] As a preferred technical solution of this application, the extended space mechanism is composed of a first thin insulating dielectric layer, a first copper foil, a second thin insulating dielectric layer, a second copper foil, blind holes and conductive paths. The surface of the conductor carrier is equipped with a second copper foil, the surface at the top position of the second thin insulating dielectric layer is equipped with a second thin insulating dielectric layer, the surface at the top position of the second thin insulating dielectric layer is equipped with a first copper foil, and the surface at the top position of the first copper foil is equipped with a first thin insulating dielectric layer.

[0009] As a preferred technical solution of this application, the surfaces of the first thin insulating dielectric layer and the second thin insulating dielectric layer are provided with equally spaced blind holes by laser drilling technology, and the interior of the blind holes is provided with conductive paths for conducting electricity by electroplating.

[0010] As a preferred technical solution of this application, the anti-electromagnetic interference mechanism is composed of silicon carbide, a cavity, conductive adhesive and a ternary alloy film. The interior of the conductor carrier is provided with a cavity. The inner wall of the cavity is fitted with silicon carbide to improve the anti-interference capability of the first chip and the second chip. The surface of the bottom position of the silicon carbide is fitted with conductive adhesive for anti-electromagnetic interference of the first chip and the second chip.

[0011] As a preferred technical solution of this application, a ternary alloy film for improving the protection effect on the first chip and the second chip is installed on the surface of the bottom position of the conductive adhesive, and the surface of the bottom position of the ternary alloy film is fixed to the inner wall of the cavity.

[0012] As a preferred technical solution of this application, the high-efficiency heat dissipation mechanism is composed of heat dissipation fins, mounting screws, heat dissipation through holes and heat dissipation copper plate. The surfaces of the conductor carrier and the carrier body on both sides are provided with heat dissipation fins for heat dissipation. The surfaces of the heat dissipation fins are threaded with mounting screws. One end of the mounting screw passes through the heat dissipation fin and is threadedly fastened to the surface of the conductor carrier.

[0013] As a preferred technical solution of this application, the inner wall of the conductor carrier is equipped with a heat dissipation copper plate for heat conduction. The heat dissipation copper plate and the inner wall of the conductor carrier are provided with heat dissipation through holes at equal intervals. The heat dissipation through holes are connected to the interior of the conductor carrier.

[0014] Compared with the prior art, this utility model provides a high-density wiring structure for electronic chips that resists electromagnetic interference, and has the following beneficial effects:

[0015] 1. This high-density wiring structure for electromagnetic interference-resistant electronic chips, through the setting of an expansion space mechanism, achieves the functions of improving the performance and power efficiency of the equipment, while reducing the size and weight of the wiring structure, thus solving the problem of insufficient wiring space in the prior art;

[0016] 2. The high-density wiring structure of the electronic chip with electromagnetic interference resistance, through the electromagnetic interference resistance mechanism, enables the first chip and the second chip to maintain stable operation in complex environments. At the same time, it suppresses high-frequency noise and reduces crosstalk, thus solving the problem of insufficient electromagnetic interference resistance in the prior art.

[0017] 3. This high-density wiring structure for electromagnetic interference-resistant electronic chips, through its efficient heat dissipation mechanism, avoids the adverse effects of overheating on the performance and physical structure of the first and second chips. At the same time, it avoids frequent equipment failures caused by overheating, thus solving the problem of insufficient heat dissipation efficiency in existing technologies. Attached Figure Description

[0018] Figure 1 This is a three-dimensional structural diagram of the present invention;

[0019] Figure 2 This is a schematic diagram of the front cross-sectional structure of this utility model;

[0020] Figure 3This is a top view cross-sectional structural diagram of the present invention;

[0021] Figure 4 For the present utility model Figure 2 A schematic diagram of the enlarged structure of the space extension mechanism;

[0022] Figure 5 For the present utility model Figure 2 Enlarged structural schematic diagram of the electromagnetic interference suppression mechanism;

[0023] Figure 6 For the present utility model Figure 3 Enlarged structural diagram of a medium-to-high efficiency heat dissipation mechanism.

[0024] In the picture:

[0025] 1. Circuit board; 101. Conductor carrier; 102. Packaging board; 103. Carrier body; 104. First chip; 105. First die; 106. Second chip; 107. First metal ball pin; 108. Second metal ball pin; 109. Silicon interposer; 110. Second die; 2. Space expansion mechanism; 21. First thin insulating dielectric layer; 22. First copper foil; 23. Second thin insulating dielectric layer; 24. Second copper foil; 25. Blind via; 26. Conductive path; 3. Electromagnetic interference suppression mechanism; 31. Silicon carbide; 32. Cavity; 33. Conductive adhesive; 34. Ternary alloy film; 4. High-efficiency heat dissipation mechanism; 41. Heat dissipation fins; 42. Mounting screws; 43. Heat dissipation through-holes; 44. Heat dissipation copper plate. Detailed Implementation

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0027] Example:

[0028] Reference Figure 1-3A high-density wiring structure for an electronic chip with electromagnetic interference resistance includes a circuit substrate 1. A conductor carrier 101 is disposed on top of the circuit substrate 1. A carrier body 103 is mounted on the bottom surface of the conductor carrier 101. Equally spaced second metal ball pins 108 are mounted on the bottom surface of the carrier body 103. The bottom surfaces of the second metal ball pins 108 are in contact with the surface of the circuit substrate 1. A packaging plate 102 is mounted on the top surface of the conductor carrier 101. A first die 105 and a second die 110 are disposed inside the packaging plate 102. Equally spaced first metal ball pins 107 are mounted on the bottom surfaces of both the first die 105 and the second die 110. The bottom surfaces of the first metal ball pins 107 are in contact with the surface of the circuit substrate 1. The surfaces of the conductor carrier 101 are in contact with each other. The first die 105 and the second die 110 are connected to the conductor carrier 101 through the first metal ball pin 107. The conductor carrier 101 and the carrier body 103 are connected to the circuit board 1 through the second metal ball pin 108. A first chip 104 is mounted on the surface of the top position of the second die 110. A second chip 106 is mounted on the surface of the top position of the first die 105. A silicon interposer 109 for signal enhancement is mounted at the center position of the surface of the conductor carrier 101. The surface of the bottom position of the first metal ball pin 107 is in contact with the surface of the silicon interposer 109. The signal between the first die 105 and the second die 110 is connected through the silicon interposer 109, and the external signal is connected to the circuit board 1 through the silicon interposer 109.

[0029] Reference Figure 2 and Figure 4 Furthermore, the conductor carrier 101 includes an expansion space mechanism 2 on its surface. The expansion space mechanism 2 comprises a first thin insulating dielectric layer 21, a first copper foil 22, a second thin insulating dielectric layer 23, a second copper foil 24, blind holes 25, and conductive paths 26. The second copper foil 24 is mounted on the surface of the conductor carrier 101. A second thin insulating dielectric layer 23 is mounted at its top position, and a first copper foil 22 is mounted at its top position. A first thin insulating dielectric layer 21 is mounted at its top position. Blind holes 25 with equal spacing are drilled on the surfaces of the first and second thin insulating dielectric layers 21 and 23 using laser drilling technology. Conductive paths 26 for conduction are electroplated inside the blind holes 25. By providing the expansion space mechanism, the performance and power efficiency of the equipment can be improved, while the size and weight of the wiring structure are reduced.

[0030] Reference Figure 2 and Figure 5Furthermore, the conductor carrier 101 includes an electromagnetic interference (EMI) suppression mechanism 3. This mechanism 3 comprises silicon carbide 31, a cavity 32, conductive adhesive 33, and a ternary alloy film 34. The conductor carrier 101 has cavities 32 inside each cavity. The inner wall of each cavity 32 is fitted with silicon carbide 31 to enhance the EMI suppression capabilities of the first chip 104 and the second chip 106. The bottom surface of the silicon carbide 31 is fitted with conductive adhesive 33 for EMI suppression of the first chip 104 and the second chip 106. The bottom surface of the conductive adhesive 33 is fitted with a ternary alloy film 34 to enhance the protection of the first chip 104 and the second chip 106. The bottom surface of the ternary alloy film 34 is fixed to the inner wall of the cavity 32. By implementing this EMI suppression mechanism, the first chip 104 and the second chip 106 can maintain stable operation in complex environments, while simultaneously suppressing high-frequency noise and reducing crosstalk.

[0031] Reference Figure 3 and Figure 6 Furthermore, the device includes a high-efficiency heat dissipation mechanism 4 on the surfaces of the conductor carrier 101 and the carrier body 103. The high-efficiency heat dissipation mechanism 4 consists of heat dissipation fins 41, mounting screws 42, heat dissipation through holes 43, and a heat dissipation copper plate 44. Heat dissipation fins 41 for heat dissipation are provided on both sides of the conductor carrier 101 and the carrier body 103. Mounting screws 42 are threaded onto the surfaces of the heat dissipation fins 41, with one end of each screw penetrating the heat dissipation fin 41 and being threadedly fastened to the surface of the conductor carrier 101. Heat dissipation copper plates 44 for heat conduction are installed on the inner walls of the conductor carrier 101. Heat dissipation through holes 43 with equal spacing are provided on both the heat dissipation copper plate 44 and the inner walls of the conductor carrier 101, and these through holes 43 communicate with the interior of the conductor carrier 101. By providing this high-efficiency heat dissipation mechanism, overheating can be prevented from adversely affecting the performance and physical structure of the first chip 104 and the second chip 106. Simultaneously, it avoids frequent equipment failures caused by overheating.

[0032] Specifically, in use, the high-density wiring structure of this electromagnetic interference-resistant electronic chip is as follows: First, the circuit board 1 is placed in the designated position. The user coats the conductor carrier 101 with insulating material to form a first thin insulating dielectric layer 21 and a second thin insulating dielectric layer 23. Then, tiny blind holes 25 are drilled using laser drilling technology. The diameter of these blind holes 25 is typically tens of micrometers. Subsequently, electroplating is performed in the blind holes 25 to form conductive paths 26, enabling electrical connections between different layers. Circuit patterns are fabricated on the first thin insulating dielectric layer 21 using processes such as photolithography and etching, controlling the line width and spacing to an extremely small scale to achieve high density of lines per unit area. After completing the fabrication of one layer of wiring, the process involves repeated steps such as coating an insulating layer, drilling and copper plating, and wiring fabrication to form a multi-layer structure. Through interlayer interconnection technology, the wiring layers are interwoven to achieve efficient signal transmission and complex function integration, ultimately achieving high-density interconnection. At the same time, by alternately stacking the first copper foil 22 with the first thin insulating dielectric layer 21 and the second thin insulating dielectric layer 23 with the second copper foil 24, each additional layer is equivalent to adding a layer of wiring space, thereby expanding the wiring space of the wiring structure. This improves the performance and power efficiency of the equipment when using the wiring structure, while reducing the size and weight of the wiring structure.

[0033] Subsequently, the second die 110 and the first die 105 are connected to the conductor carrier 101 and the carrier body 103 through the first metal ball pin 107. The conductor carrier 101 and the carrier body 103 are connected to the circuit board 1 through the second metal ball pin 108. These components work together to achieve efficient signal transmission and optimize the performance of the first chip 104 and the second chip 106. The circuit board 1, as the basis of the wiring structure, provides a mounting platform for the first chip 104, the second chip 106, and other components. Under the action of the conductor carrier 101 and the carrier body 103, it provides electrical connection and mechanical support to ensure the normal operation of the first chip 104 and the second chip 106. The carrier body 103 realizes the connection between the first chip 104 and the second chip 106 through multiple sets of carriers and wire bonding. Under the action of the silicon interposer 109, the high-speed signal between the second die 110 and the first die 105 is improved. External signals are connected to the circuit board 1 through the silicon interposer 109, improving the overall performance.

[0034] Subsequently, the ternary alloy film 34 reduces interference to the first chip 104 and the second chip 106 by reflecting or absorbing electromagnetic waves. The conductive adhesive 33 provides the wiring structure with good conductivity and electromagnetic shielding performance, enabling it to provide electromagnetic interference protection in chip packaging. The silicon carbide 31 further enhances the electromagnetic interference resistance of the wiring structure, making it more practical and realizing its electromagnetic interference resistance function. This allows the first chip 104 and the second chip 106 to maintain stable operation in complex environments during use, while suppressing high-frequency noise and reducing crosstalk.

[0035] Subsequently, due to energy loss during electronic signal transmission, this loss is converted into heat. Therefore, the first chip 104 and the second chip 106 generate a large amount of heat during operation. Heat sink fins 41 are mounted on the surfaces of the wire carrier 101 and the carrier body 103 respectively using mounting screws 42. The heat generated by the first chip 104 and the second chip 106 during operation is conducted onto the surface of the wire carrier 101. The wire carrier 101, as part of the heat dissipation path, can conduct heat from the surfaces of the first chip 104 and the second chip 106 to the external environment. The heat sink copper plate 44... The heat inside the wire carrier board 101 is conducted out and enters the surface of the heat dissipation fins 41 through the heat dissipation holes 43. Under the action of the heat dissipation fins 41, the heat dissipation efficiency of the wire carrier board 101 is improved. When the first chip 104 and the second chip 106 generate a lot of heat, it can directly help dissipate heat to achieve the function of efficient heat dissipation of the wiring structure. This prevents overheating from adversely affecting the performance and physical structure of the first chip 104 and the second chip 106 during the use of the wiring structure. At the same time, it avoids the phenomenon of frequent equipment failure due to overheating, and finally completes the use of the wiring structure.

[0036] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A high-density wiring structure for electronic chips that resists electromagnetic interference, comprising a circuit board (1), characterized in that: A conductor carrier board (101) is disposed above the circuit board (1). A carrier body (103) is mounted on the bottom surface of the conductor carrier board (101). The bottom surface of the carrier body (103) is mounted with equally spaced second metal ball pins (108). The bottom surface of the second metal ball pins (108) is in contact with the surface of the circuit board (1). An encapsulation board (102) is mounted on the top surface of the conductor carrier board (101). An expansion space mechanism (2) is disposed on the surface of the conductor carrier board (101). An anti-electromagnetic interference mechanism (3) is disposed inside the conductor carrier board (101). A high-efficiency heat dissipation mechanism (4) is disposed on the surfaces of the conductor carrier board (101) and the carrier body (103).

2. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 1, characterized in that: The encapsulation board (102) has a first die (105) and a second die (110) inside. Both the first die (105) and the second die (110) have equally spaced first metal ball pins (107) mounted on their bottom surfaces. The bottom surfaces of the first metal ball pins (107) are in contact with the surface of the wire carrier board (101). The first die (105) and the second die (110) are connected to the wire carrier board (101) via the first metal ball pins (107). The wire carrier board (101) and the carrier board body (103) are connected via second metal ball pins (108). The first chip (104) is mounted on the surface of the top position of the second chip (110), and the second chip (106) is mounted on the surface of the top position of the first chip (105). A silicon interposer (109) for signal enhancement is mounted at the center position of the surface of the conductor carrier (101). The surface of the bottom position of the first metal ball pin (107) is in contact with the surface of the silicon interposer (109). The signal between the first chip (105) and the second chip (110) is connected through the silicon interposer (109), and the external signal is connected to the circuit substrate (1) through the silicon interposer (109).

3. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 1, characterized in that: The extended space mechanism (2) is composed of a first thin insulating dielectric layer (21), a first copper foil (22), a second thin insulating dielectric layer (23), a second copper foil (24), a blind hole (25), and a conductive path (26). The surface of the conductor carrier (101) is equipped with the second copper foil (24). The surface of the second thin insulating dielectric layer (23) at the top position is equipped with the second thin insulating dielectric layer (23). The surface of the second thin insulating dielectric layer (23) at the top position is equipped with the first copper foil (22). The surface of the first copper foil (22) at the top position is equipped with the first thin insulating dielectric layer (21).

4. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 3, characterized in that: The surfaces of the first thin insulating dielectric layer (21) and the second thin insulating dielectric layer (23) are provided with equally spaced blind holes (25) by laser drilling technology, and the interior of the blind holes (25) is provided with conductive paths (26) for conducting electricity by electroplating.

5. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 1, characterized in that: The anti-electromagnetic interference mechanism (3) is composed of silicon carbide (31), cavity (32), conductive adhesive (33) and ternary alloy film (34). The inside of the conductor carrier (101) is provided with cavity (32). The inner wall of the cavity (32) is equipped with silicon carbide (31) to improve the anti-interference ability of the first chip (104) and the second chip (106). The surface of the bottom position of the silicon carbide (31) is equipped with conductive adhesive (33) for anti-electromagnetic interference of the first chip (104) and the second chip (106).

6. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 5, characterized in that: The conductive adhesive (33) has a ternary alloy film (34) installed on its bottom surface to improve the protection of the first chip (104) and the second chip (106). The bottom surface of the ternary alloy film (34) is fixed to the inner wall of the cavity (32).

7. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 1, characterized in that: The high-efficiency heat dissipation mechanism (4) consists of heat dissipation fins (41), mounting screws (42), heat dissipation through holes (43) and heat dissipation copper plate (44). The surfaces of both sides of the conductor carrier plate (101) and the carrier plate body (103) are provided with heat dissipation fins (41) for heat dissipation. The surfaces of the heat dissipation fins (41) are threaded with mounting screws (42). One end of the mounting screw (42) passes through the heat dissipation fins (41) and is threadedly fastened to the surface of the conductor carrier plate (101).

8. The high-density wiring structure for an electronic chip with electromagnetic interference resistance according to claim 1, characterized in that: The inner wall of the conductor carrier plate (101) is equipped with a heat dissipation copper plate (44) for heat conduction. The heat dissipation copper plate (44) and the inner wall of the conductor carrier plate (101) are provided with heat dissipation through holes (43) at equal intervals. The heat dissipation through holes (43) are connected to the interior of the conductor carrier plate (101).

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