Dual-channel isolated SPI circuit for MCU in supercapacitor protection board

Abstract

This utility model discloses a dual-channel isolated SPI circuit for a supercapacitor protection board MCU. The circuit includes an embedded chip, a first digital isolation chip, a second digital isolation chip, a first AFE chip, and a second AFE chip. The embedded chip is electrically connected to the first AFE chip via the first digital isolation chip, and also to the second AFE chip via the second digital isolation chip. The embedded chip is model HK32F103CET6A. In this utility model, the embedded chip sends / receives data to the first and second digital isolation chips through seven I / O ports, and controls the enable pins (EN) of the first and second digital isolation chips to control whether the digital isolation chips operate. This solves the problems of data transmission failure between the two digital isolation chips and excessive I / O port resource consumption, thus providing better protection for the supercapacitor.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to a dual-channel isolated SPI circuit for a supercapacitor protection board MCU. Background Technology

[0002] For electrical safety considerations in high-voltage platforms, most current battery management AFE chips require isolated communication with embedded MCU chips via digital isolation chips. A one-to-one communication method is commonly used, with one SPI hardware interface corresponding to one digital isolation chip for communication with the AFE chip. However, due to the limited number of SPI hardware interfaces in existing embedded MCUs, this method is only suitable for applications requiring a small number of SPI interfaces. If a large number of SPI interfaces are needed, there will be insufficient hardware resources for matching and use, leading to increased costs for electronic components.

[0003] Additionally, when two isolation chips are enabled simultaneously, if the CS1 chip select pin is enabled and the CS2 chip select pin is disabled, the data transmitted from the MISO pin of the first digital isolation chip will be raised by the second digital isolation chip, making it impossible for the embedded chip MCU to receive the correct data information.

[0004] In summary, a dual-channel isolated SPI circuit for a supercapacitor protection board MCU is designed. Utility Model Content

[0005] To overcome the above-mentioned shortcomings, this utility model provides a dual-channel isolated SPI circuit for a supercapacitor protection board MCU.

[0006] This utility model achieves the above objectives through the following technical solutions:

[0007] A dual-channel isolated SPI circuit for a supercapacitor protection board MCU includes an embedded chip, a first digital isolation chip, a second digital isolation chip, a first AFE chip, and a second AFE chip. The embedded chip is electrically connected to the first AFE chip through the first digital isolation chip, and the embedded chip is electrically connected to the second AFE chip through the second digital isolation chip.

[0008] The embedded chip is model HK32F103CET6A.

[0009] Preferably, pin 15 of the embedded chip is electrically connected to the SCK clock signal terminal of the first digital isolation chip and the SCK clock signal terminal of the second digital isolation chip, pin 16 of the embedded chip is electrically connected to the MISO data signal terminal of the first digital isolation chip and the MISO data signal terminal of the second digital isolation chip, pin 17 of the embedded chip is electrically connected to the AFE chip data signal terminal of the first digital isolation chip and the AFE chip data signal terminal of the second digital isolation chip, pin 14 of the embedded chip is electrically connected to the CS1 signal terminal of the first digital isolation chip, pin 13 of the embedded chip is electrically connected to the CS2 signal terminal of the second digital isolation chip, pin 10 of the embedded chip is electrically connected to the enable pin terminal of the first digital isolation chip, and pin 11 of the embedded chip is electrically connected to the enable pin terminal of the second digital isolation chip.

[0010] Preferably, both the first and second digital isolation chips are model PAI141E71. The digital isolation chip circuit is mainly composed of PAI141E71. Its core function is to electrically isolate the SPI communication between the embedded chip and the first and second AFE chips, so as to ensure that the dangerous signal on the high voltage side is not transmitted to the embedded chip side and damages the device.

[0011] Preferably, both the first AFE chip and the second AFE chip are MT9811, which collects battery data on the high-voltage side and transmits it to the low-voltage side embedded chip via SPI communication.

[0012] The beneficial effects of this utility model are: In the dual-channel isolated SPI circuit for the MCU of the supercapacitor protection board, the embedded chip sends / receives data to the first digital isolation chip and the second digital isolation chip through 7 IO ports, controls the enable pin EN of the first digital isolation chip and the second digital isolation chip, and controls whether the digital isolation chip runs. This solves the problem that the two digital isolation chips cannot transmit data and that the IO ports occupy too many resources, thus providing better protection for the supercapacitor. Attached Figure Description

[0013] This utility model will be described by way of example and with reference to the accompanying drawings, wherein:

[0014] Figure 1 This is the circuit schematic diagram of this utility model;

[0015] Figure 2 This is the circuit schematic diagram of the first digital isolation chip of this utility model;

[0016] Figure 3 This is the circuit schematic diagram of the second digital isolation chip of this utility model. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0018] like Figures 1-3 As shown, a dual-channel isolated SPI circuit for a supercapacitor protection board MCU includes an embedded chip 1, a first digital isolation chip 2, a second digital isolation chip 3, a first AFE chip 4, and a second AFE chip 5. The embedded chip 1 is electrically connected to the first AFE chip 4 through the first digital isolation chip 2, and the embedded chip 1 is electrically connected to the second AFE chip 5 through the second digital isolation chip 3. The first AFE chip 4 and the second AFE chip 5 are front-end analog and battery management chips that send / receive data for SPI communication.

[0019] The embedded chip 1 is model HK32F103CET6A, which is used to send / receive data for SPI communication.

[0020] Specifically, pin 15 of the embedded chip 1 is electrically connected to the SCK clock signal terminal of the first digital isolation chip 2 and the SCK clock signal terminal of the second digital isolation chip 3, pin 16 of the embedded chip 1 is electrically connected to the MISO data signal terminal of the first digital isolation chip 2 and the MISO data signal terminal of the second digital isolation chip 3, pin 17 of the embedded chip 1 is electrically connected to the AFE chip data signal terminal of the first digital isolation chip 2 and the AFE chip data signal terminal of the second digital isolation chip 3, pin 14 of the embedded chip 1 is electrically connected to the CS1 signal terminal of the first digital isolation chip 2, pin 13 of the embedded chip 1 is electrically connected to the CS2 signal terminal of the second digital isolation chip 3, pin 10 of the embedded chip 1 is electrically connected to the enable pin terminal of the first digital isolation chip 2, and pin 11 of the embedded chip 1 is electrically connected to the enable pin terminal of the second digital isolation chip 3.

[0021] Specifically, the first digital isolation chip 2 and the second digital isolation chip 3 are both PAI141E71. The digital isolation chip circuit is mainly composed of PAI141E71. Its core function is to electrically isolate the SPI communication between the embedded chip 1 and the first AFE chip 4 and the second AFE chip 5, so as to ensure that the dangerous signal on the high voltage side will not be transmitted to the embedded chip 1 side and cause damage to the device.

[0022] The first digital isolation chip 2 is electrically connected to the embedded chip 1 via resistors R1, R2, R3, R4, and R5. Similarly, the first digital isolation chip 2 is electrically connected to the first AFE chip 4 via resistors R6, R7, R8, R9, and R10. The second digital isolation chip 3 is electrically connected to the embedded chip 1 and the second AFE chip 5 via corresponding resistors. The first digital isolation chip 2 and the second digital isolation chip 3 are insulated from ground on both sides.

[0023] Specifically, the first AFE chip 4 and the second AFE chip 5 are both MT9811, which collects battery data on the high-voltage side and transmits it to the low-voltage embedded chip 1 via SPI communication.

[0024] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A two-way isolated SPI circuit for a supercap protection board MCU, characterized in that: It includes an embedded chip, a first digital isolation chip, a second digital isolation chip, a first AFE chip, and a second AFE chip. The embedded chip is electrically connected to the first AFE chip through the first digital isolation chip, and the embedded chip is electrically connected to the second AFE chip through the second digital isolation chip. The embedded chip is model HK32F103CET6A.

2. The dual-isolation SPI circuit for a supercap protection board MCU of claim 1, wherein: Pin 15 of the embedded chip is electrically connected to the SCK clock signal terminal of the first digital isolation chip and the SCK clock signal terminal of the second digital isolation chip, respectively. Pin 16 of the embedded chip is electrically connected to the MISO data signal terminal of the first digital isolation chip and the MISO data signal terminal of the second digital isolation chip, respectively. Pin 17 of the embedded chip is electrically connected to the AFE chip data signal terminal of the first digital isolation chip and the AFE chip data signal terminal of the second digital isolation chip, respectively. Pin 14 of the embedded chip is electrically connected to the CS1 signal terminal of the first digital isolation chip. Pin 13 of the embedded chip is electrically connected to the CS2 signal terminal of the second digital isolation chip. Pin 10 of the embedded chip is electrically connected to the enable pin terminal of the first digital isolation chip. Pin 11 of the embedded chip is electrically connected to the enable pin terminal of the second digital isolation chip.

3. The dual-channel isolated SPI circuit for a supercapacitor protection board MCU according to claim 2, characterized in that: Both the first and second digital isolation chips are model PAI141E71.

4. The dual-channel isolated SPI circuit for a supercapacitor protection board MCU according to claim 1, characterized in that: Both the first AFE chip and the second AFE chip are model MT9811.

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