A data acquisition circuit that supports mixed inputs
By designing a data acquisition circuit that supports mixed inputs and using components such as transistors and field-effect transistors, eight-channel data acquisition was achieved, solving the problems of multiple devices and high costs in existing technologies, and realizing flexible signal type configuration and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI MARKAI INTELLIGENT TECH CO LTD
- Filing Date
- 2025-05-23
- Publication Date
- 2026-05-26
Smart Images
Figure CN224289785U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of access control data acquisition circuit technology, and in particular to a data acquisition circuit that supports mixed input. Background Technology
[0002] Industrial environments require the collection of various data types, such as analog voltage, analog current, and digital levels. Different devices are typically used to collect different data types; alternatively, dedicated signal switching chips can be used, but this approach involves complex circuit designs. Furthermore, industrial environments often involve the acquisition and measurement of multiple signals, necessitating multiple devices and thus increasing the cost of data acquisition.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this utility model, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content
[0004] The purpose of this invention is to solve the technical problems existing in the background art. To this end, a data acquisition circuit that supports mixed input is provided, which can receive different types of data signals.
[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0006] A data acquisition circuit supporting mixed inputs includes a transistor Q27, a field-effect transistor Q3, and a voltage follower U2A;
[0007] The base of the transistor Q27 is connected to the logic signal DI1_switch, the collector of the transistor Q27 is electrically connected to one end of the resistor R139, and the other end of the resistor R139 is electrically connected to the input terminal AI1.
[0008] The input terminal AI1 is electrically connected to the drain of the field-effect transistor Q3 through parallel resistors R7 and R8, and the gate of the field-effect transistor Q3 is connected to the logic signal AI1_switch;
[0009] The input terminal AI1 is electrically connected to pin 3 of the voltage follower U2A through resistors R1 and R2 connected in series. Pin 1 of the voltage follower U2A is grounded through resistors R12 and R9 connected in series. The connection point between resistors R12 and R9 serves as the output terminal AIN1.
[0010] The following is a further technical solution of this utility model: the base and emitter of the transistor Q27 are electrically connected by a resistor R114, and the emitter of the transistor Q27 is connected to a 3.3V voltage.
[0011] The following is a further technical solution of this utility model: the gate (G) and source (S) of the field-effect transistor Q3 are electrically connected by a resistor R83, and the source (S) of the field-effect transistor Q3 is grounded.
[0012] The following is a further technical solution of this utility model: the input terminal AI1 is grounded through capacitor RC1.
[0013] The following is a further technical solution of this utility model: the connection point between resistor R1 and resistor R2 is grounded through capacitor C2.
[0014] The following is a further defined technical solution of this utility model: a capacitor C5 and a resistor R15 are connected in parallel between pin 1 and pin 2 of the voltage follower U2A.
[0015] The following is a further technical solution of this utility model, which also includes a Schottky diode Q1. The pin 3 of the Schottky diode Q1 is connected to the line between resistor R12 and resistor R9, the pin 1 of the Schottky diode Q1 is grounded, and the pin 2 of the Schottky diode Q1 is connected to a 3.3V voltage.
[0016] Compared with the prior art, the present invention has the following technical effects:
[0017] This invention features an 8-channel data acquisition circuit, meaning that a single terminal device has 8 inputs. Each channel supports mixed input measurement of digital quantities, analog current, and analog voltage, which greatly reduces the number of field devices and lowers equipment costs. The input signal types can be flexibly configured.
[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a circuit connection diagram of the first data acquisition circuit in this utility model;
[0021] Figure 2 This is a circuit connection diagram of the second data acquisition circuit in this utility model;
[0022] Figure 3This is a circuit connection diagram of the third data acquisition circuit in this utility model;
[0023] Figure 4 This is a circuit connection diagram of the fourth data acquisition circuit in this utility model;
[0024] Figure 5 This is a circuit connection diagram of the fifth data acquisition circuit in this utility model;
[0025] Figure 6 This is a circuit connection diagram of the sixth data acquisition circuit in this utility model;
[0026] Figure 7 This is a circuit connection diagram of the seventh data acquisition circuit in this utility model;
[0027] Figure 8 This is a circuit connection diagram of the eighth data acquisition circuit in this utility model. Detailed Implementation
[0028] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.
[0029] like Figure 1-8 As shown, this embodiment provides a data acquisition circuit that supports mixed input, featuring eight data acquisition circuits, including a first data acquisition circuit, a second data acquisition circuit, a third data acquisition circuit, a fourth data acquisition circuit, a fifth data acquisition circuit, a sixth data acquisition circuit, a seventh data acquisition circuit, and an eighth data acquisition circuit. Therefore, eight signals can be acquired and measured through these eight data acquisition circuits, integrated into a single device.
[0030] like Figure 1-8 As shown, the circuit structures of the eight data acquisition circuits are all identical, and all can support mixed input, meaning they can acquire different types of data (digital quantities, analog current, and analog voltage). Therefore, in this embodiment, only the circuit structure of the first data acquisition circuit is described in detail.
[0031] like Figure 1As shown, the first data acquisition circuit mainly consists of transistor Q27, field-effect transistor Q3, voltage follower U2A, resistors R139, R7, R8, R1, R2, R12, R9, R114, R83, capacitors RC1, C2, C5, resistor R15, and Schottky diode Q1.
[0032] A resistor R114 is electrically connected between the base and emitter of transistor Q27, and the emitter of transistor Q27 is connected to a 3.3V voltage. The base of transistor Q27 is connected to the logic signal DI1_switch. The collector of transistor Q27 is electrically connected to one end of resistor R139, and the other end of resistor R139 is electrically connected to the input terminal AI1. Input terminal AI1 is electrically connected to the drain (D) of field-effect transistor Q3 through parallel resistors R7 and R8. The gate (G) of field-effect transistor Q3 is connected to the logic signal AI1_switch. A resistor R83 is electrically connected between the gate (G) and source (S) of field-effect transistor Q3, and the source (S) of field-effect transistor Q3 is grounded.
[0033] Input terminal AI1 is electrically connected to pin 3 of voltage follower U2A via resistors R1 and R2 connected in series. Pin 1 of voltage follower U2A is grounded via resistors R12 and R9 connected in series. The connection point between resistors R12 and R9 serves as output terminal AIN1. Further, input terminal AI1 is grounded via capacitor RC1. The connection point between resistors R1 and R2 is grounded via capacitor C2.
[0034] A capacitor C5 and a resistor R15 are connected in parallel between pin 1 and pin 2 of the voltage follower U2A.
[0035] Pin 3 of Schottky diode Q1 is connected to the line between resistors R12 and R9, pin 1 of Schottky diode Q1 is grounded, and pin 2 of Schottky diode Q1 is connected to a 3.3V voltage.
[0036] The MCU's I / O control logic signals DI1_switch and AI1_switch are used to measure data of different input types, specifically according to the control logic in the table below:
[0037]
[0038] When the input AI1 simulates a 0-20mA current, the MCU control logic signal DI1_switch is high, transistor Q27 is not conducting, the MCU control logic signal AI1_switch is high, the field-effect transistor Q3 is conducting, and the current flows through resistors R7 and R8 and the field-effect transistor Q3 to GND (i.e., ground terminal), generating a voltage at pin 3 of the voltage follower U2A. The input voltage is output from pin 1 of the voltage follower U2A, and after being divided by resistors R12 and R9, it is input to the MCU's AD pin. The MCU converts the current value into an AD value through AD acquisition and calculation.
[0039] When input AI1 is a digital signal, the MCU control logic signal DI1_switch is low, transistor Q27 is turned on, and when the MCU control logic signal AI1_switch is low, MOSFET Q3 is not turned on. When input AI1 is open-circuited or high-level, pin 1 of voltage follower U2A outputs high-level; when input AI1 is short-circuited or low-level, pin 1 of voltage follower U2A outputs low-level. The voltage output from pin 1 of voltage follower U2A is divided by resistors R12 and R9 and then input to the MCU's AD pin. The MCU converts the voltage into a high or low level through AD acquisition and calculation.
[0040] When the input is a simulated 0-10VDC voltage, the MCU control logic signal DI1_switch is high, and transistor Q27 is not turned on. When the MCU control logic signal AI1_switch is low, the field-effect transistor Q3 is not turned on. The input voltage is input to pin 3 of voltage follower U2A through resistors R1 and R2. The voltage is output from pin 1 of voltage follower U2A, and after being divided by resistors R12 and R9, it is input to the MCU's AD pin. The MCU converts the voltage into a voltage value through AD acquisition and calculation.
[0041] It should be noted that the control processes involved in the MCU described above are not within the protection scope of this utility model. The algorithms and programs involved in the MCU control process are all existing technologies and are only used by those skilled in the art to understand the overall circuit application.
[0042] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the disclosed methods and techniques, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Therefore, all equivalent changes made based on the shape, structure, and principle of this utility model without departing from its technical solution should be covered within the protection scope of this utility model.
Claims
1. A data acquisition circuit supporting mixed inputs, characterized in that, This includes transistor Q27, field-effect transistor Q3, and voltage follower U2A; The base of the transistor Q27 is connected to the logic signal DI1_switch, the collector of the transistor Q27 is electrically connected to one end of the resistor R139, and the other end of the resistor R139 is electrically connected to the input terminal AI1. The input terminal AI1 is electrically connected to the drain of the field-effect transistor Q3 through parallel resistors R7 and R8, and the gate of the field-effect transistor Q3 is connected to the logic signal AI1_switch; The input terminal AI1 is electrically connected to pin 3 of the voltage follower U2A through resistors R1 and R2 connected in series. Pin 1 of the voltage follower U2A is grounded through resistors R12 and R9 connected in series. The connection point between resistors R12 and R9 serves as the output terminal AIN1.
2. The data acquisition circuit supporting mixed input as described in claim 1, characterized in that, The base and emitter of the transistor Q27 are electrically connected by resistor R114, and the emitter of the transistor Q27 is connected to a voltage of 3.3V.
3. The data acquisition circuit supporting mixed input as described in claim 1, characterized in that, The gate (G) and source (S) terminals of the field-effect transistor Q3 are electrically connected by a resistor R83, and the source terminal of the field-effect transistor Q3 is grounded.
4. A data acquisition circuit supporting mixed input as described in claim 1, characterized in that, The input terminal AI1 is grounded through capacitor RC1.
5. A data acquisition circuit supporting mixed input as described in claim 1, characterized in that, The connection point between resistor R1 and resistor R2 is grounded through capacitor C2.
6. A data acquisition circuit supporting mixed input as described in claim 1, characterized in that, A capacitor C5 and a resistor R15 are connected in parallel between pin 1 and pin 2 of the voltage follower U2A.
7. A data acquisition circuit supporting mixed input as described in claim 1, characterized in that, It also includes a Schottky diode Q1, with pin 3 of the Schottky diode Q1 connected to the line between resistor R12 and resistor R9, pin 1 of the Schottky diode Q1 grounded, and pin 2 of the Schottky diode Q1 connected to a 3.3V voltage.