Packaging structure

Abstract

The packaging structure includes a packaging element, a thermal interface material layer, a ring structure, and a heat dissipation element. The packaging element is located above a substrate. The packaging element includes a first element wafer, a second element wafer, and a packaging compound laterally surrounding the first and second element wafers. The thermal interface material layer is located above the packaging element. The ring structure is located above the substrate and surrounds the packaging element. The heat dissipation element is located above the ring structure and the thermal interface material layer. The heat dissipation element includes a cover portion, multiple heat dissipation fins, a first protrusion, and a second protrusion. The multiple heat dissipation fins extend upward from the top surface of the cover portion. The first and second protrusions extend downward from the bottom surface of the cover portion. The projected area of ​​the first protrusion on the substrate overlaps with the projected area of ​​the first element wafer on the substrate. The projected area of ​​the second protrusion on the substrate overlaps with the projected area of ​​the second element wafer on the substrate.

Description

Technical Field

[0001] This disclosure relates to a packaging structure. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to the production of generation after generation of ICs, each generation being smaller and more complex than the last. However, these advancements have also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are necessary to realize these advancements.

[0003] In the evolution of integrated circuits, functional density (i.e., the number of interconnect components per wafer region) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also results in relatively high power dissipation values, which can be addressed by using low-power dissipation components such as complementary metal-oxide-semiconductor (CMOS) devices. Utility Model Content

[0004] In some embodiments, the package structure includes a package element, a thermal interface material layer, a ring structure, and a heat dissipation element. The package element is located above a substrate. The package element includes a first element wafer, a second element wafer, and a package compound laterally surrounding the first element wafer and the second element wafer. The thermal interface material layer is located above the package element. The ring structure is located above the substrate and surrounds the package element. The heat dissipation element is located above the ring structure and the thermal interface material layer. The heat dissipation element includes a cover portion, a plurality of heat dissipation fins, a first protrusion, and a second protrusion. The plurality of heat dissipation fins extend upward from the top surface of the cover portion. The first and second protrusions extend downward from the bottom surface of the cover portion. The projected area of ​​the first protrusion on the substrate overlaps with the projected area of ​​the first element wafer on the substrate. The projected area of ​​the second protrusion on the substrate overlaps with the projected area of ​​the second element wafer on the substrate.

[0005] In some embodiments, the encapsulation structure includes a substrate, an encapsulation structure, an annular structure, a thermal interface material layer, and a heat dissipation structure. The encapsulation structure is located on the substrate. The annular structure is attached to the substrate and surrounds the encapsulation structure. The thermal interface material layer is attached to the encapsulation structure. The heat dissipation structure is attached to the thermal interface material layer and the annular structure, wherein the heat dissipation structure includes a cover portion and a plurality of heat dissipation fins extending upward from a top surface of the cover portion.

[0006] In some embodiments, the packaging structure includes an interposer, a packaging structure, a first metallization layer, a thermal interface material layer, a second metallization layer, and a heat dissipation structure. The packaging structure is located on the interposer. The first metallization layer is located on the packaging structure. The thermal interface material layer is located on the first metallization layer. The second metallization layer is located on the thermal interface material layer. The heat dissipation structure is located on the second metallization layer. Attached Figure Description

[0007] When viewed in conjunction with the accompanying drawings, the best understanding of the nature of this disclosure is found in the following detailed illustrations. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 7D A schematic diagram illustrating intermediate stages in the formation of the packaging structure according to some embodiments of this disclosure is provided.

[0009] Figures 7E to 7L A schematic diagram illustrating the packaging structure according to some embodiments of this disclosure is provided.

[0010] [Symbol Explanation]

[0011] 10, 210, 410, 510, 610, 710: Package structure

[0012] 20, 34, 46, 46A, 46B, 80: Packaged components

[0013] 22: Packaging substrate

[0014] 24, 26, 28, 38: Dielectric layers

[0015] 30: Redistribution line

[0016] 36: Substrate

[0017] 40: Through-Silicon Vias

[0018] 47: Surface Mount Components

[0019] 48: Conformal coating

[0020] 50, 42: Solder area

[0021] 52: Encapsulated Compounds

[0022] 54, 44: Bottom packing

[0023] 60: Memory chip

[0024] 62: Packaging materials

[0025] 63: Conductive terminal

[0026] 66, 68: Adhesive layer

[0027] 67: Ring structure

[0028] 69: Thermal interface material layer

[0029] 69a, 69b: Intermetallic compound layers

[0030] 70, 270, 370, 470, 570, 670, 770: Heat dissipation components

[0031] 70c: Covered portion

[0032] 70f: Fin section

[0033] 70p, 270p1, 270p2, 370p1, 370p2, 570p1, 570p2, 770p1, 770p2:

[0034] Highlights

[0035] 70s: Stepped structure

[0036] 270t1, 270t2, 370t1, 370t2, 570t1, 570t2, 770t1,

[0037] 670r, 770r: Depressed portion

[0038] 770t2: Groove

[0039] A-A', B-B': Reference cross-sections

[0040] BSM1, BSM2: Conductive layers

[0041] C0, C1, C2: Outline

[0042] H0: Vertical dimension

[0043] H1, H2, H3, H4, H5, H6: Depth

[0044] L1: Area

[0045] O: Opening

[0046] PKG: Packaging Structure

[0047] S1, S2, S3, S4: Surface

[0048] T1: Thickness

[0049] W1, W2: Width Detailed Implementation

[0050] The following disclosure provides numerous different implementations or examples for implementing various features of the provided object. Specific examples of components and configurations are illustrated below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following illustrations, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define the relationships between the various implementations and / or configurations discussed.

[0051] Additionally, for ease of illustration, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, are used herein to illustrate the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Elements may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative illustration terms used herein may be interpreted accordingly. As used herein, “approximately,” “probably,” “around,” or “substantially” can mean within 20%, 10%, or 5% of a given value or range. However, those skilled in the art will understand that the values ​​or ranges listed throughout the illustrations are merely examples and may decrease as integrated circuits shrink. The numerical values ​​disclosed herein are approximate, and unless explicitly stated otherwise, terms such as “approximately,” “probably,” “around,” or “substantially” can be inferred.

[0052] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning, unless expressly defined herein.

[0053] According to some embodiments disclosed herein, it is applicable to in-memory computing, memory processing, memory-based processing, near-memory computing, near-data processing, near-memory processing, storage processing, GPU accelerators, TPU accelerators, in-memory computing, memory processing, near-memory computing and / or near-memory processing.

[0054] Thermal management of chip-on-wafer (CoW) systems typically involves a series of thermal interfaces, which introduces considerable thermal resistance and hinders effective heat dissipation from the package. Furthermore, using a cap-based structure in a CoW system may require multiple layers of thermal interface materials, thus increasing manufacturing costs.

[0055] Therefore, the various embodiments disclosed herein provide a method to reduce the number of thermal interfaces by simultaneously using backside metallization (BSM) on the wafer and the heat dissipation element, and employing a ring structure instead of a cap, thereby reducing thermal resistance and improving thermal performance. Furthermore, using a metal thermal interface material (metal TIM) directly bonded to the heat dissipation element avoids the problem of remelting during reflow, which could affect the coverage and performance of the thermal interface material.

[0056] See Figures 1 to 7D . Figures 1 to 7D This illustration shows intermediate stages in the formation of the package structure 10 according to some embodiments of this disclosure. Specifically, Figure 2A A top view of the packaging structure 10 according to some embodiments of the present disclosure is shown. Figure 1 , Figure 2B , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A This describes some embodiments according to the present disclosure, from Figure 2A The cross-sectional view of the package structure 10 obtained from the reference cross section A-A' is shown. Figure 2C and Figure 7B This describes some embodiments according to the present disclosure, from Figure 2A The cross-sectional view of the package structure 10 obtained from the reference cross-section B-B' is shown. Figure 7C A top view of a heat dissipation element 70 and annular structure 67 according to some embodiments of the present disclosure is shown. Figure 7D This describes some embodiments based on the present disclosure. Figure 7A A magnified view of a portion of region L1 in the middle. It should be understood that... Figures 1 to 7D Other operations may be performed before, during, and after the process shown, and some of the operations described below may be replaced or omitted to implement other embodiments of the method. The order of operations / processes may be interchangeable.

[0057] See Figures 1 to 2C .exist Figure 1The package component 20 may be provided. The package component 20 may include multiple package components. According to some embodiments, the package component 20 may be a package substrate strip containing multiple package substrates 22. The package substrate 22 may be a cored package substrate including a core, or a coreless package substrate not containing a core. According to alternative embodiments, the package component 20 may be another type, such as an interposer wafer, a printed circuit board, a reconstructed wafer, etc. The package component 20 may or may not contain active components, such as transistors and diodes. The package component 20 may or may not contain passive components, such as capacitors, inductors, resistors, etc.

[0058] According to some embodiments of this disclosure, the encapsulation element 20 includes multiple dielectric layers, which may include dielectric layer 24, dielectric layer 26 covering dielectric layer 24, and dielectric layer 28 located beneath dielectric layer 24. According to some embodiments, dielectric layers 26 and 28 may be formed from dry films, such as Ajinomoto build-up film (ABF). Alternatively, dielectric layers 26 and 28 may be made of or contain polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which can be coated in a flowable form and then cured. When dielectric layer 24 serves as the core layer, it may be formed from epoxy resin, glass fiber, prepreg (containing epoxy resin, glass fiber), glass, molding compound, plastic, combinations thereof, and / or multilayer materials. According to alternative embodiments, dielectric layer 24 may be formed from polymers, such as polybenzoxazole, polyimide, benzocyclobutene, etc. Redistribution lines 30, including metal lines / pads and vias, are formed in dielectric layer 24. The redistribution lines 30 can be interconnected to form connections within the package element 20. According to some embodiments, when the package element 20 is not rigid enough to support itself and structures above it, a first carrier (not shown) can be provided to support the package element 20. According to alternative embodiments, the package element 20 is thick and rigid (e.g., when it is a reconstructed wafer) to support structures formed thereon. Therefore, a first carrier may not be necessary. When used, the first carrier can be a glass carrier, an organic carrier, etc. According to alternative embodiments, the package element 20 can be pre-formed. According to alternative embodiments, the package element 20 can be built layer by layer onto the first carrier.

[0059] See further Figure 1 A package structure PKG can be placed on package element 20. Although one package structure PKG is illustrated, multiple package structure PKGs can be placed in this process, each package structure PKG placed on a corresponding package substrate 22. According to some embodiments, the package structure PKG can be interchangeably referred to as a package element or a package. The package structure PKG contains a component die therein and may contain other package elements, such as interposers, packages, die stacks, etc. According to some embodiments, the package structure PKG may include package element 34, package element 46A, and package element 46B. According to some embodiments, package element 34 may be an interposer, containing a substrate 36 and a corresponding dielectric layer 38. Therefore, package element 34 may also be referred to as an interposer, and package element 34 may also be of other types. The structure of package element 34 is schematic and details of the multilayer dielectric layers, metal lines and vias, metal pads, etc., on the top and bottom surfaces are not shown. A through-silicon via 40 can penetrate the substrate 36. The through-silicon via 40 can be used to interconnect the conductive features of the top and bottom surfaces of the substrate 36. Solder region 42 may be located below and connected to the interposer layer for connecting package element 34 to package element 20. Other bonding methods, such as metal-to-metal direct bonding, hybrid bonding, etc., may also be used to bond package element 34 to package element 20.

[0060] According to some embodiments, package element 46A and package element 46B are coupled to a corresponding lower package element 34. Figure 1 The diagram illustrates the cross-section of one package element 46A and two package elements 46B, which are bonded to the same package element 34. Another cross-section of the package structure PKG is shown below. Figure 2CThe diagram shows two packaged elements 46A bonded to the same packaged element 34 (e.g., an interposer). Packaged elements 46A and 46B can be different types of packaged elements, collectively referred to as packaged elements 46. Each packaged element 46 can be a component chip, a package containing component chips, a system-on-a-chip (SoC) chip containing multiple integrated circuits (or component chips), etc. The component chips in packaged element 46 can be or may include logic chips, memory chips, input / output chips, integrated passive devices (IPDs), etc., or combinations thereof. For example, the logic component chips in packaged element 46 can be central processing unit (CPU) chips, graphics processing unit (GPU) chips, mobile application chips, microcontroller units (MCUs), baseband (BB) chips, application processors (APs), etc. The memory chip in package element 46 may include a static random access memory (SRAM) chip, a dynamic random access memory (DRAM) chip, etc. The component chip in package element 46 may include a semiconductor substrate and an interconnect structure.

[0061] In the following discussion, according to some exemplary embodiments, package element 46A may be referred to as a component wafer, and according to some embodiments, these wafers may be system-on-a-chip (SoC). Package element 46B may be a memory stack, such as a high-performance memory (HBM) stack. Package element 46B may include a memory wafer 60 forming the wafer stack, and a packaging material 62 (e.g., molding compound) encapsulating therein. (See top view) Figure 2A The encapsulation material 62 can form a ring surrounding the memory chip 60, and can also extend into the gaps between the memory chips 60.

[0062] See further Figure 1Package element 46 can be bonded to lower package element 34 via solder region 50. Underfill 54 can be distributed between package element 46 and lower package element 34. According to some embodiments, the material of underfill 54 can be an insulating material, including resin (e.g., epoxy resin), filler material, stress release agent (SRA), adhesion promoter, other materials, or combinations thereof. According to some embodiments, underfill layer UF1 is optional. According to some embodiments, the package structure PKG can be formed via a wafer bonding process, wherein discrete wafer / package 46 is bonded to package element 34 on an uncut wafer to form a reconstructed wafer.

[0063] After dispensing the underfill 54, an encapsulation material, such as a molding compound 52, can be applied, and then the molding compound 52 is planarized so that its top surface is flush with the top surface of the encapsulation element 46. According to some embodiments, the molding compound 52 can be an encapsulation material, a molding underfill, a resin (e.g., epoxy resin, phenolic resin), etc. According to some alternative embodiments, the material of the molding compound 52 can include silicon oxide (SiOx, x>0), silicon oxynitride (SiOxNy, x>0 and y>0), silicon nitride (SiNx, x>0), or other suitable dielectric materials. According to some embodiments, the molding compound 52 includes a filler. The filler can be particles made of silicon dioxide, aluminum oxide, etc. According to some embodiments, the molding compound 52 is formed by a molding process, an injection process, a thin film deposition process, or a combination thereof. Molding processes include, for example, transfer molding processes, compression molding processes, etc. Thin film deposition processes include, for example, CVD, HDPCVD, PECVD, ALD, or a combination thereof.

[0064] See further Figure 1A conductive layer BSM1 can be formed on package elements 46A and 46B and package compound 52 to form a reconstructed wafer. The conductive layer BSM1 can be in physical contact with the top surface of package element 46A, the top surface of package element 46B, the top surface of package compound 52, and the top surface of bottom filler 54. According to some embodiments, the conductive layer BSM1 may include multiple metal layers, including an adhesion layer to ensure strong bonding, a diffusion barrier layer to prevent unwanted material migration, and an anti-oxidation layer (e.g., gold) to protect against environmental damage. Specifically, the adhesion layer can be deposited on package elements 46A and 46B and package compound 52 to ensure that subsequent layers (such as the diffusion barrier layer) adhere well to package elements 46A and 46B and package compound 52. The adhesion layer can be deposited using methods such as sputtering or chemical vapor deposition (CVD). Subsequently, a diffusion barrier layer can be deposited on the adhesion layer. An adhesion layer can anchor the diffusion barrier layer to package elements 46A and 46B and the encapsulation compound 52, while protecting package elements 46A and 46B, the encapsulation compound 52, and subsequent layers from material mixing. The adhesion layer can be deposited using methods such as sputtering or chemical vapor deposition (CVD). Subsequently, conductive and other functional layers can be deposited on the diffusion barrier layer. According to some embodiments, the adhesion layer may include titanium (Ti), aluminum (Al), chromium (Cr), other suitable materials, or any combination thereof. According to some embodiments, the diffusion barrier layer may include nickel (Ni), nickel vanadium (NiV), other suitable materials, or any combination thereof. According to some embodiments, the oxidation-resistant layer may include conductive copper or a noble metal (e.g., gold) that prevents oxidation and corrosion.

[0065] However, this disclosure is not limited thereto. According to some embodiments, the material of the conductive layer BSM1 may include metals such as aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), tantalum (Ta), silver (Ag), and gold (Au). The thickness of the conductive layer BSM1 can be approximately... to Within a range, such as approximately 10, 100, 1000 or To provide application flexibility. According to some embodiments, the conductive layer BSM1 can be formed by sputtering, electroplating, deposition, or deposition processes. It should be noted that the conductive layer BSM1 can be used to promote adhesion between the subsequently formed thermal interface material (TIM) layer (e.g., thermal interface material layer 69) and the package structure PKG, and can be interchangeably referred to as back metallization or back metal layer.

[0066] The reconstructed wafer can be sawn to form discrete package structures PKG, which can be bonded to package element 20. Package compound 52 and package element 34 are subjected to a dicing process to obtain... Figure 1 The packaging structure PKG is shown in the diagram. Although... Figure 1 The diagram shows only one package structure PKG for illustrative purposes; however, those skilled in the art will understand that multiple package structure PKGs can be obtained after the dicing process. The final structure of the package structure PKG is shown below. Figures 2A to 2C As shown. According to some embodiments, the dicing process typically involves dicing using a rotating blade and / or a laser beam. In other words, the dicing process includes laser dicing, mechanical dicing, laser grooving, other suitable processes, or combinations thereof. According to some embodiments, since the packaged element 34 is in wafer form, the package structure PKG is considered to be formed by a wafer-on-wafer process, and the package structure PKG is also referred to as a wafer-on-wafer package.

[0067] After placing the package structure PKG onto the package element 20, reflow of the solder area 42 can be performed, and the underfill 44 (see...) can be applied. Figure 2B and Figure 2C The filler 44 is distributed into the gap between the package structure PKG and the package element 20. According to some embodiments, the material of the bottom filler 44 is an insulating material comprising resin (e.g., epoxy resin), filler material, stress-relieving agent, adhesion promoter, other materials, or combinations thereof. According to some embodiments, the bottom filler 44 may be optional. Other package elements may also be present, such as surface mount devices (SMDs) 47, which are bonded to the package element 20. According to some embodiments, the surface mount device 47 may be a discrete capacitor, discrete inductor, discrete resistor, etc. According to some embodiments, no active elements, such as transistors, are formed in the surface mount device 47; the surface mount device 47 may be interchangeably referred to as an Independent Passive Device (IPD). Figure 2AAs shown, the package structure PKG may include one or more component wafers 46A and multiple memory stacks 46B. Each memory stack 46B may include stacked memory wafers 60 and encapsulating (and surrounding) the memory wafers 60 with packaging material 62. The packaging material (e.g., encapsulating material) 52 may fill the gaps between adjacent packaged components 46. Surface mount elements 47 may be bonded to the peripheral area of ​​the package substrate 22. Furthermore, a conformal coating 48 may be applied to the surface mount elements 47 to prevent potential damage caused by indium migration. The conformal coating 48 may be made of polymer-based materials such as acrylic or epoxy resin.

[0068] See Figure 3 An adhesive layer 66 may be formed on the surface S1 of the package element 20. For example, the adhesive layer 66 may be formed near the edge of the surface S1 of the package element 20 to surround / encapsulate the package structure PKG, the bottom filler 44, and the surface mount element 47. According to some embodiments, the adhesive layer 66 partially covers the surface S1 of the package element 20. For example, the package structure PKG, the bottom filler 44, and the surface mount element 47 are physically isolated from the adhesive layer 66. According to some embodiments, the adhesive layer 66 has an annular shape in a plan view. According to some embodiments, the pattern of the adhesive layer 66 may be designed according to different designs. For example, the adhesive layer 66 may have a linear shape, an L-shape, a U-shape, a dot shape, etc. According to some embodiments, the shape of the adhesive layer 66 may depend on the shape of the package element 20. For example, when the package element 20 is in wafer form (i.e., has a circular top view), the adhesive layer 66 may appear as a circular annular shape in the top view. When the package element 20 is in panel form (i.e., has a rectangular or square top view), the adhesive layer 66 may appear as a rectangular or square annular shape in the top view. According to some embodiments, the adhesive layer 66 can be applied to the encapsulation element 20 via a dispensing process, spin coating process, etc. According to some embodiments, the thermal conductivity of the adhesive layer 66 is greater than about 0 W / m·K to 5 W / m·K. According to some embodiments, the adhesive layer 66 may comprise an epoxy resin-based material. However, this disclosure is not limited thereto. According to some alternative embodiments, other polymeric materials with adhesive properties can be used as the adhesive layer 66.

[0069] See Figure 4A ring structure 67 is attached to the package element 20. According to some embodiments, the ring structure 67 can be made of robust materials such as stainless steel, copper (Cu), or Alloy 42, providing structural integrity and facilitating thermal management. According to some embodiments, the ring structure 67 can be made of metal. According to some embodiments, the Young's modulus of the ring structure 67 can range from about 50 GPa to about 200 GPa. According to some embodiments, the ring structure 67 can surround the package structure PKG and the surface mount device 47. Figure 4 As shown, the annular structure 67 can be spatially separated from the package structure PKG, the bottom filler 44, and the surface mount element 47. According to some embodiments, the top surface of the annular structure 67 can be located above the top surface of the conductive layer BSM1.

[0070] Specifically, the annular structure 67 can be attached to the encapsulation element 20 via the adhesive layer 66. For example, the annular structure 67 can first be placed on the encapsulation element 20 to make physical contact with the adhesive layer 66. Subsequently, the annular structure 67 can be pressed onto the adhesive layer 66. According to some embodiments, pressing the annular structure 67 onto the adhesive layer 66 may include a thermal clamping process, wherein the temperature range of the thermal clamping process is approximately 60°C to approximately 300°C. Subsequently, a curing process is performed on the adhesive layer 66 so that the annular structure 67 can be attached to the encapsulation element 20 via the adhesive layer 66. Specifically, a curing process is performed on the adhesive layer 66 to securely fix the annular structure 67 to the encapsulation element 20. According to some embodiments, the temperature range of the curing process is approximately 60°C to approximately 300°C.

[0071] See Figure 5 Multiple conductive terminals 63 can be formed on the surface S2 of the package element 20. According to some embodiments, the conductive terminals 63 are solder balls, ball grid array (BGA) balls, etc. According to some embodiments, the conductive terminals 63 are made of a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof. According to some embodiments, the conductive terminals 63 can be in physical contact with the exposed redistribution lines 30 (or wiring patterns) on the surface S2 of the package element 20. According to some embodiments, the conductive terminals 63 can be used for physical and electrical connections between the package element 20 and other devices, packages, connection components, etc. In other words, the conductive terminals 63 can be used to provide physical and / or electrical connections to external components. Figure 5As shown, conductive terminals 63 and the package structure PKG are located on two opposite sides of the package element 20, with some of the conductive terminals 63 electrically connected to the package structure PKG via redistribution lines 30 and solder areas 42. According to some embodiments, the conductive terminals 63 can be formed on the surface S2 of the package element 20 through a ball-placement process and a reflow process. According to some embodiments, a reflow process can be performed to reshape the conductive terminals 63, thereby achieving a good physical and metallurgical bond between the conductive terminals 63 and the package element 20.

[0072] See Figure 6 A package element 80 may be provided. According to some embodiments, the package element 80 may be a printed circuit board (PCB), etc. According to some embodiments, the package element 80 may be referred to as a circuit substrate. According to some embodiments, the package element 80 may contain a plurality of wiring patterns embedded therein. According to some embodiments, these wiring patterns may be interconnected. In other words, these wiring patterns may be electrically interconnected. Figure 5 The illustrated package structure can be bonded to package element 80. According to some embodiments, Figure 5 The illustrated package structure can be attached to the package element 80 via conductive terminal 63. For example, Figure 5 The conductive terminals 63 of the illustrated package structure can physically contact the wiring pattern exposed on the surface of the package element 80 to achieve... Figure 5 The electrical connection between the package structure and the package element 80 is shown.

[0073] Subsequently, an adhesive layer 68 can be placed on the top surface of the annular structure 67 to surround / encapsulate the encapsulation structure PKG, the bottom filler 44, and the surface mount element 47. According to some embodiments, the adhesive layer 68 has an annular shape in a plan view. According to some embodiments, the pattern of the adhesive layer 68 can be designed according to different designs. For example, the adhesive layer 68 can have a linear shape, an L-shape, a U-shape, a dotted shape, etc. According to some embodiments, the shape of the adhesive layer 68 can depend on the shape of the encapsulation element 20. For example, when the encapsulation element 20 can be in wafer form (i.e., having a circular top view), the adhesive layer 68 can present a circular annular shape in the top view. For example, when the encapsulation element 20 can be in panel form (i.e., having a rectangular or square top view), the adhesive layer 68 can present a rectangular or square annular shape in the top view. According to some embodiments, the adhesive layer 68 can be applied to the annular structure 67 through a dispensing process, a spin coating process, etc. According to some embodiments, the thermal conductivity of the adhesive layer 68 is less than about 0.5 W / m·K. According to some embodiments, the adhesive layer 68 can contain an epoxy resin-based material. However, this disclosure is not limited thereto. According to some alternative embodiments, other polymeric materials with adhesive properties can be used as the adhesive layer 68.

[0074] See Figures 7A to 7D A thermal interface material layer (TIM layer) 69 may be formed on the conductive layer BSM1. According to some embodiments, the TIM layer 69 may be of a sheet-like type. According to some embodiments, the TIM layer 69 may be formed on the conductive layer BSM1 through a pick-and-place process. According to some embodiments, the material of the TIM layer 69 may be a solderable material. According to some embodiments, the TIM layer 69 may be formed of a pure metallic material and may be interchangeably referred to as a metallic thermal interface material. According to some embodiments, the TIM layer 69 may be free of organic and polymeric materials. According to some embodiments, the material of the TIM layer 69 includes metallic materials such as indium, copper, tin, indium-silver alloys, or combinations thereof. According to some embodiments, the thermal conductivity of the TIM layer 69 ranges from approximately 10 W / (m·K) to approximately 90 W / (m·K). According to some embodiments, the Young's modulus of the TIM layer 69 ranges from approximately 5 GPa to approximately 70 GPa. According to some embodiments, the top surface height of the TIM layer 69 may be lower than the top surface height of the annular structure 67. However, this disclosure is not limited thereto. According to some alternative embodiments, the top surface height of the thermal interface material layer 69 may be higher than the top surface height of the annular structure 67.

[0075] According to some embodiments, the thermal interface material layer 69 may overlap with package elements 46A and 46B. For example, the vertical projection of the thermal interface material layer 69 onto the package element 20 may completely overlap with the vertical projections of package elements 46A and 46B onto the package element 20. However, this disclosure is not limited thereto. According to some alternative embodiments, the vertical projection of the thermal interface material layer 69 onto the package element 20 may partially overlap with the vertical projections of package elements 46A and 46B onto the package element 20. From another perspective, the thermal interface material layer 69 may be formed at least at the locations of package elements 46A and 46B (see [reference needed]). Figure 7E , Figure 7F , Figure 7J and Figure 7L ).

[0076] According to some embodiments, for better adhesion, flux (not shown) can be placed between the conductive layer BSM1 and the thermal interface material layer 69, and another flux (not shown) can be applied to the top surface of the thermal interface material layer 69. For example, flux (not shown) can be formed on the conductive layer BSM1 before the thermal interface material layer 69 is placed on the conductive layer BSM1; and another flux (not shown) can be formed on the top surface of the thermal interface material layer 69 after the thermal interface material layer 69 is placed on the conductive layer BSM1. According to some embodiments, flux formation includes performing a spraying or dispensing process. According to some embodiments, the flux material includes rosin or acids.

[0077] See you again Figures 7A to 7D A heat sink 70 can be placed on the annular structure 67, the encapsulation element 20, the encapsulation structure PKG, and the surface mount element 47, such that the encapsulation structure PKG and the thermal interface material layer 69 can be located between the encapsulation element 20 and the heat sink 70. In some embodiments, the heat sink 70 may also be referred to as a heat dissipation structure. The heat sink 70 serves to dissipate heat. In other words, the heat generated during the operation of the encapsulation structure PKG can be dissipated through the channels created by the heat sink 70. The heat sink 70, the annular structure 67, and the encapsulation element 20 together surround the encapsulation structure PKG and the surface mount element 47. In other words, the heat sink 70 and the annular structure 67 can be formed to accommodate the encapsulation structure PKG and / or the surface mount element 47. For example, the cover portion 70c of the heat sink 70 and the annular structure 67 can present an inverted U-shape in a cross-sectional view, such as... Figure 7A and Figure 7BAs shown. According to some embodiments, the heat dissipation element 70 can be made of metal, plastic, ceramic, etc. The metal of the heat dissipation element 70 may include, but is not limited to, copper, stainless steel, solder, gold, nickel, molybdenum, nickel-iron, or nickel-iron-chromium. According to some embodiments, the thermal conductivity of the heat dissipation element 70 ranges from about 80 W / (m·K) to about 450 W / (m·K). According to some embodiments, the Young's modulus of the heat dissipation element 70 ranges from about 50 GPa to about 200 GPa.

[0078] According to some embodiments, the heat dissipation element 70 may include a cover portion 70c, a protruding portion 70p, and a fin portion 70f. The cover portion 70c may extend along the X and Y directions and may be of a sheet-like type. The fin portion 70f may protrude upward from the surface S3 of the cover portion 70c. The protruding portion 70p protrudes from the surface S4 (or back side) of the cover portion 70c, opposite to the surface S3. According to some embodiments, the protruding portion 70p may be thicker than the adhesion layer 68. By way of example only and not limitation, the thickness T1 of the protruding portion 70p may range from approximately 50 to 100 μm, such as 50, 60, 70, 80, 90, or 100 μm. In other words, the protruding portion 70p with the cover portion 70c may form a stepped structure 70s on the back side of the heat dissipation element 70, located above the wafer region on the wafer. This stepped structure 70s may be customized according to the height of the annular structure 67 to ensure a suitable and optimized thermal interface. However, not all implementations have this stepped structure, allowing for flexibility in application. According to some implementations, the cover portion 70c can be interchangeably referred to as the bulk portion, and the fin portion can be interchangeably referred to as the heat dissipation fins.

[0079] According to some embodiments, the cover portion 70c and the protruding portion 70p can be integrally formed. For example, the material of the protruding portion 70p can be the same as the material of the cover portion 70c. However, this disclosure is not limited thereto. According to some alternative embodiments, the protruding portion 70p can be mounted on the cover portion 70a. For example, the material of the protruding portion 70p can be different from the material of the cover portion 70c. According to some embodiments, the cover portion 70c and the fin portion 70f can be integrally formed. For example, the material of the fin portion 70f can be the same as the material of the cover portion 70c. However, this disclosure is not limited thereto. According to some alternative embodiments, the fin portion 70f can be mounted on the cover portion 70c. For example, the material of the fin portion 70f can be different from the material of the cover portion 70c.

[0080] The heat dissipation element 70 can be securely attached to the annular structure 67 by attaching the cover portion 70c to the adhesive layer 68, such that the protrusion 70p can extend into the opening O of the annular structure 67. According to some embodiments, the contour C0 of the protrusion 70p (see...) Figure 7C It can roughly correspond to the outline of the opening O of the annular structure 67 (see...). Figure 7C Correspondingly, the thermal interface material layer 69 can be sandwiched between the protruding portion 70p of the heat dissipation element 70 and the package structure PKG.

[0081] According to some embodiments, a conductive layer BSM2 may be formed on the protruding portion 70p of the heat dissipation element 70 before the additional cover structure 70. Specifically, as Figure 7A and Figure 7B As shown, the conductive layer BSM2 and the protrusion 70p are located in the opening O of the annular structure 67. It should be noted that the conductive layer BSM2 can be used to promote adhesion between the thermal interface material layer 69 and the heat dissipation element 70, and can be referred to as a back metallization layer or a back metal layer. According to some embodiments, the material of the conductive layer BSM2 can be the same as the material of the conductive layer BSM1. According to some alternative embodiments, the material of the conductive layer BSM2 can be different from the material of the conductive layer BSM1. According to some embodiments, the conductive layer BSM2 can be formed on the heat dissipation element 70 by electroplating, sputtering, or dispensing processes. According to some embodiments, the material of the conductive layer BSM2 can include metals such as aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), gold (Au), silver (Ag), or copper (Cu). According to some embodiments, the conductive layer BSM2 can be integrated as a gold-plated heat dissipation element. That is, the back side of the heat dissipation element 70 can be plated with gold (Au) to improve thermal conductivity and prevent oxidation, while its main components may include materials such as copper (Cu) or aluminum (Al). The heat dissipation element is bonded to both the CoW and the annular structure 67 using an adhesive to ensure a secure assembly and thermal efficiency.

[0082] Specifically, after forming the conductive layer BSM2 on the heat dissipation element 70, the heat dissipation element 70 and the conductive layer BSM2 can be placed above the thermal interface material layer 69 and the adhesive layer 68, such that the conductive layer BSM2 can contact the top surface of the thermal interface material layer 69, and the covering portion 70a of the heat dissipation element 70 can contact the adhesive layer 68. Subsequently, the heat dissipation element 70 and the conductive layer BSM2 are pressed onto the thermal interface material layer 69. However, this disclosure is not limited thereto. According to some alternative embodiments, the conductive layer BSM2 is not formed on the heat dissipation element 70.

[0083] According to some embodiments, pressing the heat dissipation element 70 and the conductive layer BSM2 onto the thermal interface material layer 69 and the adhesive layer 68 may include performing a heated clamping process, wherein the process temperature of the heated clamping process ranges from approximately 60°C to approximately 300°C. Subsequently, a curing process can be performed on the adhesive layer 68 so that the heat dissipation element 70 can be attached to the encapsulation element 20 through the adhesive layer 68. Specifically, the curing process can be performed on the adhesive layer 68 to securely fix the heat dissipation element 70 to the encapsulation element 20. According to some embodiments, the process temperature of the curing process ranges from approximately 60°C to approximately 300°C. However, this disclosure is not limited thereto. According to some embodiments, during the curing process, the covering portion 70c can be attached to the encapsulation structure PKG through the protruding portion 70p and the thermal interface material layer 69. That is, in these embodiments, during the curing process, the heat dissipation element 70 has a good physical and metallurgical bond with the encapsulation structure PKG. In these embodiments, the process temperature of the curing process ranges from approximately 160°C to approximately 260°C.

[0084] Therefore, the package disclosed herein can combine a wafer assembly (e.g., a package structure PKG) on a wafer having a conductive layer BSM1 (e.g., a back metallization layer), a thermal interface material layer 69, a ring structure 67, and a heat dissipation element 70, and also includes a conductive layer BSM2 (e.g., a back metallization layer) on its back side. This assembly can be arranged sequentially to optimize thermal management. In this configuration, there are two interfaces: a first interface between the heat dissipation element 70 and the thermal interface material layer 69, and a second interface between the thermal interface material layer 69 and the package structure PKG (e.g., a wafer on a wafer).

[0085] Backside metallization (BSM) can be applied to the back side of the heat sink 70. Combined with a ring process, this eliminates the need for lids on the wafer. This method enables direct bonding between the thermal interface material layer 69 and the heat sink 70, effectively reducing the total number of thermal interfaces. This reduction improves thermal efficiency, achieving a thermal resistance (TR) reduction of at least approximately 50%, such as approximately 50, 55, 60, 65, 70, 75, 76.8, or 80%. By way of example and not limitation, the first interface can exhibit a thermal resistance of approximately 0.8 to 1 mm²K / W, such as approximately 0.8, 0.85, 0.9, 0.95, or 1 mm²K / W. The thermal interface material layer 69 can exhibit a volumetric thermal conductivity of approximately 1 to 5 mm²K / W, such as approximately 1, 1.5, 2, 2.3, 2.5, 3, 3.5, 4, 4.5, or 5 mm²K / W. The second interface can display thermal resistances from approximately 0.8 to 1 mm²K / W, such as approximately 0.8, 0.85, 0.9, 0.95, or 1 mm²K / W.

[0086] By integrating the ring structure 67 and back-side metallization process into the package, and utilizing the thermal interface material layer 69 directly bonded to the heat dissipation element 70, heat dissipation performance can be improved. This simplifies the thermal path, resulting in an overall thermal resistance reduction from approximately 17.7 mm²K / W to approximately 4.4 mm²K / W, which translates to a thermal resistance reduction of at least approximately 50%.

[0087] According to some embodiments, at the interface in the semiconductor package, where the thermal interface material layer 69 contacts the conductive layer BSM2 and the heat dissipation element 70, a series of intermetallic compounds (IMCs) can be synthesized to form an intermetallic compound layer 69b. According to some embodiments, a series of intermetallic compounds can be synthesized to form an intermetallic compound layer 69a on the side of the thermal interface material layer 69 near the conductive layer BSM1. The formation of the intermetallic compounds can improve the performance of the package. The intermetallic compounds can include, but are not limited to, gold-indium alloys (Au-In), nickel-indium alloys (Ni-In), nickel-gold-indium alloys (Ni-Au-In), other suitable materials, or combinations thereof. Specifically, the intermetallic compounds can have a robust metallurgical bond. The intermetallic compound layer 69b can ensure high mechanical strength in terms of long-term reliability of the bond between the thermal interface material layer 69 and the conductive layer BSM2 and the heat dissipation element 70, as it can withstand various thermal cycles and mechanical stresses without degradation. Similarly, the intermetallic compound layer 69a ensures high mechanical strength for long-term reliability of the bonding between the thermal interface material layer 69, the conductive layer BSM1, and the package structure PKG, as it can withstand various thermal cycles and mechanical stresses without degradation. Furthermore, the intermetallic compound facilitates the thermal pathway from the semiconductor element to the heat dissipation element 70, promoting efficient heat dissipation.

[0088] According to some embodiments, the formation of the intermetallic compound layer 69b can occur within a thickness range T3, ranging from approximately 0.1 to 2 μm, such as approximately 0.1, 0.5, 0.8, 1, 1.5, 1.8, or 2 μm. If the thickness of the intermetallic compound layer 69b is less than approximately 0.1 μm, the formation of the intermetallic compound may not provide sufficient mechanical support or thermal conductivity. If the thickness of the intermetallic compound layer 69b is greater than approximately 2 μm, the formation of the intermetallic compound may introduce unwanted thermal resistance or impair the integrity of the bond. According to some embodiments, the formation of the intermetallic compound layer 69a can occur within a thickness range T2, ranging from approximately 0.1 to 2 μm, such as approximately 0.1, 0.5, 0.8, 1, 1.5, 1.8, or 2 μm. If the thickness of the intermetallic compound layer 69a is less than approximately 0.1 μm, the formation of the intermetallic compound may not provide sufficient mechanical support or thermal conductivity. If the thickness of the intermetallic compound layer 69a is greater than about 2 μm, the formation of the intermetallic compound may introduce unwanted thermal resistance or impair the integrity of the bond.

[0089] See Figures 7E to 7G . Figure 7E and Figure 7F A cross-sectional view of package 210 including heat dissipation element 270 according to some embodiments of this disclosure is shown, respectively corresponding to Figure 7A and Figure 7B . Figure 7G A top view of the heat dissipation element 270 and the annular structure 67 according to some embodiments of this disclosure is shown. Although Figures 7E to 7G Showing with Figures 1 to 7D The present disclosure describes different implementations of package structure 210 with different heat dissipation element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various implementations and / or configurations discussed.

[0090] According to some embodiments, voids may form around the thermal interface material layer 69 or the heat sink 70 in a semiconductor package, thereby affecting the thermal performance of the package. These voids may be air gaps formed during assembly, including during solder reflow, application of the thermal interface material, or when the package undergoes thermal cycling. In some embodiments, voids may be formed due to the venting of solvent or flux. Due to the low thermal conductivity of air, voids can act as thermal insulators, reducing the efficiency of heat dissipation from the semiconductor element to the heat sink 70. Furthermore, voids may weaken the mechanical bond between the thermal interface material layer 69 and the heat sink 70, reducing the structural integrity of the package and making it more susceptible to delamination or failure during thermal cycling.

[0091] Therefore, at least one groove can be formed on the back side of the heat dissipation element 270 (e.g., Figures 7E to 7G The grooves 270t1 and 270t2 shown are used to mitigate the effects of voids. The grooves formed on the back of the heat sink 270 can serve as storage spaces to trap venting material, flux, and air that may form voids in the interface region. By providing grooves 270t1 and 270t2 to allow voids to escape, void formation within the thermal interface material layer 69 or between the thermal interface material layer 69 and the heat sink 270 can be minimized. By reducing the presence of voids, grooves 270t1 and 270t2 can improve thermal conductivity at the interface, thereby increasing heat dissipation efficiency and extending device life. According to some embodiments, grooves 270t1 and 270t2 formed on the back of the heat sink 270 can be interchangeably referred to as spaces.

[0092] The heat dissipation element 270 may include a cover portion 70c, different protrusions 270p1 and 270p2, and a fin portion 70f. The protrusions 270p1 and 270p2 extend from surface S4 of the cover portion 70c, opposite surface S3, ensuring mechanical engagement and enhanced thermal coupling with the underlying package elements 46A and 46B. The thickness of the protrusions 270p1 and 270p2 may exceed the thickness of the adhesive layer 68. Specifically, the contours C1 and C2 of the protrusions 270p1 and 270p2 (see...) Figure 7G The package element 46A and package element 46B within the package structure PKG can be aligned with their geometry. According to some embodiments, the spatial layout of package element 46A can be adapted to fit within the boundary of protrusion 270p1, and similarly, the spatial layout of package element 46B can fit within the boundary of protrusion 270p2. According to some embodiments, the spatial layout of protrusion 270p1 can be adapted to fit within the boundary of package element 46A, and similarly, the spatial layout of protrusion 270p2 can fit within the boundary of package element 46B.

[0093] Furthermore, the placement of recesses 270t1 and 270t2 within the heat dissipation element 270 associated with protrusions 270p1 and 270p2 can target areas in the package structure PKG that are less involved in heat generation. Specifically, recess 270t1 can be positioned aligned with the package compound 52, while recess 270t2 can be positioned aligned with the bottom filler 54, embedded between package element 46A and package element 46B. According to some embodiments, recess 270t1 can have an annular footprint surrounding the package area. According to some embodiments, the width W1 of recess 270t1 (see...) Figure 7G It can be greater than the width W2 of the groove 270t2 (see...) Figure 7G ).

[0094] In the heat dissipation element 270, the collective structure formed by the cover portion 70c and the protrusions 270p1 and 270p2 can establish a vertical dimension (e.g., thickness / height) H0. In this collective structure, the two distinct recesses 270t1 and 270t2 can each have a depth H2 and a depth H1. The depth H1 can also correspond to the vertical dimensions of the protrusions 270p1 and 270p2. According to some embodiments, the vertical dimension H0 can be greater than the depth H1 of the recess 270t2, and the depth H1 of the recess 270t2 can be equal to or greater than the depth H2 of the recess 270t1. This dimensional difference ensures a suitable and optimized thermal path within the heat dissipation element 270, allowing for efficient heat dissipation.

[0095] See Figure 7H . Figure 7H A top view of a heat dissipation element 370 according to some embodiments of this disclosure is shown. Although Figure 7H Showing with Figures 7E to 7G The package 210 is described in different implementations with different thermal element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various implementations and / or configurations discussed.

[0096] like Figure 7H As shown, Figure 7H The implementation methods and Figures 7E to 7G The difference in the implementation method lies in the alteration of the arrangement and number of protrusions 370p1 and 370p2, which differs from the corresponding portions (e.g., protrusions 270p1 and 270p2) in the previous illustrations. This adjustment is to enhance the alignment of protrusions 370p1 and 370p2 with the package elements 46A and 46B located within the underlying package structure PKG, ensuring that each protrusion 370p1 and 370p2 can cover the corresponding package element 46A and package element 46B, thereby optimizing the heat conduction path and ensuring robust mechanical support, thus improving the overall performance and reliability of the semiconductor package.

[0097] Furthermore, despite these adjustments made to protrusions 370p1 and 370p2, the placement of recesses 370t1 and 370t2 remains consistent with earlier embodiments. Specifically, recess 370t1 may be positioned aligned with encapsulation compound 52, while recess 370t2 may be positioned aligned with bottom filler 54, embedded between encapsulation element 46A and encapsulation element 46B. According to some embodiments, recess 370t1 may have an annular footprint surrounding the encapsulation area.

[0098] See Figure 7I . Figure 7I A cross-sectional view of package 410 according to some embodiments of this disclosure is shown, corresponding to Figure 7A .Although Figure 7I Showing with Figures 1 to 7D The present disclosure describes different embodiments of package 410 with different thermal element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0099] like Figure 7I As shown, Figure 7I The implementation methods and Figures 1 to 7D The difference in the implementation is that, although the heat dissipation element 470 retains the cover portion 70c and the fin portion 70f, similar to the previous implementation, it eliminates the protruding portion 70p of the previous implementation. That is, the bottom surface S4 of the heat dissipation element 470 can be flat. The heat dissipation element 470 can represent a streamlined heat dissipation element architecture, focusing on the essential elements required for effective heat dissipation. The cover portion 70c can serve as an interface between the heat dissipation element 470 and the package structure PKG, facilitating heat conduction from the package structure PKG to the heat dissipation element 470.

[0100] See Figure 7J . Figure 7J A cross-sectional view of package 510 according to some embodiments of this disclosure is shown, corresponding to Figures 7E to 7G .Although Figure 7J Showing with Figures 7E to 7G The present disclosure describes different embodiments of package 510 with different thermal element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0101] like Figure 7J As shown, Figure 7J The implementation methods and Figures 7E to 7GThe difference in the implementation is that, although the heat dissipation element 570 retains the cover portion 70c and the fin portion 70f, similar to the previous implementation, it eliminates the protrusions 270p1 and 270p2 that extend beyond the back of the cover portion 70c in the previous implementation. Specifically, grooves 570t1 and 570t2 can be formed within the cover portion 70c of the heat dissipation element 570 and are targeted at areas in the package structure PKG that are less involved in heat generation. Specifically, groove 570t1 can be positioned aligned with the package compound 52, while groove 570t2 can be positioned aligned with the bottom filler 54 and embedded between package elements 46A and 46B. According to some implementations, groove 570t1 can have an annular footprint surrounding the package area. Grooves 570t1 and 570t2 can each have a depth H4 and a depth H3. According to some implementations, the depth H3 of groove 570t2 can be equal to or greater than the depth H4 of groove 570t1. According to some embodiments, the depth H3 of the groove 570t2 can be less than the depth H4 of the groove 570t1. This dimensional difference ensures a suitable and optimized thermal path within the heat dissipation element 570, allowing for efficient heat dissipation.

[0102] On the other hand, recesses 570t1 and 570t2 can define protrusions 570p1 and 570p2 extending from the back side of the cover portion 70c. Specifically, the outlines of protrusions 570p1 and 570p2 can be aligned with the geometry of package elements 46A and 46B within the package structure PKG. According to some embodiments, the spatial layout of package element 46A can be adapted within the boundary of protrusion 570p1, and similarly, the spatial layout of package element 46B can be adapted within the boundary of protrusion 570p2.

[0103] See Figure 7K . Figure 7K A cross-sectional view of package 610 according to some embodiments of this disclosure is shown, corresponding to Figures 1 to 7D .Although Figure 7K Showing with Figures 1 to 7D The present disclosure describes different embodiments of package 610 with different thermal element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0104] like Figure 7K As shown, Figure 7K The implementation methods and Figures 1 to 7DThe difference in the implementation is that, although the heat dissipation element 670 retains the cover portion 70c and the fin portion 70f, similar to the previous implementation, it eliminates the protruding portion 70p of the previous implementation and introduces a recessed portion 670r covering the package structure PKG. Specifically, after positioning the heat dissipation element 70 and the conductive layer BSM2 above the thermal interface material layer 69, the recessed portion 670r can accommodate at least a portion of the thermal interface material layer 69, ensuring that the top surface of the thermal interface material layer 69 is above the surface S4 of the cover portion 70c. The recessed portion 670r can ensure direct contact between the top surface of the thermal interface material layer 69 and the heat dissipation element 670, improving the heat transfer efficiency from the semiconductor package to the heat dissipation element 670. According to some implementations, the side surface of the thermal interface material layer 69 can contact the side surface of the recessed portion 670r in the heat dissipation element 670 to further increase thermal contact. Furthermore, embedding the thermal interface material layer 69 into the recessed portion 670r can provide additional mechanical stability to the assembly, maintaining the integrity of the thermal interface under various operating conditions, including thermal cycling and mechanical stress.

[0105] See Figure 7L . Figure 7L A cross-sectional view of package 710 according to some embodiments of this disclosure is shown, corresponding to Figures 7E to 7G .Although Figure 7L Showing with Figures 7E to 7G The present disclosure describes different embodiments of package 710 with different thermal element configurations, but reference numerals and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0106] like Figure 7L As shown, Figure 7L The implementation methods and Figures 7E to 7GThe difference in the implementation is that, although the heat dissipation element 710 retains the cover portion 70c and the fin portion 70f, similar to the previous implementation, it eliminates the protrusions 270p1 and 270p2 that extend beyond the back of the cover portion 70c in the previous implementation and introduces a recessed portion 770r covering the package structure PKG. Specifically, after positioning the heat dissipation element 70 and the conductive layer BSM2 above the thermal interface material layer 69, the recessed portion 770r can accommodate at least a portion of the thermal interface material layer 69, ensuring that the top surface of the thermal interface material layer 69 is above the surface S4 of the cover portion 70c. The recessed portion 770r can ensure direct contact between the top surface and sidewalls of the thermal interface material layer 69 and the heat dissipation element 670, improving the heat transfer efficiency from the semiconductor package to the heat dissipation element 670. In addition, embedding the thermal interface material layer 69 in the recessed portion 770r can provide additional mechanical stability to the assembly, maintaining the integrity of the thermal interface under various operating conditions, including thermal cycling and mechanical stress.

[0107] Specifically, recesses 770t1 and 770t2 can be formed within the cover portion 70c of the heat dissipation element 770, targeting areas in the package structure PKG that contribute less to heat generation. Specifically, recess 770t1 can be positioned aligned with the package compound 52, while recess 770t2 can be positioned aligned with the bottom filler 54, embedded between package elements 46A and 46B. According to some embodiments, recess 770t1 can have an annular footprint surrounding the package area. Recesses 770t1 and 770t2 can each have depths H6 and H5. According to some embodiments, the depth H5 of recess 770t2 can be equal to or greater than the depth H6 of recess 770t1. According to some embodiments, the depth H5 of recess 770t2 can be less than the depth H6 of recess 770t1. This dimensional difference ensures a suitable and optimized thermal path within the heat dissipation element 770, allowing for efficient heat dissipation.

[0108] On the other hand, recesses 770t1 and 770t2 can define protrusions 770p1 and 770p2 extending from the back side of the cover portion 70c. Specifically, the contours of protrusions 770p1 and 770p2 can be aligned with the geometry of package elements 46A and 46B within the package structure PKG. According to some embodiments, the spatial layout of package element 46A can be adapted within the boundary of protrusion 770p1, and similarly, the spatial layout of package element 46B can be adapted within the boundary of protrusion 770p2.

[0109] Therefore, based on the above discussion, it can be seen that this disclosure provides advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is a specific advantage claimed for all embodiments. This disclosure provides a method in various embodiments to reduce the number of thermal interfaces, thereby reducing thermal resistance and improving thermal performance, by incorporating back-side metallization on the wafer and heat dissipation elements and using a ring structure instead of a cap. Furthermore, incorporating a metal thermal interface material directly bonded to the heat dissipation element avoids the problem of remelting during reflow, which could affect the coverage and performance of the thermal interface material. In addition, ball grid array (BGA) packages with metal thermal interface materials offer a smaller size and greater input / output (I / O) capability compared to land grid array (LGA) packages, facilitating better system integration.

[0110] In some embodiments, a method of manufacturing a packaging structure includes: bonding the packaging structure to a substrate; attaching an annular structure to the substrate, the annular structure surrounding the packaging structure; forming a thermal interface material layer over the packaging structure; and attaching a heat dissipation structure to the thermal interface material layer and the annular structure, wherein the heat dissipation structure includes a cover portion and a plurality of heat dissipation fins, the plurality of heat dissipation fins extending upward from a top surface of the cover portion. In some embodiments, the method of manufacturing the packaging structure further includes: forming a metallization layer on the heat dissipation structure, wherein the heat dissipation structure is attached to the thermal interface material layer through the metallization layer. In some embodiments, the metallization layer includes aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), tantalum (Ta), silver (Ag), gold (Au), or any combination thereof. In some embodiments, the metallization layer has a thickness, the aforementioned thickness ranging from approximately to In some embodiments, the method of manufacturing the package structure further includes: after attaching a heat dissipation structure to a thermal interface material layer and an annular structure, forming an intermetallic compound layer between the metallization layer and the heat dissipation structure. In some embodiments, the intermetallic compound layer includes a gold-indium alloy, a nickel-indium alloy, a nickel-gold-indium alloy, or any combination thereof. In some embodiments, the intermetallic compound layer has a thickness ranging from approximately 0.1 to 2 μm. In some embodiments, the heat dissipation structure includes copper, aluminum, or any combination thereof. In some embodiments, the method of manufacturing the package structure further includes: bonding a surface mount element to a substrate; and conformally forming a protective coating on the surface mount element. In some embodiments, the protective coating includes acrylic, epoxy resin, or any combination thereof.

[0111] In some embodiments, a method of manufacturing a package structure includes: performing a back-side metallization process on the package structure to form a first metallization layer on the package structure; placing the package structure on an interposer; forming a thermal interface material layer on the first metallization layer; forming a second metallization layer on a heat dissipation structure; and attaching the heat dissipation structure to the thermal interface material layer through the second metallization layer. In some embodiments, the heat dissipation structure has a stepped structure protruding from its bottom surface, and the second metallization layer is formed on the stepped structure. In some embodiments, the heat dissipation structure has a flat bottom surface, and the second metallization layer is formed on the flat bottom surface. In some embodiments, the method of manufacturing the package structure further includes: placing an annular structure on the interposer to surround the package structure before attaching the heat dissipation structure to the thermal interface material layer through the second metallization layer. In some embodiments, the thermal interface material layer includes indium.

[0112] In some embodiments, the packaging structure includes a packaging element, a thermal interface material layer, a ring structure, and a heat dissipation element. The packaging element is located above a substrate. The packaging element includes a first element wafer, a second element wafer, and a packaging compound laterally surrounding the first element wafer and the second element wafer. The thermal interface material layer is located above the packaging element. The ring structure is located above the substrate and surrounds the packaging element. The heat dissipation element is located above the ring structure and the thermal interface material layer. The heat dissipation element includes a cover portion, a plurality of heat dissipation fins, a first protrusion, and a second protrusion. The plurality of heat dissipation fins extend upward from the top surface of the cover portion. The first and second protrusions extend downward from the bottom surface of the cover portion. The projected area of ​​the first protrusion on the substrate overlaps with the projected area of ​​the first element wafer on the substrate. The projected area of ​​the second protrusion on the substrate overlaps with the projected area of ​​the second element wafer on the substrate. In some embodiments, the first and second protrusions extend downward beyond the bottom surface of the cover portion. In some embodiments, the packaging structure further includes an intermetallic compound layer. The intermetallic compound layer is located between the thermal interface material layer and the first protrusion of the heat dissipation structure. In some embodiments, the ring structure includes stainless steel, copper, or a combination thereof. In some embodiments, the packaging structure further includes a surface mount element and a polymer-based coating. The surface mount element is located above the substrate. The polymer-based coating is conformally located on the surface mount element.

[0113] In some embodiments, the encapsulation structure includes a substrate, an encapsulation structure, a ring structure, a thermal interface material layer, and a heat dissipation structure. The encapsulation structure is located on the substrate. The ring structure is attached to the substrate and surrounds the encapsulation structure. The thermal interface material layer is attached to the encapsulation structure. The heat dissipation structure is attached to the thermal interface material layer and the ring structure, wherein the heat dissipation structure includes a cover portion and a plurality of heat dissipation fins extending upward from a top surface of the cover portion. In some embodiments, the encapsulation structure further includes a metallization layer. The metallization layer is located between the thermal interface material layer and the heat dissipation structure. In some embodiments, the encapsulation structure further includes an intermetallic compound layer. The intermetallic compound layer is located between the metallization layer and the heat dissipation structure.

[0114] In some embodiments, the encapsulation structure includes an interposer, an encapsulation structure, a first metallization layer, a thermal interface material layer, a second metallization layer, and a heat dissipation structure. The encapsulation structure is located on the interposer. The first metallization layer is located on the encapsulation structure. The thermal interface material layer is located on the first metallization layer. The second metallization layer is located on the thermal interface material layer. The heat dissipation structure is located on the second metallization layer. In some embodiments, the heat dissipation structure has a stepped structure protruding from its bottom surface, and the second metallization layer is formed on the stepped structure. In some embodiments, the encapsulation structure further includes an annular structure. The annular structure is located on the interposer and surrounds the encapsulation structure.

[0115] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A package structure, characterized by, include: A package element is located above a substrate, the package element including a first element wafer, a second element wafer, and a package compound that laterally surrounds the first element wafer and the second element wafer; A thermal interface material layer is located above the packaged element; A ring structure is located above the substrate and surrounds the encapsulation element; as well as A heat dissipation structure is located above the annular structure and the thermal interface material layer. The heat dissipation structure includes a cover portion, a plurality of heat dissipation fins, a first protrusion portion and a second protrusion portion. The plurality of heat dissipation fins extend upward from a top surface of the cover portion, and the first protrusion portion and the second protrusion portion extend downward from a bottom surface of the cover portion. The projected area of ​​the first protrusion portion on the substrate overlaps with the projected area of ​​the first component wafer on the substrate, and the projected area of ​​the second protrusion portion on the substrate overlaps with the projected area of ​​the second component wafer on the substrate.

2. The package structure of claim 1, wherein, The first protruding portion and the second protruding portion extend downward beyond the bottom surface of the covering portion.

3. The packaging structure as described in claim 1, characterized in that, Further includes: An intermetallic compound layer is located between the thermal interface material layer and the first protruding portion of the heat dissipation structure.

4. The packaging structure as described in claim 1, characterized in that, Further includes: A surface mount element is located above the substrate; as well as A polymer-based coating is conformally located on the surface-mount element.

5. A packaging structure, characterized in that, include: One substrate; An encapsulation structure is located on the substrate; A ring structure is attached to the substrate and surrounds the encapsulation structure; A thermal interface material layer is located on the packaging structure; as well as A heat dissipation structure is attached to the thermal interface material layer and the annular structure, wherein the heat dissipation structure includes a cover portion and a plurality of heat dissipation fins, the plurality of heat dissipation fins extending upward from a top surface of the cover portion.

6. The packaging structure as described in claim 5, characterized in that, Further includes: A metallization layer is located between the thermal interface material layer and the heat dissipation structure.

7. The packaging structure as described in claim 6, characterized in that, Further includes: An intermetallic compound layer is located between the metallization layer and the heat dissipation structure.

8. A packaging structure, characterized in that, include: One intermediary layer; An encapsulation structure is located on this interposer layer; A first metallization layer is located on the packaging structure; A thermal interface material layer is located on the first metallization layer; A second metallization layer is located on the thermal interface material layer; as well as A heat dissipation structure is located on the second metallization layer.

9. The packaging structure as described in claim 8, characterized in that, The heat dissipation structure has a stepped structure protruding from its bottom surface, and the second metallization layer is formed on the stepped structure.

10. The packaging structure as described in claim 8, characterized in that, Further includes: A ring structure is located on the intermediary layer and surrounds the encapsulation structure.

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