Semiconductor device

Abstract

A semiconductor device includes a plurality of nanostructures, a first source / drain contact, a second source / drain contact, a gate electrode, and a solid doped layer. The nanostructures are over a substrate. The first source / drain contact is over a first source / drain region of the nanostructures. The second source / drain contact is over a second source / drain region of the nanostructures. The gate electrode is between the first source / drain contact and the second source / drain contact. The solid doped layer overlaps the first source / drain contact.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a device having carbon nanotubes. Background Technology

[0002] As the semiconductor industry moves towards nanotechnology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs, such as gate all-around (GAA) structures. Non-silicon-based low-dimensional materials are excellent candidates for providing superior electrostatics (e.g., for short-channel effects) and higher performance (e.g., less surface scattering). Carbon nanotubes (CNTs) are considered promising candidates due to their high carrier mobility and essentially one-dimensional structure. Utility Model Content

[0003] In some embodiments, a semiconductor device includes a plurality of nanostructures above a substrate, a first source / drain contact above a first source / drain region of the plurality of nanostructures, a second source / drain contact above a second source / drain region of the plurality of nanostructures, a gate electrode between the first source / drain contact and the second source / drain contact, and a first solid-state doped layer overlapping the first source / drain contact.

[0004] In some embodiments, a semiconductor device includes a plurality of nanotubes above a substrate, a first metal contact above a first source / drain region of the plurality of nanotubes, a second metal contact above a second source / drain region of the plurality of nanotubes, a gate electrode between the first metal contact and the second metal contact, and a first nitride-based dielectric layer overlapping the first metal contact.

[0005] In some embodiments, a semiconductor device includes a plurality of carbon nanotubes above a substrate, a first metal contact above a first source / drain region of the plurality of carbon nanotubes, a second metal contact above a second source / drain region of the plurality of carbon nanotubes, a gate electrode between the first metal contact and the second metal contact, and a gate dielectric layer located between the gate electrode and the plurality of carbon nanotubes and covering the first metal contact. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a perspective view of a CNTFET according to some embodiments of the present disclosure;

[0008] Figure 2 yes Figure 1 The cross-sectional view of the CNTFET shown;

[0009] Figure 3A A cross-sectional view showing a multilayer stack including solid-state doped layers is shown.

[0010] Figures 3B to 3C Is it displayed as follows Figure 3A The graph shows the experimental results of multilayer stacking;

[0011] Figure 4A A cross-sectional view of the original CNTFET without a solid-state doped layer is shown.

[0012] Figure 4B A cross-sectional view of an electrostatically doped CNTFET with a solid-state doped layer is shown.

[0013] Figure 4C It is a display Figure 4A The original CNTFET shown Figure 4B The graph shows the experimental results of electrostatically doped CNFFET;

[0014] Figures 5A to 11D Top and cross-sectional views of intermediate stages of forming an example CNTFET according to some embodiments of the present disclosure are illustrated.

[0015] Figures 12A to 18D Top and cross-sectional views of intermediate stages of forming an example CNTFET according to some embodiments of the present disclosure are illustrated.

[0016] Figures 19A to 21D Top and cross-sectional views of intermediate stages of forming an example CNTFET according to some embodiments of the present disclosure are illustrated.

[0017] [Symbol Explanation]

[0018] 100:Substrate

[0019] 102: Dielectric layer

[0020] 104:CNT

[0021] 104c: Passage Area

[0022] 104 s / d: Source / Drain region

[0023] 106: Source / Drain Contacts

[0024] 108: Gate dielectric layer

[0025] 110: Oxide-based dielectric layer

[0026] 111: Double-layer electrostatic doped stack

[0027] 112: Nitride-based dielectric layer

[0028] 112h: Horizontal section

[0029] 112v: Vertical section

[0030] 114: Gate electrode

[0031] 300: Multi-layer stacking

[0032] 302: p-type substrate

[0033] 304: Oxide-based barrier layer

[0034] 306: Nitride-based dielectric layer

[0035] 308: Metal electrode

[0036] 400: Original CNTFET

[0037] 400a: Electrostatically Doped CNFFET

[0038] 402:Substrate

[0039] 404: Dielectric layer

[0040] 406:CNT

[0041] 408: Source / Drain Contact

[0042] 410: Oxide-based dielectric layer

[0043] 412: Nitride-based dielectric layer

[0044] 500:Substrate

[0045] 502: Dielectric layer

[0046] 504:CNT

[0047] 506: Source / Drain Contact

[0048] 508: Gate dielectric layer

[0049] 510: Gate electrode

[0050] 512: Oxide-based dielectric layer

[0051] 512s / d: Oxide-based dielectric layer

[0052] 514: Nitride-based dielectric layer

[0053] 514h: Higher Zone

[0054] 514l: Lower zone

[0055] 514s / d: Nitride-based dielectric layer

[0056] 600:Substrate

[0057] 602: Dielectric layer

[0058] 604: Nitride-based dielectric layer

[0059] 606: Oxide-based dielectric layer

[0060] 608:CNT

[0061] 610: Source / Drain Contact

[0062] 612: Gate dielectric layer

[0063] 614: Gate electrode

[0064] 616: Oxide-based dielectric layer

[0065] 616s / d: Oxide-based dielectric layer

[0066] 618: Nitride-based dielectric layer

[0067] 618s / d: Nitride-based dielectric layer

[0068] C1~C5: Curves

[0069] O1~O2: Grooves Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. As used herein, “approximately,” “about,” “roughly,” or “substantially” generally mean within 20%, 10%, or 5% of any approximate value or range of a given value. The quantities given herein are approximate, thus meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges mentioned throughout the specification are merely examples and may decrease or vary as the scale of integrated circuits shrinks.

[0072] Due to their cylindrical geometry and excellent electrical and mechanical properties, carbon nanotubes (CNTs) with nanometer-scale dimensions (e.g., about 1 nm) are considered a preferred material for fabricating miniaturized FET devices. Field-effect transistors (FETs) using CNTs with gate lengths of about 10 nm or less exhibit excellent electrical characteristics. However, the fabrication technology for CNT FETs is not yet well established.

[0073] Silicon-based devices rely on ion implantation to dope their source / drain (S / D) regions. However, this method can be detrimental to carbon nanotubes (CNTs) due to the high implantation energy, damaging the CNTs and impairing their transport properties. Conversely, lower-energy ion implantation cannot achieve sufficient doping effects. Therefore, the embodiments disclosed herein relate to an improved doping technique designed for carbon nanotube field-effect transistors (CNTFETs) that addresses the limitations of the aforementioned doping methods. Specifically, the embodiments disclosed herein use electrostatic doping to induce charge carriers in the source / drain regions of CNTs without implanting dopant atoms into the CNTs. Specifically, electrostatic doping can be achieved by forming one or more dielectric layers in proximity to the CNTs, wherein the one or more dielectric layers are non-stoichiometric, including nitrogen vacancies and / or oxygen vacancies, which can induce an electric field around the CNTs, thus inducing an n-type electrostatic doping effect in the CNTs.

[0074] Figure 1This is a perspective view of a CNTFET according to some embodiments of the present disclosure. Figure 2 yes Figure 1 The diagram shows a cross-sectional view of a CNTFET. The CNTFET is formed on substrate 100. In some embodiments, substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. Substrate 100 may include semiconductor materials, such as elemental semiconductors, including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, GaInAsP; combinations thereof, or the like. Substrate 100 may be doped or substantially undoped. In some embodiments, substrate 100 may be a sapphire substrate.

[0075] A dielectric layer 102 is formed above the substrate 100 to electrically isolate the overlying CNTFET from the underlying substrate 100. In some embodiments, the dielectric layer 102 is an interlayer dielectric (ILD) layer comprising an oxide-based dielectric material, such as silicon oxide (SiO2). x ), Hafnium oxide (HfO) x ), aluminum oxide (AlO) x ( ), analogues, or combinations thereof. In some embodiments, the dielectric layer 102 has a thickness ranging from about 10 nm to about 1000 nm.

[0076] Multiple carbon nanotubes (CNTs) or nanotubes 104 are disposed above the dielectric layer 102. The CNTs 104 are disposed on the dielectric layer 102 in substantially the same orientation (e.g., as shown in the image). Figure 1The CNT 104 is aligned in the X direction (as shown). In some embodiments, the alignment of the CNT 104 deviates from the X direction by about ±12 degrees, and in other embodiments by about ±3 degrees. In some embodiments, the CNT 104 is arranged along the Y direction at a density of about 20 tubes / μm to about 350 tubes / μm. In some embodiments, the length of the CNT 104 (in the X direction) is in the range of about 0.1 μm to about 10 μm. In some embodiments, the average diameter of the CNT 104 is in the range of about 1 nm to about 10 nm. In some embodiments, the CNT 104 can be formed by various methods, such as arc discharge or laser ablation methods, or template CVD methods on a sapphire substrate. The formed CNT 104 can be dispersed in a solvent, such as sodium dodecyl sulfate (SDS). The CNT 104 can be transferred to and disposed on the dielectric layer 102 using various methods, such as the floating evaporation self-assembly method in some embodiments. Carbon nanotubes are interchangeably referred to as nanostructures, one-dimensional (1D) channel structures, nanochannel structures, or atomic channel structures.

[0077] Source / drain contacts 106 are respectively disposed on the source / drain regions 104s / d of each CNT 104. In some embodiments, the source / drain contacts include Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof, and are therefore also referred to as metal contacts. In some embodiments, each source / drain contact 106 has a thickness ranging from about 20 nm to about 1000 nm.

[0078] A gate dielectric layer 108 is disposed above the channel region 104c of each CNT 104. In some embodiments, the gate dielectric layer 108 may comprise an oxide-based dielectric or a nitride-based dielectric. For example, the gate dielectric layer 108 comprises SiO2. x HfO x AlO x 、YO x ScO x MoO x WO x VO x SiN x HfN x AlN x YN x ,ScN x Analogs, or combinations thereof. In some embodiments, the gate dielectric layer 108 has a thickness ranging from about 2 nm to about 100 nm.

[0079] A nitride-based dielectric layer 112 is disposed above the source / drain regions 104s / d of each CNT 104 to induce electrostatic doping effects on the source / drain regions 104s / d of each CNT 104. In some embodiments, the nitride-based dielectric layer 112 is non-stoichiometric and includes nitrogen vacancies, which are sites where nitrogen atoms are missing. Therefore, the nitride-based dielectric layer with nitrogen vacancies can be interchangeably referred to as a nitrogen-vacancy-containing layer or a solid-state doping layer for inducing electrostatic effects on the source / drain regions 104s / d of the CNT 104. These nitrogen vacancies are not only empty spaces but also act as centers of electronic activity. They can trap electrons, thereby forming a region charge. The trapping of electrons at nitrogen vacancy sites generates a dipole moment due to charge separation. This dipole moment then generates an electric field that extends into the surrounding material, including the lower source / drain region 104s / d of the CNT 104. When the source / drain region 104s / d of the CNT 104 is close to the nitride substrate 112 with nitrogen vacancies, the electric field generated by the dipoles at the vacancy sites interacts with the electrons in the source / drain region 104s / d of the CNT 104. This interaction can lead to an n-type electrostatic doping effect on the source / drain region 104s / d of the CNT 104. In n-type doping, electrons are added to the conduction band of the material, increasing its conductivity. The electric field emanating from the nitrogen vacancy effectively “donates” electrons to the source / drain region 104s / d of the CNT 104, increasing the electron density in the conduction band of the source / drain region 104s / d of the CNT. This process does not involve the physical transfer of dopant atoms into the carbon nanotube structure as in existing ion implantation methods. Instead, it is an electrostatic effect in which the presence of an electric field alters the electronic properties of adjacent regions in CNT 104, making it behave as if it were doped with electron-donating atoms.

[0080] In some embodiments, the nitride-based dielectric layer 112 comprises a non-stoichiometric nitride material having nitrogen vacancies. For example, the nitride-based dielectric layer 112 may comprise SiN. x HfN x AlN x YN x ,ScN xAnalogs, or combinations thereof. For example, the nitride-based dielectric layer 112 comprises non-stoichiometric aluminum nitride, wherein the atomic ratio of aluminum (Al) to nitrogen (N) deviates from the ideal or stoichiometric ratio of 1:1. Non-stoichiometric aluminum nitride can be formed under certain conditions of aluminum excess or nitrogen deficiency during the formation process. Techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) can be optimized to adjust the flow rate ratio of aluminum-containing gas to nitrogen-containing gas, temperature, and pressure, thereby promoting the formation of nitrogen vacancies. This imbalance in the atomic ratio of aluminum to nitrogen can lead to the creation of nitrogen vacancies (missing nitrogen atoms) within the non-stoichiometric aluminum nitride, which contributes to the induction of electrostatic doping effects in the source / drain regions 104s / d within the CNT 104.

[0081] In some embodiments, the nitride-based dielectric layer 112 has a maximum thickness T1 ranging from about 2 nm to about 100 nm. The nitride-based dielectric layer 112 has a maximum thickness T1 in the region laterally offset from the source / drain contact 106 and a minimum thickness T2 in the region perpendicularly overlapping with the source / drain contact 106. In some embodiments, the minimum thickness T2 is less than the maximum thickness T1. This may be because the nitride-based dielectric layer 112 is not formed conformally to the underlying material, thereby increasing the overall volume of the nitride-based dielectric layer 112, which in turn enhances the electrostatic doping effect in the underlying source / drain region 104s / d of the CNT 104. In some embodiments, each nitride-based dielectric layer 112 has a vertical portion 112v extending vertically between the gate electrode 114 and the source / drain contact 106, and a horizontal portion 112h extending horizontally above the source / drain contact 106.

[0082] In some embodiments, an oxide-based dielectric layer 110 is disposed between the nitride-based dielectric layer 112 and the corresponding source / drain regions 104s / d in the CNT 104. The oxide-based dielectric layer 110 is used to further enhance the electrostatic doping effect and increase the carrier mobility in the source / drain regions 104s / d of the CNT 104. Specifically, the oxide-based dielectric layer 110 is a non-stoichiometric oxide layer with oxygen vacancies. Therefore, an oxide-based dielectric layer with oxygen vacancies can be interchangeably referred to as an oxygen-vacancy-containing layer or an oxygen-vacancy-containing oxide layer. The oxygen vacancy concentration in the oxide-based dielectric layer 110 may differ from the nitrogen vacancy level in the nitride-based dielectric layer 112. This difference in vacancy concentration can result in different charge numbers between the oxide-based dielectric layer 110 and the nitride-based dielectric layer 112, which enhances the electrostatic doping effect on the CNT 104 in a net effect.

[0083] In some embodiments, the oxide-based dielectric layer 110 includes SiO2. x HfO x AlO x 、YO x ScO x MoO x WO x VO x Analogs, or combinations thereof. For example, the oxide-based dielectric layer 110 may include non-stoichiometric yttrium oxide (YO). x In this process, the atomic ratio of yttrium (Y) to oxygen (O) deviates from the ideal or stoichiometric ratio of 2:3. This imbalance in the atomic ratio of yttrium to oxygen can lead to the creation of oxygen vacancies (missing oxygen atoms) within the non-stoichiometric yttrium oxide, which helps to enhance the electrostatic doping effect of the 104 s / d source / drain regions within the CNT 104.

[0084] In some embodiments, unlike the non-conformal profile of the nitride-based dielectric layer 112, the oxide-based dielectric layer 110 is a conformal layer having a cross-sectional profile that follows the topography of the underlying surface. The oxide-based dielectric layer 110 has a thickness T3 that is less than the minimum thickness T2 of the nitride-based dielectric layer 112. This thickness difference allows for the formation of a sufficiently thick nitride-based dielectric layer 112 at a sufficiently short distance from the CNT 104 to optimize electrostatic doping effects. In some embodiments, the oxide-based dielectric layer 110 has a thickness T3 ranging from about 1 angstrom to about 100 nm. In some embodiments, the oxide-based dielectric layer 110 and the nitride-based dielectric layer 112 may be collectively referred to as a double-layer electrostatic doped stack 111.

[0085] A gate electrode 114 is disposed above the gate dielectric layer 108. In some embodiments, the gate electrode 114 comprises Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof. In some embodiments, the gate electrode 106 has a thickness ranging from about 20 nm to about 1000 nm. The gate electrode 114 is disposed between two double-layer electrostatic doped stacks 111. In other words, the left double-layer electrostatic doped stack 111 on the left side of the gate electrode 114 is separated from the right double-layer electrostatic doped stack 111, and the gate electrode 114 is not covered by either of the double-layer electrostatic doped stacks 111.

[0086] Figures 3B to 3C Is it displayed as follows Figure 3A The graph shows the experimental results of the multilayer stack 300, which includes a p-type substrate 302, an oxide-based barrier layer 304 above the p-type substrate 302, a nitride-based dielectric layer 306 above the oxide-based barrier layer 304, and a metal electrode 308 above the nitride-based dielectric layer 306. In some embodiments, the oxide-based barrier layer 304 is a yttrium oxide layer with a thickness of approximately 4.2 nm. The nitride-based dielectric layer 306 is an aluminum nitride layer with nitrogen vacancies. Figure 3B The capacitance-voltage (CV) measurements of a multilayer structure 300 with nitride-based dielectric layers 306 of varying thicknesses are plotted at a frequency of approximately 1 MHz. A graph is plotted on the y-axis showing the capacitance per unit area (in nF / cm²). 2 The graph shows the relationship between the applied voltage (in V) on the x-axis and the voltage on the x-axis. The graphs show three different CV curves C1, C2, and C3 corresponding to the thicknesses of the nitride-based dielectric layer 306 at 0 nm, 5 nm, and 10 nm, indicating the capacitance changes during the voltage scan. Figure 3C It is to plot the flat-band voltage (V) derived from CV curves C1, C2, and C3. FB The graphs (in V) show the relationship between the flat-band voltage and the thickness of the nitride-based dielectric layer 306. These graphs indicate that as the thickness of the nitride-based dielectric layer 306 increases, the flat-band voltage gradually shifts towards more negative values. This observed trend suggests that the nitride-based dielectric layer 306 induces n-type conductivity in the multilayer stack 300.

[0087] Figure 4C Is it displayed as follows Figure 4A The original CNTFET 400 shown and as Figure 4BThe graph shows the experimental results for the electrostatically doped CNFFET 400a. The original CNFFET 400 includes a substrate 402, a dielectric layer 404 above the substrate 402, one or more CNTs 406 above the dielectric layer 404, and source / drain contacts 408 above the CNTs 406. The electrostatically doped CNFFET 400a generally shares the same structure as the original CNFFET 400, except that it further includes an oxide-based dielectric layer 410 with oxygen vacancies and a nitride-based dielectric layer 412 with nitrogen vacancies. Specifically, the oxide-based dielectric layer 410 includes a yttrium oxide layer, and the nitride-based dielectric layer 412 includes an aluminum nitride layer. Figure 4C Plot the current-voltage (I) of these CNTFETs D -V GS The characteristics are illustrated by plotting the current as a function of gate-source voltage for both the original CNTFET 400 and the electrostatically doped CNTFET 400a. Specifically, curve C4 represents the current-voltage characteristic of the original CNTFET 400, and curve C5 represents the current-voltage characteristic of the electrostatically doped CNTFET 400a. Figure 4C As shown, the electrostatic doping effect generated by dielectric layers 410 and 412 effectively affects the conductivity type of the CNTFET, as indicated by the shift from the original IV curve C4 to the electrostatically doped IV curve C5. Specifically, the original CNTFET 400 exhibits p-type transistor behavior as shown in IV curve C4, while the electrostatically doped CNTFET 400a exhibits n-type transistor behavior as shown in IV curve C5. This change in conductivity type is attributed to the induction of n-type charge carriers within CNT 406, which is likely due to the presence of positive charges in the nitride-based dielectric layer 412 caused by nitrogen vacancies. These experimental results demonstrate the effectiveness of electrostatic doping in modulating the conductivity type of the CNTFET through the strategic incorporation of a non-stoichiometric dielectric layer.

[0088] Figures 5A to 11D Top and cross-sectional views of intermediate stages in the formation of an example CNTFET according to some embodiments of this disclosure are illustrated. Although Figures 5A to 11D The top view and cross-sectional views shown are described with reference to one method, but it should be understood that... Figures 5A to 11D The structure shown is not limited to this method, but can exist independently of it. Although Figures 5A to 11D The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures.

[0089] Figure 5A This is a top view of an intermediate stage in the manufacturing of CNTFETs. Figure 5B From Figure 5AThe cross-sectional view obtained from section A-A' in the diagram. Figure 5C From Figure 5A The cross-sectional view obtained from section B-B'. Figures 5A to 5C The diagram illustrates a substrate 500. In some embodiments, substrate 500 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. Substrate 500 may include semiconductor materials, such as elemental semiconductors, including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, GaInAsP; combinations thereof, or the like. Substrate 500 may be doped or substantially undoped. In some embodiments, substrate 500 may be a sapphire substrate.

[0090] A dielectric layer 502 is formed over a substrate 500 using a suitable deposition technique. In some embodiments, the dielectric layer 502 is formed by, for example, spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like. In some embodiments, the dielectric layer 502 is an interlayer dielectric (ILD) layer formed of silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon nitride, amorphous boron nitride (a-BN), or the like. In some embodiments, the dielectric layer 502 has a thickness ranging from about 10 nm to about 1000 nm.

[0091] After forming a dielectric layer 502 over a substrate 500, a plurality of carbon nanotubes (CNTs) 504 are formed over the dielectric layer 502. The CNTs 504 are disposed on the dielectric layer 502 and extend in substantially the same direction. In some embodiments, the CNTs 504 can be formed by various methods, such as arc discharge or laser ablation methods, or by template CVD methods on a sapphire substrate. The formed CNTs 504 can be dispersed in a solvent, such as sodium dodecyl sulfate (SDS). The CNTs 504 can be transferred to and disposed on the dielectric layer 502 using various methods, such as the floating evaporation self-assembly method in some embodiments. For example, firstly, CNT 504 is disposed on a dummy substrate. Then, a transfer film is formed above CNT 504 and the dummy substrate. Next, the transfer film and CNT 504 are removed from the dummy substrate together. Then, the transfer film is attached to dielectric layer 502. Then, the transfer film is removed from dielectric layer 502, thereby leaving CNT 504 on dielectric layer 502.

[0092] Figure 6A Is Figures 5A to 5C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 6B From Figure 6A The cross-sectional view obtained from section A-A' in the diagram. Figure 6C From Figure 6A The cross-sectional view obtained from section B-B'. Figures 6A to 6C In this configuration, source / drain contacts 506 are formed on the source / drain regions of each CNT 504. From... Figure 6A As shown in the top view, each source / drain contact 506 has an elongated pattern extending across the CNT 504 in a direction perpendicular to its length. In this manner, the source regions of the CNT 504 share a continuous contact 506, and the drain regions of the CNT 504 share another continuous contact 506. In some embodiments, the source / drain contacts 506 comprise Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof, and are formed by a suitable deposition technique, such as CVD, ALD, PVD, the like, or combinations thereof. In some embodiments, each source / drain contact 506 has a thickness ranging from about 20 nm to about 1000 nm.

[0093] Figure 7A yes Figures 6A to 6C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 7B From Figure 7A The cross-sectional view obtained from section A-A' in the diagram. Figure 7C From Figure 7A The cross-sectional view obtained from section B-B' in the middle. Figure 7D From Figure 7A The cross-sectional view obtained from section C-C'. Figures 7A to 7D In this process, a gate dielectric layer 508 is deposited over the source / drain contacts 506 and channel regions of each CNT 104. In some embodiments, the gate dielectric layer 508 may comprise an oxide-based dielectric or a nitride-based dielectric formed using a suitable deposition method such as CVD, PVD, ALD, or a combination thereof. For example, the gate dielectric layer 508 comprises SiO2. x HfO x AlO x 、YO x ScO x MoO x WO x VO x SiN x HfN x AlN x YN x ,ScN x Analogs, compounds, or combinations thereof. In some embodiments, the gate dielectric layer 508 has a thickness ranging from about 2 nm to about 100 nm. In some embodiments, such as Figure 7D The depicted gate dielectric layer 508 is formed using a conformal deposition process. This method ensures that the layer conforms to the underlying surface profile (including source / drain contacts 506 and CNT 504). It should be noted that, for simplicity, [the following text is incomplete and requires further context]. Figure 7B and Figure 7C In the diagram, the gate dielectric layer 508 is not shown as having a conformal profile, and the diameter of CNT504 is shown to be significantly smaller than the thickness of the gate dielectric layer 508.

[0094] Figure 8A yes Figures 7A to 7D The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 8B From Figure 8A The cross-sectional view obtained from section A-A' in the diagram. Figure 8C From Figure 8A The cross-sectional view obtained from section B-B' in the middle. Figure 8D From Figure 8A The cross-sectional view obtained from section C-C'. Figures 8A to 8DIn this process, a gate electrode 510 is formed over a portion of the channel region of the gate dielectric layer 508 located in the CNT 504 using suitable deposition and patterning techniques. For example, in the process of forming the gate electrode 510, various deposition techniques can be used to deposit one or more metal layers over the gate dielectric layer 508. For example, one or more metal layers can be deposited over the gate dielectric layer 508 using, for example, PVD, CVD, plasma-enhanced CVD (PECVD), or the like. Once the metal layers(s) of the gate electrode 510 have been deposited, the next step involves patterning these metal layers to form the gate electrode 510. This can be achieved using optical lithography, a process involving coating one or more metal layers with a photoresist that is a photosensitive material. In some embodiments, the photoresist is then exposed to ultraviolet light through a photomask carrying the target pattern of the gate electrode 510. In some embodiments, the exposed areas of the photoresist become soluble and develop away, thereby exposing the underlying metal. Next, an etching process is used to remove the unprotected metal, leaving the patterned gate electrode 510. Etching can be performed using wet chemical etchants or dry etching techniques such as reactive ion etching (RIE), which provides high anisotropy and fidelity to the initial pattern.

[0095] In some embodiments, such as Figure 8A and Figure 8C As shown, the gate electrode 510 has an elongated pattern extending along a direction perpendicular to the length direction of the CNT 504. In this way, the channel regions of the CNT 504 share a continuous gate electrode 510. In some other embodiments, the gate electrode 510 may be patterned as discontinuous gate electrodes above the CNT 504, and the channel regions of the CNT 504 may be controlled by using individual gate electrodes. In some embodiments, the gate electrode 510 includes Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof. In some embodiments, the gate electrode 510 has a thickness ranging from about 20 nm to about 1000 nm.

[0096] Figure 9A Is Figures 8A to 8D The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 9B From Figure 9A The cross-sectional view obtained from section A-A' in the diagram. Figure 9C From Figure 9A The cross-sectional view obtained from section B-B' in the middle. Figure 9D From Figure 9A The cross-sectional view obtained from section C-C'. Figures 9A to 9DIn this CNT 504, an oxide-based dielectric layer 512 is formed over the source / drain contacts 506 and the gate electrode 510. The oxide-based dielectric layer 512 enhances electrostatic doping effects and improves carrier mobility in the source / drain regions. In some embodiments, the oxide-based dielectric layer 512 is a non-stoichiometric oxide layer with oxygen vacancies. For example, the oxide-based dielectric layer 512 may include non-stoichiometric SiO₂. x HfO x AlO x 、YO x ScO x MoO x WO x VO x or similar substances.

[0097] In some embodiments, the oxide-based dielectric layer 512 is a non-stoichiometric metal oxide (e.g., non-stoichiometric yttrium oxide), which can be formed by first depositing a metal layer (e.g., a yttrium layer) blanket over the gate dielectric layer 508 and the gate electrode 510, and then oxidizing the metal layer into a non-stoichiometric metal oxide. Non-stoichiometric yttrium oxide (YO) is formed. x The process involves controlling the oxidation environment to create oxygen vacancies of a desired level or concentration within the oxide substrate 512. A custom non-stoichiometric yttrium oxide layer with desired oxygen vacancies can be achieved by adjusting parameters such as temperature, pressure, and the flow rate of the oxidant during the oxidation process. In some embodiments, the oxide-based dielectric layer 512 has a thickness less than the minimum thickness of the gate dielectric layer 508 and the minimum thickness of the gate electrode 510.

[0098] Figure 10A yes Figures 9A to 9D The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 10B From Figure 10A The cross-sectional view obtained from section A-A' in the diagram. Figure 10C From Figure 10A The cross-sectional view obtained from section B-B' in the middle. Figure 10D From Figure 10A The cross-sectional view obtained from section C-C'. Figures 10A to 10D In this structure, a nitride-based dielectric layer 514 is formed above an oxide-based dielectric layer 512. The nitride-based dielectric layer 514 is formed from a non-stoichiometric nitride with nitrogen vacancies, thereby inducing electrostatic doping effects on the source / drain regions of the CNT 504, as discussed regarding... Figure 3B , Figure 3C ,and Figure 4C The experimental results shown are discussed in detail. In some embodiments, the nitride-based dielectric layer 514 comprises SiN. x HfNx AlN x YN x ,ScN x Analogs, or combinations thereof.

[0099] In some embodiments, the nitride-based dielectric layer 514 comprises nonstoichiometric aluminum nitride, wherein the atomic ratio of aluminum (Al) to nitrogen (N) deviates from a 1:1 stoichiometric ratio to create nitrogen vacancies of a desired level or concentration within the nitride-based dielectric layer 514. Precise control of the material composition at the atomic level to create nitrogen vacancies of the desired level can be achieved by using, for example, an atomic layer deposition (ALD) process. The ALD process involves the sequential use of gas-phase chemical processes. The oxide-based dielectric layer 512 is exposed to alternating precursor gases that react with the surface sequentially rather than overlapping, thereby allowing the film to grow atomically layer by layer. To produce nonstoichiometric aluminum nitride with nitrogen vacancies, the ALD process involves using an aluminum-containing precursor, such as trimethylaluminum (TMA), and a nitrogen-containing precursor, such as ammonia (NH3). The atomic ratio of aluminum to nitrogen can be controlled by adjusting the exposure time to the nitrogen-containing precursor and the purge time between pulses of the aluminum-containing precursor. For example, shorter exposure times to nitrogen-containing precursors or longer cleanup times following nitrogen-containing precursors can result in lower nitrogen concentrations, thereby creating nitrogen vacancies within the nitride-based dielectric layer 514. Process temperature and pressure can also be adjusted to control the stoichiometry of the non-stoichiometric AlN film, thereby obtaining the desired level of nitrogen vacancies.

[0100] like Figure 10D As shown, in some embodiments, the nitride-based dielectric layer 514 has a top surface having a higher region 514h overlapping the channel region of the CNT 504 and a lower region 514l overlapping the source / drain region of the CNT 504. This is because the gate electrode 510 has a top surface higher than the top surface of the source / drain contact 506. In some embodiments, the nitride-based dielectric layer 514 has a minimum thickness greater than the maximum thickness of the oxide-based dielectric layer 512, which allows for the formation of a sufficiently thick nitride-based dielectric layer 514 at a sufficiently short distance from the CNT 504, thereby improving electrostatic doping effects.

[0101] Figure 11A yes Figures 10A to 10D The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 11B From Figure 11A The cross-sectional view obtained from section A-A' in the diagram. Figure 11C From Figure 11A The cross-sectional view obtained from section B-B' in the middle. Figure 11D From Figure 11A The cross-sectional view obtained from section C-C'. Figures 11A to 11D In this process, the nitride-based dielectric layer 514 and the oxide-based dielectric layer 512 are patterned to form trenches O1 on the top surface of the gate electrode 510 using suitable optical lithography and etching techniques. For example, a photoresist layer is formed over the nitride-based dielectric layer 514 using a spin-coating process, and then the photoresist layer is patterned using suitable optical lithography techniques to expose the target area of ​​the nitride-based dielectric layer 514. For example, the photoresist layer is irradiated (exposed) and developed to remove portions of the photoresist layer. More specifically, a photomask or master photomask (not shown) can be placed on the photoresist layer and then exposed to a radiation beam, which can be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using immersion lithography or extreme ultraviolet (EUV) tools to increase resolution and reduce the minimum achievable pitch. Baking or curing operations can be performed to harden the exposed photoresist layer, and depending on whether a positive or negative photoresist is used, the exposed or unexposed portions of the photoresist material can be removed using a developer. After forming the patterned photoresist layer, one or more etching processes are performed on the regions of the nitride-based dielectric layer 514 and the oxide-based dielectric layer 512 corresponding to the pattern of the gate electrode 510, thereby forming trenches O1 in the nitride-based dielectric layer 514 and the oxide-based dielectric layer 512.

[0102] In some embodiments, trench O1 is etched in the nitride-based dielectric layer 514 using a selective etching process, which selectively etches the nitride-based dielectric layer 514 while there is no etching or negligible etching in the oxide-based dielectric layer 512. For example, the nitride-based dielectric layer 514 can be selectively etched using phosphoric acid. After the initial etching of trench O1 in the nitride-based dielectric layer 514, trench O1 is then etched in the oxide-based dielectric layer 512 using another selective etching process, which selectively etches the oxide-based dielectric layer 512 while there is no etching or negligible etching in the gate electrode 510. For example, the oxide-based dielectric layer 512 can be selectively etched using hydrofluoric acid (HF). The selective etching of the oxide-based dielectric layer 512 continues until the top surface of the gate electrode 510 is exposed.

[0103] like Figure 11A and Figure 11DAs shown, trench O1 extends parallel to gate electrode 510 and splits the continuous nitride-based dielectric layer 514 into two separate nitride-based dielectric layers 514s / d spaced apart by gate electrode 510. Trench O1 further splits the continuous oxide-based dielectric layer 512 into separate oxide-based dielectric layers 512s / d spaced apart by gate electrode 510. Each nitride-based dielectric layer 514s / d and the underlying oxide-based dielectric layer 512s / d jointly overlap with the source / drain region within CNT 504, inducing n-type carriers (i.e., electrons) in the source / drain region within CNT 504 through electrostatic doping effects.

[0104] Figures 12A to 18D Top and cross-sectional views of intermediate stages in the formation of an example CNTFET according to some embodiments of this disclosure are illustrated. Although Figures 12A to 18D The top view and sectional view shown are described with reference to one method, but it should be understood that... Figures 12A to 18D The structure shown is not limited to this method, but can exist independently of it. Although Figures 12A to 18D The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures.

[0105] Figure 12A This is a top view of an intermediate stage in the manufacturing of CNTFETs. Figure 12B From Figure 12A The cross-sectional view obtained from section A-A' in the diagram. Figure 12C From Figure 12A The cross-sectional view obtained from section B-B'. Figures 12A to 12C In this process, a dielectric layer 602 is formed above the substrate 600. The dielectric layer 602 and the substrate 600 may be the same as the dielectric layer 502 and the substrate 500, respectively. Therefore, for the sake of simplicity, the details of the dielectric layer 602 and the substrate 600 will not be repeated.

[0106] Figure 13A Is Figures 12A to 12C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 13B From Figure 13A The cross-sectional view obtained from section A-A' in the diagram. Figure 13C From Figure 13A The cross-sectional view obtained from section B-B'. Figures 13A to 13C In this process, a nitride-based dielectric layer 604 is formed above the dielectric layer 602. The nitride-based dielectric layer 604 is formed of a non-stoichiometric nitride with nitrogen vacancies, thereby serving to induce electrostatic doping effects on the source / drain regions of the subsequently formed CNTs, as per [reference needed]. Figure 3B , Figure 3C ,and Figure 4CThe experimental results shown are discussed in detail. In some embodiments, the nitride-based dielectric layer 604 comprises SiN. x HfN x AlN x YN x ,ScN x Analogs, or combinations thereof.

[0107] In some embodiments, the nitride-based dielectric layer 604 comprises nonstoichiometric aluminum nitride, wherein the atomic ratio of aluminum (Al) to nitrogen (N) deviates from a 1:1 stoichiometric ratio to create nitrogen vacancies of a desired level or concentration within the nitride-based dielectric layer 604. Precise control of the material composition at the atomic level to create nitrogen vacancies of the desired level can be achieved by using, for example, an atomic layer deposition (ALD) process. The ALD process involves the sequential use of gas-phase chemical processes. The dielectric layer 602 is exposed to alternating precursor gases that react with the surface sequentially rather than overlapping, allowing the film to grow atomically layer by layer. To produce nonstoichiometric aluminum nitride with nitrogen vacancies, the ALD process involves using an aluminum-containing precursor, such as trimethylaluminum (TMA), and a nitrogen-containing precursor, such as ammonia (NH3). The atomic ratio of aluminum to nitrogen can be controlled by adjusting the exposure time to the nitrogen-containing precursor and the purge time between pulses of the aluminum-containing precursor. For example, shorter exposure times to nitrogen-containing precursors or longer purification times after nitrogen-containing precursors can result in lower nitrogen concentrations, thereby creating nitrogen vacancies within the nitride-based dielectric layer 604. Process temperature and pressure can also be adjusted to control the stoichiometry of the non-stoichiometric AlN film, thereby obtaining the desired level of nitrogen vacancies.

[0108] Figure 14A yes Figures 13A to 13C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 14B From Figure 14A The cross-sectional view obtained from section A-A' in the diagram. Figure 14C From Figure 14A The cross-sectional view obtained from section B-B'. Figures 14A to 14C In this configuration, an oxide-based dielectric layer 606 is formed over a nitride-based dielectric layer 604. The oxide-based dielectric layer 606 enhances electrostatic doping effects and improves carrier mobility in the source / drain regions of the subsequently formed CNTs. In some embodiments, the oxide-based dielectric layer 606 is a non-stoichiometric oxide layer with oxygen vacancies. For example, the oxide-based dielectric layer 606 may comprise non-stoichiometric SiO₂. x HfO x AlO x 、YO x ScO x MoO xWO x VO x or similar substances.

[0109] In some embodiments where the oxide-based dielectric layer 606 is a non-stoichiometric metal oxide (e.g., non-stoichiometric yttrium oxide), the oxide-based dielectric layer 606 can be formed by first depositing a metal layer (e.g., a yttrium layer) over a nitride-based dielectric layer 604, and then oxidizing the metal layer into a non-stoichiometric metal oxide. Non-stoichiometric yttrium oxide (YO) is formed. x The process involves controlling the oxidation environment to create oxygen vacancies of a desired level or concentration within the oxide-based dielectric layer 606. A custom non-stoichiometric yttrium oxide layer with the desired level or concentration of oxygen vacancies can be achieved by adjusting parameters such as temperature, pressure, and the flow rate of the oxidant during the oxidation process. In some embodiments, the oxide-based dielectric layer 606 has a thickness less than that of the nitride-based dielectric layer 604, which allows for the formation of a sufficiently thick nitride-based dielectric layer 606 at a sufficiently short distance from the subsequently formed CNTs, thereby improving electrostatic doping effects.

[0110] Figure 15A yes Figures 14A to 14C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 15B From Figure 15A The cross-sectional view obtained from section A-A' in the diagram. Figure 15C From Figure 15A The cross-sectional view obtained from section B-B'. Figures 15A to 15C In this structure, multiple carbon nanotubes (CNTs) 608 are formed on top of an oxide-based dielectric layer 606. The CNTs 608 are disposed on the oxide-based dielectric layer 606 and extend in substantially the same direction. In some embodiments, the CNTs 608 can be formed by various methods, such as arc discharge or laser ablation methods, or by template CVD methods on a sapphire substrate. The formed CNTs 608 can be dispersed in a solvent, such as sodium dodecyl sulfate (SDS). Various methods can be used to transfer and deposit CNTs 608 onto the oxide-based dielectric layer 606, such as the floating evaporation self-assembly method in some embodiments. For example, firstly, CNT 608 is disposed on a dummy substrate. Then, a transfer film is formed over CNT 608 and the dummy substrate. Next, the transfer film and CNT 608 are removed from the dummy substrate together. Then, the transfer film is attached to the oxide-based dielectric layer 606. Then, the transfer film is removed from the oxide-based dielectric layer 606, thereby leaving CNT 608 on the oxide-based dielectric layer 606.

[0111] Figure 16A Is Figures 15A to 15CThe diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 16B From Figure 16A The cross-sectional view obtained from section A-A' in the diagram. Figure 16C From Figure 16A The cross-sectional view obtained from section B-B'. Figures 16A to 16C In this configuration, source / drain contacts 610 are formed on the source / drain regions of each CNT 608. From... Figure 6A As shown in the top view, each source / drain contact 610 has an elongated pattern extending across the CNT 608 in a direction perpendicular to its length. In this manner, the source regions of the CNT 608 share a continuous contact 610, and the drain regions of the CNT 608 share another continuous contact 610. In some embodiments, the source / drain contacts 610 comprise Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof, and are formed by a suitable deposition technique, such as CVD, ALD, PVD, the like, or combinations thereof. Figure 16B As shown, the source / drain contact 610 has a bottom surface that contacts the top surface of the oxide-based dielectric layer 606.

[0112] Figure 17A yes Figures 16A to 16C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 17B From Figure 17A The cross-sectional view obtained from section A-A' in the diagram. Figure 17C From Figure 17A The cross-sectional view obtained from section B-B'. Figures 17A to 17C In this process, a gate dielectric layer 612 is deposited over the source / drain contacts 506 and channel regions of each CNT 608. In some embodiments, the gate dielectric layer 612 may comprise an oxide-based dielectric or a nitride-based dielectric formed using a suitable deposition method such as CVD, PVD, ALD, or a combination thereof. For example, the gate dielectric layer 612 comprises SiO2. x HfO x AlO x 、YO x ScO x MoO x WO x VO x SiN x HfN x AlN x YN x ,ScN xAnalogs, compounds, or combinations thereof. In some embodiments, the gate dielectric layer 612 has a thickness ranging from about 2 nm to about 100 nm. In some embodiments, such as Figure 17C The depicted gate dielectric layer 612 is formed using a conformal deposition process. This method ensures that the layer conforms to the underlying surface profile (including source / drain contacts 610 and CNT 608). It should be noted that, for simplicity, the gate dielectric layer 612 is... Figure 17B The diagram does not show a conformal profile and shows that the diameter of CNT 608 is significantly smaller than the thickness of the gate dielectric layer 612.

[0113] Figure 18A Is Figures 17A to 17C The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 18B From Figure 18A The cross-sectional view obtained from section A-A' in the diagram. Figure 18C From Figure 18A The cross-sectional view obtained from section B-B' in the middle. Figure 18D From Figure 18A The cross-sectional view obtained from section C-C'. Figures 18A to 18D In this embodiment, a gate electrode 614 is formed over a portion of the channel region of the CNT 608 using a suitable deposition and patterning technique. In some embodiments, the gate electrode 614 has an elongated pattern extending along a direction perpendicular to the length direction of the CNT 608. In this way, the channel regions of the CNT 608 share a continuous gate electrode 614. In some other embodiments, the gate electrode 614 may be patterned as discontinuous gate electrodes over the CNT 608, and the channel regions of the CNT 608 can be controlled by using individual gate electrodes. In some embodiments, the gate electrode 614 comprises Pd, Pt, Au, Sc, Y, W, Ti, TiN, the like, or combinations thereof.

[0114] exist Figures 18A to 18D In the CNTFET device shown, the nitride-based dielectric layer 604 and the oxide-based dielectric layer 606 overlap entirely with the CNT 608, thus potentially inducing electrostatic doping effects across the entire CNT 608. In this scenario, the operating voltage of the CNTFET can be related to... Figures 11A to 11D The CNTFET shown is different.

[0115] Figures 19A to 21D Top and cross-sectional views of intermediate stages in the formation of an example CNTFET according to some embodiments of this disclosure are illustrated. Although Figures 19A to 21D The top view and sectional view shown are described with reference to one method, but it should be understood that... Figures 19A to 21D The structure shown is not limited to this method, but can exist independently of it. Although Figures 19A to 21D The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures.

[0116] Figure 19A This is a top view of an intermediate stage in the manufacturing of CNTFETs. Figure 19B From Figure 19A The cross-sectional view obtained from section A-A' in the diagram. Figure 19C From Figure 19A The cross-sectional view obtained from section B-B' in the middle. Figure 19D From Figure 19A The cross-sectional view obtained from section C-C'. Figures 19A to 19D The CNTFET shown is generally with Figures 18A to 18D The configuration is the same as shown, except that an additional oxide-based dielectric layer 616 is formed above the gate dielectric layer 612 and the gate electrode 614. The oxide-based dielectric layer 616 is used to enhance electrostatic doping effects and improve carrier mobility in the source / drain regions of the CNT 608. In some embodiments, the oxide-based dielectric layer 616 is a non-stoichiometric oxide layer with oxygen vacancies. For example, the oxide-based dielectric layer 616 may comprise non-stoichiometric SiO₂. x HfO x AlO x 、YO x ScO x MoO x WO x VO x or similar substances.

[0117] In some embodiments where the oxide-based dielectric layer 616 is a non-stoichiometric metal oxide (e.g., non-stoichiometric yttrium oxide), the oxide-based dielectric layer 616 can be formed by first depositing a metal layer (e.g., a yttrium layer) overlay over the gate dielectric layer 612 and the gate electrode 614, and then oxidizing the metal layer into a non-stoichiometric metal oxide. Non-stoichiometric yttrium oxide (YO) is formed. x The process involves controlling the oxidation environment to create oxygen vacancies of the desired level or concentration within the oxide-based dielectric layer 616. By adjusting parameters such as temperature, pressure, and the flow rate of the oxidant during the oxidation process, a custom non-stoichiometric yttrium oxide layer with the desired level or concentration of oxygen vacancies can be achieved.

[0118] Figure 20A Is Figures 19A to 19D The diagram shows a top view of an intermediate stage in the manufacturing of CNTFETs, following the previous stage. Figure 20B From Figure 20A The cross-sectional view obtained from section A-A' in the diagram. Figure 20C From Figure 20A The cross-sectional view obtained from section B-B' in the middle. Figure 20D From Figure 20A The cross-sectional view obtained from section C-C'. Figures 20A to 20D In this process, a nitride-based dielectric layer 618 is formed above an oxide-based dielectric layer 616. The nitride-based dielectric layer 618 is formed of a non-stoichiometric nitride with nitrogen vacancies, thereby serving to induce electrostatic doping effects on the source / drain regions of the subsequently formed CNTs, as discussed in... Figure 3B , Figure 3C ,and Figure 4C The experimental results shown are discussed in detail. In some embodiments, the nitride-based dielectric layer 618 comprises SiN. x HfN x AlN x YN x ,ScN x Analogs, or combinations thereof.

[0119] In some embodiments, the nitride-based dielectric layer 618 comprises nonstoichiometric aluminum nitride, wherein the atomic ratio of aluminum (Al) to nitrogen (N) deviates from a 1:1 stoichiometric ratio to create nitrogen vacancies of a desired level or concentration within the nitride-based dielectric layer 618. Precise control of the material composition at the atomic level to create nitrogen vacancies of the desired level can be achieved by using, for example, an atomic layer deposition (ALD) process. The ALD process involves the sequential use of gas-phase chemical processes. The oxide-based dielectric layer 616 is exposed to alternating precursor gases that react with the surface sequentially rather than overlapping, thereby allowing the film to grow atomically layer by layer. To produce nonstoichiometric aluminum nitride with nitrogen vacancies, the ALD process involves using an aluminum-containing precursor, such as trimethylaluminum (TMA), and a nitrogen-containing precursor, such as ammonia (NH3). The atomic ratio of aluminum to nitrogen can be controlled by adjusting the exposure time to the nitrogen-containing precursor and the purge time between pulses of the aluminum-containing precursor. For example, shorter exposure times to nitrogen-containing precursors or longer cleanup times after nitrogen-containing precursors can result in lower nitrogen concentrations, thereby creating nitrogen vacancies within the nitride-based dielectric layer 618. Process temperature and pressure can also be adjusted to control the stoichiometry of the non-stoichiometric AlN film, thereby obtaining the desired level of nitrogen vacancies.

[0120] Figure 21A yes Figures 20A to 20D A top view of an intermediate stage in the manufacturing of CNTFETs, following the stage shown. Figure 21B From Figure 21A The cross-sectional view obtained from section A-A' in the diagram. Figure 21C From Figure 21A The cross-sectional view obtained from section B-B' in the middle. Figure 21D From Figure 21AThe cross-sectional view obtained from section C-C'. Figures 21A to 21D In this process, the nitride-based dielectric layer 618 and the oxide-based dielectric layer 616 are patterned to form trenches O2 on the top surface of the exposed gate electrode 614 by using suitable optical lithography and etching techniques.

[0121] In some embodiments, trench O2 is etched in the nitride-based dielectric layer 618 using a selective etching process, which selectively etches the nitride-based dielectric layer 618 while there is no etching or negligible etching in the oxide-based dielectric layer 616. For example, the nitride-based dielectric layer 618 can be selectively etched using phosphoric acid. After the initial etching of the trench O2 in the nitride-based dielectric layer 618, the trench O2 is then etched in the oxide-based dielectric layer 616 using another selective etching process, which selectively etches the oxide-based dielectric layer 616 while there is no etching or negligible etching in the gate electrode 614. For example, the oxide-based dielectric layer 616 can be selectively etched using hydrofluoric acid (HF). The selective etching of the oxide-based dielectric layer 616 continues until the top surface of the gate electrode 614 is exposed.

[0122] like Figure 21A and Figure 21C As shown, trench O2 extends parallel to gate electrode 614 and splits the continuous nitride-based dielectric layer 618 into two separate nitride-based dielectric layers 618s / d spaced apart by gate electrode 614s. Trench O2 further splits the continuous oxide-based dielectric layer 616 into separate oxide-based dielectric layers 616s / d spaced apart by gate electrode 614. Each nitride-based dielectric layer 618s / d and the underlying oxide-based dielectric layer 616s / d jointly overlap with the source / drain region within CNT 504, inducing n-type carriers (i.e., electrons) in the source / drain region within CNT 504 through electrostatic doping effects.

[0123] Based on the above discussion, it is clear that this disclosure offers advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages herein, nor is any particular advantage required for all embodiments. One advantage is that the source / drain regions of the CNTFET can be doped using electrostatic doping effects without implanting dopant species into the CNT, which in turn prevents potential damage due to ion implantation into the CNT.

[0124] In some embodiments, this disclosure provides a method comprising the steps of forming a plurality of nanostructures over a substrate and forming a first source / drain contact over a first source / drain region of the plurality of nanostructures. Additionally, the method involves forming a second source / drain contact over a second source / drain region of the plurality of nanostructures and forming a gate electrode over a channel region of the plurality of nanostructures. Furthermore, the method includes forming a solid-state doped layer over the gate electrode and over the first and second source / drain contacts. The method terminates by removing a first portion of the solid-state doped layer from the top surface of the gate electrode, while a second and third portion of the solid-state doped layer remain over the first and second source / drain contacts, respectively. In some embodiments, the method further includes forming an oxygen-vacant oxide layer over the first and second source / drain contacts. In some embodiments, the oxygen-vacant oxide layer is formed prior to the formation of the solid-state doped layer. In some embodiments, the oxygen-vacant oxide layer has a thickness less than the minimum thickness of the solid-state doped layer. The oxygen-vacant oxide layer is further formed over the gate electrode. The method further includes removing a first portion of the oxygen-vacant oxide layer from the top surface of the gate electrode, and leaving a second and a third portion of the oxygen-vacant oxide layer above the first and second contacts, respectively. In some embodiments, the oxygen-vacant oxide layer comprises SiO₂. x HfO x AlO x 、YO x ScO x MoO x WO x , or VO x The solid-state doped layer contains SiN x HfN x AlN x YN x or ScN x The method further includes forming a gate dielectric layer over first and second source / drain contacts and channel regions of a plurality of nanostructures. The gate dielectric layer is formed prior to the formation of a solid-state doped layer. In some embodiments, a second portion of the solid-state doped layer includes a vertically extending portion between the gate electrode and the first source / drain contact, and a horizontally extending portion above the first source / drain contact. A third portion of the solid-state doped layer includes a vertically extending portion between the gate electrode and the second source / drain contact, and a horizontally extending portion above the second source / drain contact.

[0125] In some embodiments, this disclosure provides a method comprising forming a first solid-state doped layer over a substrate. This method further involves disposing of a plurality of nanostructures over the aforementioned nitride layer. Furthermore, the method includes forming a first source / drain contact over a first source / drain region of the nanostructure. A second source / drain contact is also formed over a second source / drain region of the nanostructure. The method further includes forming a gate electrode located between the first and second source / drain contacts. The method further includes forming an oxygen-vacant oxide layer over a first nitrogen-vacant nitride layer. In some embodiments, a plurality of nanostructures are disposed on the oxygen-vacant oxide layer. In some embodiments, the method further includes forming a second solid-state doped layer over the first and second source / drain contacts and the gate electrode; and removing a first portion of the second solid-state doped layer from the top surface of the gate electrode, leaving a second portion and a third portion of the second solid-state doped layer over the first and second source / drain contacts, respectively. In some embodiments, the method further includes forming the oxygen-vacant oxide layer over the first and second source / drain contacts before forming the second solid-state doped layer.

[0126] In some embodiments, this disclosure provides an apparatus comprising a plurality of nanostructures above a substrate, a first source / drain contact above a first source / drain region of the nanostructures, a second source / drain contact above a second source / drain region of the nanostructures, a gate electrode between the first and second source / drain contacts, and a first solid-state doped layer overlapping the first source / drain contact. In some embodiments, the apparatus further comprises a second solid-state doped layer overlapping the second source / drain contact, and a third solid-state doped layer between the nanostructures and the substrate. In some embodiments, the apparatus further comprises an oxide layer between the first solid-state doped layer and the first source / drain contact.

[0127] In some embodiments, a semiconductor device includes a plurality of nanotubes above a substrate, a first metal contact above a first source / drain region of the plurality of nanotubes, a second metal contact above a second source / drain region of the plurality of nanotubes, a gate electrode between the first metal contact and the second metal contact, and a first nitride-based dielectric layer overlapping the first metal contact. In some embodiments, the semiconductor device further includes a second nitride-based dielectric layer overlapping the second metal contact. In some embodiments, the semiconductor device further includes a dielectric layer between the plurality of nanotubes and the substrate. In some embodiments, the semiconductor device further includes an oxide-based dielectric layer between the first nitride-based dielectric layer and the first metal contact.

[0128] In some embodiments, a semiconductor device includes a plurality of carbon nanotubes above a substrate, a first metal contact above a first source / drain region of the plurality of carbon nanotubes, a second metal contact above a second source / drain region of the plurality of carbon nanotubes, a gate electrode between the first metal contact and the second metal contact, and a gate dielectric layer located between the gate electrode and the plurality of carbon nanotubes and covering the first metal contact. In some embodiments, the semiconductor device further includes an oxide-based dielectric layer located on the gate dielectric layer; and a nitride-based dielectric layer located on the oxide-based dielectric layer.

[0129] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: Multiple nanostructures on a substrate; A first source / drain contact above the first source / drain region of the plurality of nanostructures; a second source / drain contact above the second source / drain region of the plurality of nanostructures; a gate electrode between the first source / drain contact and the second source / drain contact; and A first solid-state doped layer that overlaps with the first source / drain contact.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A second solid-state doped layer that overlaps with the second source / drain contact.

3. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A third solid-state doped layer between the plurality of nanostructures and the substrate.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: An oxide layer between the first solid doped layer and the first source / drain contact.

5. A semiconductor device, characterized in that, Include: Multiple nanotubes above a substrate; A first metal contact above the first source / drain region of the plurality of nanotubes; A second metal contact above the second source / drain regions of the plurality of nanotubes; A gate electrode between the first metal contact and the second metal contact; and A first nitride-based dielectric layer overlapping the first metal contact.

6. The semiconductor device as claimed in claim 5, characterized in that, Also includes: A second nitride-based dielectric layer overlapping the second metal contact.

7. The semiconductor device as claimed in claim 5, characterized in that, Also includes: A dielectric layer between the plurality of nanotubes and the substrate.

8. The semiconductor device as claimed in claim 5, characterized in that, Also includes: An oxide-based dielectric layer between the first nitride-based dielectric layer and the first metal contact.

9. A semiconductor device, characterized in that, Include: Multiple carbon nanotubes above a substrate; A first metal contact above the first source / drain region of the plurality of carbon nanotubes; A second metal contact above the second source / drain regions of the plurality of carbon nanotubes; A gate electrode between the first metal contact and the second metal contact; and A gate dielectric layer is located between the gate electrode and the plurality of carbon nanotubes and covers the first metal contact.

10. The semiconductor device as claimed in claim 9, characterized in that, Also includes: An oxide-based dielectric layer is located on the gate dielectric layer; and A nitride-based dielectric layer is located on the oxide-based dielectric layer.

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