A stacked package memory chip

Abstract

The utility model belongs to the technical field of storage chip, and disclose a kind of laminated packaging's storage chip, including substrate, the substrate upper is equipped with wire carrier plate, wire carrier plate bottom linear array is equipped with external metal ball, between substrate and wire carrier plate, wire carrier plate top is equipped with silicate interposer, and the silicate interposer top linear array is equipped with wafer.The utility model is cooperated by carbon nanotube, ceramic shell and metal shell etc. structure, ceramic shell and metal shell form double protection structure, ceramic shell has good insulation and high temperature resistance, can protect internal component from high temperature and electric field interference, and cooperate metal shell to improve heat dissipation effect, while metal shell can effectively resist external physical collision, shielding electromagnetic interference simultaneously, guarantee the stable work of chip in complex environment, realize the effect of laminated chip high-efficiency heat dissipation.

Description

Technical Field

[0001] This utility model belongs to the field of memory chip technology, specifically a stacked packaged memory chip. Background Technology

[0002] Memory chips are electronic components that can temporarily or permanently store data and information. They are the core components for electronic devices to achieve memory. They are like the "warehouse" of electronic devices, responsible for storing various types of data such as programs required for system operation, user photos, documents, and videos, so that the device can retain key information after power failure or quickly retrieve data during operation.

[0003] When chips are stacked and packaged, the lower chip not only has to withstand the heat generated by its own operation, but also the heat conducted down from the upper chip, causing the local temperature of the chip to rise sharply, which seriously affects the performance and reliability of the chip. This results in poor heat dissipation of existing stacked chips. In view of this, a stacked packaged memory chip is proposed to solve the above problems. Summary of the Invention

[0004] To address the problems mentioned in the background section, this invention provides a stacked packaged memory chip.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a stacked packaged memory chip, comprising a substrate, a conductive carrier plate disposed on the top of the substrate, an outer metal ball linearly arrayed at the bottom of the conductive carrier plate located between the substrate and the conductive carrier plate, a silicon interposer plate disposed on the top of the conductive carrier plate, a wafer linearly arrayed on the top of the silicon interposer plate, a plurality of carbon nanotubes disposed between adjacent wafers and between the silicon interposer plate and the top wafer, a ceramic shell disposed on the top of the conductive carrier plate, and a metal shell disposed on the outside of the ceramic shell.

[0006] Preferably, the ceramic outer shell has several through holes on its outer side, and the metal outer shell has through blocks fixedly provided on the inner side corresponding to the through holes, with the through blocks snapped into the inner side of the through holes.

[0007] Preferably, the silicon interposer and the bottom of the wafer are provided with transistors corresponding to the outer metal spheres, the transistors are provided with empty layers between each adjacent wafer, and the carbon nanotubes are provided between the empty layers.

[0008] Preferably, carbon nanotubes are arranged in a linear array on the inner side of the empty layer, located outside the outermost transistor.

[0009] Preferably, the silicon interposer and the outer surfaces of both the silicon interposer and the non-top wafer are provided with through holes, which are correspondingly arranged for connecting the silicon interposer and each wafer layer.

[0010] Preferably, the perforations in the silicon interposer are connected on both sides and connected to a transistor.

[0011] Compared with the prior art, the beneficial effects of this utility model are as follows: This invention utilizes a combination of carbon nanotubes, a ceramic shell, and a metal shell. The ceramic shell and the metal shell form a dual protective structure. The ceramic shell has excellent insulation and high temperature resistance, which can protect internal components from high temperature and electric field interference. Together with the metal shell, it can improve heat dissipation. At the same time, the metal shell can effectively resist external physical collisions and shield electromagnetic interference, ensuring the stable operation of the chip in complex environments. This achieves the effect of efficient heat dissipation of the stacked chip. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the overall structure of this utility model; Figure 2 This is a schematic diagram of the orthographic section of this utility model; Figure 3 This is a schematic diagram of the ceramic shell of this utility model.

[0013] In the figure: 1. Substrate; 2. Conductor carrier; 3. External metal ball; 4. Silicon interposer; 5. Wafer; 6. Carbon nanotube; 7. Ceramic shell; 71. Through hole; 8. Metal shell; 81. Through block. Detailed Implementation

[0014] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0015] like Figures 1 to 3 As shown, this utility model provides a stacked packaged memory chip, including a substrate 1, a wire carrier 2 on the top of the substrate 1, an outer metal ball 3 linearly arrayed at the bottom of the wire carrier 2, located between the substrate 1 and the wire carrier 2, a silicon interposer 4 on the top of the wire carrier 2, a wafer 5 linearly arrayed on the top of the silicon interposer 4, a plurality of carbon nanotubes 6 between adjacent wafers 5 and between the silicon interposer 4 and the top wafer 5, a ceramic shell 7 on the top of the wire carrier 2, and a metal shell 8 on the outside of the ceramic shell 7.

[0016] By setting a wire carrier plate 2 above the substrate 1, and the outer metal ball 3 at the bottom of the wire carrier plate 2 being located between the substrate 1 and the wire carrier plate 2, it serves to connect the two and realize signal and power transmission. A silicon interposer plate 4 is installed on the top of the wire carrier plate 2. The silicon interposer plate 4 serves as an intermediate transition component, providing a mounting base and signal transition function for the wafers 5 stacked in a linear array on top. Several carbon nanotubes 6 between adjacent wafers 5 and between the silicon interposer plate 4 and the top wafer 5 undertake the heat dissipation task between wafers 5 and between the silicon interposer plate 4 and wafers 5, absorbing heat from the surroundings for uniform heat dissipation. At the same time, the ceramic shell 7 on the top of the wire carrier plate 2 provides basic protection for the core components such as the silicon interposer plate 4 and wafers 5, and dissipates heat through its high thermal conductivity. Meanwhile, the metal shell 8 on the outside of the ceramic shell 7 further enhances the protective performance of the overall structure, resisting external physical impacts and electromagnetic interference, and works with the ceramic shell 7 to conduct heat, achieving double-layer heat dissipation.

[0017] like Figure 3 As shown, the ceramic shell 7 has several through holes 71 on its outer side, and the metal shell 8 has a through block 81 fixedly installed on the inner side of the corresponding through holes 71. The through block 81 is snapped into the inner side of the through hole 71.

[0018] During installation, the through block 81 is snapped into the inside of the through hole 71. This snapping structure achieves a fixed connection between the ceramic shell 7 and the metal shell 8, ensuring that the metal shell 8 can stably cover the outside of the ceramic shell 7 and work together to provide protection. At the same time, the through hole 71 and the through block 81 are snapped into each other, so that the metal through block 81 comes into contact with the inside of the ceramic shell 7, thereby increasing the heat conduction area between the two.

[0019] like Figure 2 As shown, transistors are provided at the bottom of silicon interposer 4 and wafer 5 corresponding to the outer metal ball 3. There is a void between each adjacent wafer 5. Carbon nanotubes 6 are provided between the voids. Carbon nanotubes 6 are arranged in a linear array inside the voids and are located outside the outermost transistor.

[0020] The empty layer design of transistors between adjacent wafers 5 provides reasonable space for the arrangement of carbon nanotubes 6. At the same time, the linear array of carbon nanotubes 6 is located outside the outermost transistor, which avoids mutual interference between carbon nanotubes 6 and transistors. It also facilitates heat dissipation inside the chip and prevents the temperature from becoming too high due to excessive component density.

[0021] like Figure 2 As shown, through holes are provided on the outer sides of both the silicon interposer 4 and the non-top layer wafer 5, and are correspondingly arranged for connection between the silicon interposer 4 and each layer wafer 5. The through holes in the silicon interposer 4 are connected on both sides of each adjacent layer and connected to a transistor.

[0022] The corresponding through-holes provide a stable connection channel between the silicon interposer 4 and each non-top layer wafer 5, facilitating signal and power transmission between each layer wafer 5 and the silicon interposer 4, ensuring that each layer wafer 5 can respond to commands synchronously. At the same time, the through-holes on both sides of the silicon interposer 4 are connected to the transistors, increasing the flexibility and diversity of signal transmission, enabling the signals processed by the transistors to be quickly transmitted to different locations as needed, improving the efficiency of signal distribution inside the chip, and adapting to complex data processing scenarios.

[0023] Working principle and usage process of this utility model: The stacked memory chip is based on substrate 1 as the supporting structure. A wire carrier 2 is set on top of substrate 1. The outer metal ball 3 of the linear array at the bottom of the wire carrier 2 is located between substrate 1 and wire carrier 2, which plays the role of connecting the two and realizing signal and power transmission. A silicon interposer 4 is installed on the top of the wire carrier 2. The silicon interposer 4 serves as an intermediate transition component, providing a mounting base and signal transition function for the wafers (5) set on the top linear array. Several carbon nanotubes 6 between adjacent wafers 5 and between silicon interposer 4 and top wafer 5 are used to realize the task of high-speed signal transmission. At the same time, the ceramic shell 7 on the top of the wire carrier 2 plays a basic protective role for the core components such as silicon interposer 4 and wafers 5 inside. The metal shell 8 on the outside of the ceramic shell 7 further enhances the protective performance of the overall structure and resists external physical impact and electromagnetic interference.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0025] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A stacked packaged memory chip, comprising a substrate (1), characterized in that: A wire carrier plate (2) is provided above the substrate (1). An outer metal ball (3) is linearly arranged at the bottom of the wire carrier plate (2) and located between the substrate (1) and the wire carrier plate (2). A silicon interposer plate (4) is provided at the top of the wire carrier plate (2). A wafer (5) is linearly arranged at the top of the silicon interposer plate (4). A plurality of carbon nanotubes (6) are provided between adjacent wafers (5) and between the silicon interposer plate (4) and the top wafer (5). A ceramic shell (7) is provided at the top of the wire carrier plate (2). A metal shell (8) is provided on the outside of the ceramic shell (7).

2. The memory chip with stacked packaging according to claim 1, characterized in that: The ceramic shell (7) has several through holes (71) on its outer side, and the metal shell (8) has a through block (81) fixedly installed on the inner side of the corresponding through hole (71), and the through block (81) is snapped into the inner side of the through hole (71).

3. The memory chip with stacked packaging according to claim 1, characterized in that: The silicon interposer (4) and the wafer (5) are both provided with transistors corresponding to the outer metal ball (3) at the bottom. The transistors are provided with empty layers between each adjacent wafer (5), and the carbon nanotubes (6) are provided between the empty layers.

4. The memory chip with stacked packaging according to claim 3, characterized in that: The inner side of the empty layer is provided with carbon nanotubes (6) arranged in a linear array, located outside the outermost transistor.

5. The memory chip with stacked packaging according to claim 1, characterized in that: The silicon interposer (4) and the outer side of the non-top layer wafer (5) are provided with through holes, which are correspondingly arranged for connecting the silicon interposer (4) and each layer wafer (5).

6. The memory chip with stacked packaging according to claim 5, characterized in that: The perforations in the silicon intermediate plate (4) are connected on both sides of each adjacent side and connected to a transistor.

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